JP2730519B2 - Staff synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention is applicable to two types, such as working and spare.
The present invention relates to a digital wireless communication system having two systems, and more particularly to a stuff synchronization circuit for synchronizing when two systems are switched.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 2, a communication system of this type includes first and second transmission units S1 and S2 in a transmission system, and first and second reception units R1 and R2 in a reception system. , R2
You. In each transmission system, an asynchronous signal is converted into a synchronous signal to perform multiplexing, and a stuff synchronous circuit is used to take timing at this time.

FIG. 4 is a block diagram of an example of a conventional stuff synchronization circuit. This stuff synchronization circuit is used to convert a plurality of asynchronous signals into synchronous signals, multiplex them, and transmit them. A stuff synchronization circuit (hereinafter, referred to as a first stuff synchronization circuit) ST1 of the first transmission system is provided with a first clock generator 203 and a first phase comparator 201, and the first clock generator 203 generates the first clock generated by the first clock generator 203. The phase of the clock 21 is compared with the phase of the clock of the asynchronous signal 10, and when the phase difference becomes equal to or greater than a predetermined value, the stuff request signal 24 indicating the timing of inserting the stuff pulse for skipping the first clock is output. It sends one click lock generator 203. As a result, the first clock generator 203 outputs the first clock 21 with one bit missing.

Similarly, a stuff synchronization circuit (hereinafter, referred to as a second stuff synchronization circuit) ST2 of the second transmission system is provided with a second clock generator 204 and a second phase comparator 202.
The phase of the second clock 22 generated by the clock generator 204 is compared with the phase of the clock of the asynchronous signal 10, and when the phase difference becomes equal to or greater than a predetermined value, the stuff pulse of the second clock 22 is omitted. A stuff request signal 25 indicating the insertion timing is sent to the second clock generator 204. Accordingly, the second clock generator 204, and outputs a second clock 2 2 became missing bit teeth.

The stuff request signal is multiplexed with a main signal by a multiplexing circuit (not shown) and transmitted to a receiving system. Then, the receiving system performs destuffing based on the received stuff request signal, and converts the synchronous signal into an asynchronous signal.

[0006]

In such a conventional stuff synchronous circuit, the frame timing at the time of converting an asynchronous signal into a synchronous signal and performing multiplexing differs between the first transmission system and the second transmission system. Therefore, for example, as shown in FIG. 5, when switching from the first transmission system to the second transmission system, there is a possibility that the same bit of received data may be duplicated or missing in the receiving unit. Also, the first clock and the second clock
Since the clocks are not synchronized, the stuff request signal output from each phase comparator has a different stuffing pulse timing, and a stuffing frame timing difference occurs between the first transmission system and the second transmission system. become.

In this case, it is conceivable to synchronize the first clock and the second clock. However, if the phases of the first clock and the second clock are different, the stuffing timing is different. For such a difference in timing, stuffing is usually performed once every ten or more frames, but as shown in FIG. 6, at the moment when switching from the first transmission / reception system to the second transmission / reception system is performed. In the receiving unit, destuffing occurs for two consecutive frames, and there is a possibility that the same bit of received data is duplicated or missing.

The stuff synchronization is described in, for example, JP-A-61-224740 and JP-A-61-1252.
No. 41 and Japanese Patent Application Laid-Open No. 59-4242 disclose techniques of a stuff synchronization system and a synchronizer. In these systems, the phase comparison result between a write clock and a read clock is randomly determined for one system. The technique relates to a technique of spreading low-frequency jitter in the stuff pulse insertion waiting time by changing the frequency, effectively performing jitter suppression on the receiving side, and preventing deterioration of transmission quality.
It does not have a function for improving the transmission quality when switching between the two communication systems as described above.

[0009]

SUMMARY OF THE INVENTION An object of the present invention is to synchronize frame timing and stuff timing at the time of switching between two communication systems at the same time, thereby preventing bit duplication or loss on the receiving side and improving transmission quality. Another object of the present invention is to provide a stuff synchronization circuit.

[0010]

SUMMARY OF THE INVENTION A stuff synchronization circuit according to the present invention includes a clock generator and a clock generated by the clock generator as an asynchronous signal for each of the first and second systems selectively connected. A phase comparator that compares the phases and outputs a stuff request signal, and a selector that selects the stuff request signal of the own system and the stuff request signal of the other system and sends the stuff request signal to the clock generator of the own system are provided. A switching signal for switching between the first system and the second system is input to each selector and the clock generator, and a clock and a frame pulse of another system are mutually input to each clock generator. A configuration in which a stuff request signal of the selectively connected system is selected and output, and the clock generator operates so that its own system clock and frame pulse are synchronized with the selectively connected system clock and frame pulse. Is done.

Here, the clock generator has a PLL structure, and when the own system is selectively connected, outputs a self-generated clock based on a stuff request signal of the own system and outputs a frame pulse of the own system. Output, when the other system is selectively connected, outputs a clock generated in phase with the clock of the other system based on the stuff request signal of the other system, and outputs a frame whose phase is adjusted to the frame pulse of the other system. It is configured to output a pulse.

[0012]

When the other system is selected, the own system clock generator is synchronized with the clock generated by the other system clock generator and based on the stuff request signal from the other system phase comparator. Is output, and a frame pulse whose phase is adjusted to the frame pulse from the clock generator of another system is output. Therefore, the frame timing and stuff timing of the own system can be matched with those of the other system,
Even when switching from the other system to the own system, duplication of the same bits of received data and loss of bits due to a timing shift are prevented when the receiving unit of each system performs destuffing.

[0013]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a stuff synchronization circuit according to the present invention. As shown in FIG. 2, a first transmission unit S1 in a digital wireless communication system including a first transmission / reception system and a second transmission / reception system And the stuff synchronization circuits ST1 and ST2 in the second transmission section S2. The first stuff synchronization circuit ST1 of the first transmission unit S1 includes a first clock generator 10 having a PLL configuration for generating a first clock 11.
3 and the first clock generated by the first clock generator 103.
A first phase comparator 101 compares the phase of the clock 11 with the clock 10 of the asynchronous signal, and a first selector 105 selects a stuff request signal input to the first clock generator 103.

Similarly, the second stuff synchronization circuit ST2 of the second transmission unit S2 generates a second clock 12
A second clock generator 104 having an LL configuration, a second phase comparator 102 for comparing the phase of the second clock 12 generated by the second clock generator 104 with the clock of the asynchronous signal 10, and the second clock generator 102 And a second selector 106 for selecting a stuff request signal input to the device 104.

The first and second phase comparators 101, 1
02 receives the same asynchronous signal 10. Further, as described later, the first and second phase comparators 101 and 102
Are output to first and second selectors 105 and 106, respectively, and the stuff request signals 16 and
17 are first and second clock generators 103 and 1 respectively.
04. Further, here, a switching signal 13 for switching the first and second transmission systems is provided.
Are input to the first and second selectors 105 and 106 and the first and second clock generators 103 and 104, and the selection operation in each of the selectors 105 and 106 and the clock generation operation in each of the clock generators 103 and 104 are performed. Configured to control. Further, between the first clock generator 103 and the second clock generator 104, the first clock 11 and the second clock 12 generated respectively are configured to be input to each other, and Frame pulse 1 for composing a frame in the main signal
8, 19 are mutually transferred.

According to the above configuration, in the first stuff synchronous circuit ST1, the first phase comparator 101 compares the clock of the asynchronous signal 10 with the phase of the first clock 11 from the first clock generator 103, When the phase difference exceeds a predetermined value, a stuff request signal 14 indicating the stuff pulse insertion timing is output. Similarly, in the second stuff synchronous circuit ST2, the clock of the asynchronous signal 10 in the second phase comparator 102 and the second clock generator 1
The phase of the second clock 12 from 04 is compared, and when the phase difference becomes equal to or greater than a predetermined value, a stuff request signal 15 indicating the stuff pulse insertion timing is output.

The stuff request signals 14 and 15 from the phase comparators 101 and 102 are input to first and second selectors 105 and 106, respectively. Each selector selects the stuff request signal of the connected system based on the input switching signal 13 based on whether the currently connected system is the first transmission system or the second transmission system. For example, when the first transmission system is currently selected and connected, the first selector 105 and the second selector 106 respectively select the stuff request signal 14 from the first phase comparator 101, and The stuff request signal is sent to the first and second clock generators 103 and 104, respectively. Conversely, when the second transmission system is selected and connected, the first and second selectors 10
Reference numerals 5 and 106 respectively denote stuff request signals from the second phase comparator 102 to the first and second clock generators 103 and 10.
4

In the first clock generator 103,
When the first transmission system is selectively connected based on the input switching signal 13, the first clock 11 generated by its own clock generator 103 is output as it is. Further, when the second transmission system is selectively connected, a clock synchronized with the second clock 12 is generated by a PLL operation using the second clock generated by the second clock generator 104 as a reference clock, and this is generated. Output as the first clock 11. Thereby, the first clock 11 is synchronized with the second clock 12, and the phases are matched. Similarly, the second
In the clock generator 104, its own clock when the second transmission system is selected connected generated as the second clock 12, when the first transmission system is selected connected from the first clock generator 103 first A clock having the same phase synchronized with the clock 11 is generated and output as the second clock 12.

At this time, the first and second clock generators 103 and 104 have the first and second selectors 10 and 10 respectively.
Stuff request signal 1 selected and output by 5,106
The first and second clocks 11 and 12 that are respectively output are made inconsistent based on 6 and 17. Therefore, when the first transmission system is selectively connected, the second clock 12 from the second clock generator 104 is the first clock 1
1 and output as a stuffed clock, and when the second transmission system is selectively connected,
The first clock 11 from the first clock generator 103 is synchronized with the second clock 12 and output as a stuffed clock. As a result, the stuff timings of the first and second stuff synchronization circuits ST1 and ST2 match.

Also, frame pulses 18, which constitute a frame for multiplexing a plurality of main signals and a plurality of auxiliary signals,
Also in 19, the output is performed between the first and second clock generators 103 and 104, and the output timing is adjusted by using the frame pulse on the transmission / reception side selected based on the switching signal 13. , The frame timings are matched.

[0021] Consequently, as shown in FIG. 3, a first transmit unit in a second transmission unit, the synchronization of the frame timing for radio transmission are matched, and the staff timing is matched. Therefore, even when switching between the first transmission system and the second transmission system, duplication of the same bits of received data and loss of bits due to a timing shift do not occur when each receiver performs destuffing. , Instantaneous interruption switching can be realized.

[0022]

As described above, according to the present invention, the stuff request signal of the own system and the stuff request of the other system are provided to each of the first and second systems selectively connected together with the clock generator and the phase comparator. A selector for selecting a signal and transmitting the selected signal to the clock generator of the own system; a switching signal for switching between the first system and the second system is input to each selector and the clock generator; Since clocks of other systems and frame pulses are mutually input to each clock generator,
When the other system is selected, the own system clock generator outputs a clock synchronized with the clock generated by the other system clock generator and based on the stuff request signal from the other system phase comparator. A frame pulse whose phase is adjusted to the frame pulse from the clock generator of another system is output. Therefore, the frame timing and the stuff timing of the own system can be made coincident with those of the other system, and even when switching from the other system to the own system, the same bit of the received data due to a timing shift when the receiving unit of each system performs destuffing. Overlap and bit loss are prevented, and the effect of improving transmission quality is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a stuff synchronization circuit according to the present invention.

FIG. 2 is a block diagram of a wireless communication system to which the present invention is applied.

FIG. 3 is a diagram showing frame timing and stuff timing of first and second transmission / reception systems according to the present invention.

FIG. 4 is a block diagram of an example of a conventional frame synchronization circuit.

FIG. 5 is a diagram showing frame timing and stuff timing in the first and second transmission / reception systems in the related art.

FIG. 6 is a diagram showing a frame timing and a stuff timing in the conventional first and second transmission / reception systems.

[Explanation of symbols]

 Reference Signs List 101 First phase comparator 102 Second phase comparator 103 First clock generator 104 Second clock generator 105 First selector 106 Second selector 10 Asynchronous signal 11 First clock 12 Second clock 13 Switching signal 14, 15 16 , 17 Staff request signal 18, 19 Frame pulse

Claims (3)

(57) [Claims] 1. A digital radio communication system comprising a first system and a second system for selectively connecting and communicating with each other, each system includes a clock generator and a clock generator generated by the clock generator. A phase comparator for comparing the phase of the generated clock with the asynchronous signal to output a stuff request signal, and a selector for selecting the stuff request signal of the own system and the stuff request signal of the other system and transmitting the stuff request signal to the clock generator of the own system A switching signal for switching between the first system and the second system is input to the selector and the clock generator, and a clock and a frame pulse of another system are mutually input to each clock generator. The selector selects and outputs the stuff request signal of the selectively connected system, and the clock generator selects the own system clock and the frame pulse of the selectively connected system clock. And a stuff synchronization circuit operable to be synchronized with a frame pulse. 2. A clock generator having a PLL configuration, outputs a self-generated clock based on a stuff request signal of the own system when the own system is selectively connected, and outputs a frame pulse of the own system. When the other system is selectively connected, a clock that is generated in phase with the clock of the other system based on the stuff request signal of the other system is output, and a frame pulse that is in phase with the frame pulse of the other system is output. 2. The stuff synchronization circuit according to claim 1, wherein: 3. A digital radio communication system comprising a first system and a second system for selectively connecting and communicating with each other, wherein the first system includes a first clock generator and the first clock. A first phase comparator for comparing the phase of a clock generated by a generator with an asynchronous signal and outputting a stuff request signal, and selecting a stuff request signal of a first system and a stuff request signal of a second system. A first selector for transmitting the clock to the first clock generator; a second system for comparing a phase of a clock generated by the second clock generator with an asynchronous signal by using a second clock generator; A second phase comparator for outputting a stuff request signal; a second stuff request signal for the second system and a stuff request signal for the first system;
A second selector for sending to the clock generator;
A switching signal for switching between the first system and the second system is input to the first and second selectors and the first and second clock generators, and the first and second clock generators are input to the first and second selectors and the first and second clock generators. A clock generator receives a clock of another system and a frame pulse mutually, and the first and second selectors select and output a stuff request signal of a system which is selectively connected, and generate the first clock. When the first system is selectively connected, the comparator outputs a first clock based on a stuff request signal from the first phase comparator selected by the first selector, and outputs a frame pulse of the first system. When the second system is selectively connected, the second selector selected by the first selector
Outputting a first clock based on the stuff request signal from the phase comparator and the second clock from the second clock generator, and outputting a frame pulse synchronized with the frame pulse from the second clock generator; The two clock generator outputs a second clock based on the stuff request signal from the second phase comparator selected by the second selector when the second system is selectively connected, and outputs the second system frame. A second clock based on a stuff request signal from the first phase comparator selected by the second selector and a first clock from the first clock generator when the first system is selectively connected; And a frame pulse synchronized with the frame pulse from the first clock generator.