JPH0453138B2 - - Google Patents

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a loop time division multiplex data way communication system, and in particular to a method for reducing loop transmission delay by switching control data memory used in time division multiplex communication. The present invention relates to this type of communication system that uses compensation.

[Technical Background of the Invention] FIG. 4 shows the configuration of a conventional loop type time division multiplex data way. In FIG. 4, communication controllers No. 1 to No. n are connected in a loop through a transmission path 1, and data is transmitted and received. communication controller
The transmission signal sent from No. 1 is received after going around the loop and sent out again, so the transmission delay of data going around the loop is always the length of the sent data, that is, an integer of data frames. It has to be doubled. However, it is difficult to match the transmission path length to the data transmission delay so that it becomes an integral number of data frames, and it also changes depending on external conditions. Therefore, it is known to provide a loop delay compensation circuit at one location on the loop to control the round trip delay of the loop so that it is always an integral multiple of the data frame.

Generally, loop delay compensation is performed using a delay controller consisting of a counter, etc., with a delay element 4 such as a memory or a shift register interposed between the receiver 2 and the transmitter 3, as shown in FIG. 5. The delay controller 5 receives the signal from the receiver 2 and also receives the signal from the transmitter 3 from the signal line 6.
It also receives a transmission timing signal. In such a circuit, the receiver 2 performs reception clock regeneration and data identification and regeneration of the received signal, and the receiver 2 sends reception timing signals such as the reception data clock and reception data frame signal to the delay controller 5. At the same time, an input data signal is sent to the delay element 4. The delay controller 5 uses the reception timing signal and the transmission timing signal on the signal line 6 to send to the delay element 4 a delay time signal for making the round trip delay of the loop an integral multiple of the data frame. The delay element 4 sends an output data signal to the transmitter 3 in response to a signal from a delay controller 5, and the transmitter 3 outputs a transmission signal to a transmission line in response to a transmission timing signal on a signal line 6.

[Problems with the Background Art] However, the loop delay compensation described above requires independent hardware such as data memory, and in order to operate adaptively to changes due to arbitrary loop lengths and external conditions, delay elements and delay controls are required. However, there are disadvantages in that the circuit scale of the device increases, and the cost and hardware burden increase.

[Object of the Invention] The present invention has been made in view of the above-mentioned conventional difficulties, and it is possible to reduce the loop transmission delay in a loop type time division multiplex data way by using a switching control data memory commonly used in time division multiplex communication. It is an object of the present invention to provide a loop-type time-division multiplex dataway communication system that reduces the circuit scale and reduces the cost and burden on hardware.

[Summary of the Invention] FIG. 1 shows loop delay compensation in a loop time division multiplex dataway communication system to achieve the above object. Of these, data memory 10, address bus 11 and data bus 1
2 is performed by using existing memory and bus used for switching control in time division multiplex communication. In FIG. 1, a receiver 13 sends a reception timing signal to a reception timing control circuit 14, and also sends reception data to a data memory 10 via a data bus 12. Further, from the reception timing control circuit 14,
A received data address signal is sent to data memory 10 via address bus 11 .

On the other hand, a transmission timing address signal is sent from the transmission timing control circuit 15 to the transmission exchange control circuit 16, and a transmission data address signal is sent from the transmission exchange control circuit 16 to the data memory 10 via the address bus 11. Also, data memory 1
Transmission data is sent from 0 to the transmitter 17 via the data bus 12, and the transmission timing control circuit 15
A transmission signal is output from the transmitter 17 in response to a transmission timing signal from the transmitter 17.

That is, in this method, first, the received signal is sent to the receiver 13.
, the signal clock is regenerated, the received data signal is identified and reproduced, and the data frame information is regenerated, and the signal clock and data frame information receive timing signals are sent to the receive timing control circuit 14 via the data bus 12. The received data signal is sent to the data memory 10. Upon receiving the reception timing signal, the reception timing control circuit 14 sends a reception data address signal to the data memory 10 via the address bus 11 in order to instruct the address at which the reception data signal should be stored in the data memory 10. Signal data memory 1
0 for each frame period.

On the transmission side, the transmission timing control circuit 15 sends a transmission timing address signal to the transmission exchange control circuit 16, and the transmission exchange control circuit 16 uses the transmission data address signal indicating the storage address of the data to be transmitted in the data memory 10 as an address. It is sent to the data memory 10 via the bus 11 to specify it, and the data at the address is read out at an integral multiple of the frame period. The read data is sent to the transmitter 17 via the data bus 1, and the transmitter 17 outputs it as a transmission signal in response to a transmission timing signal from the transmission timing control circuit 15. In this way, the received data is transmitted after being delayed by an integral multiple of the frame period.

[Embodiments of the Invention] Preferred embodiments of the present invention will be described below with reference to FIGS. 2 and 3.

The loop time division multiplex dataway communication system of the present invention is realized by a loop delay compensation circuit as shown in FIG. In FIG. 2, a line receiver 20 is connected to a bit synchronization circuit 21 and a code demodulation circuit 22, and from the code demodulation circuit 22, a serial to parallel conversion shift register 23 is connected to a frame synchronization circuit 24, a data latch 25, and a 3-state buffer 26. connected to. Further, the bit period circuit 21 is connected to a code demodulation circuit 22, a serial/parallel conversion shift register 23, and a frame synchronization circuit 24, thereby forming the receiver 13 in FIG.

The reception timing control circuit 14 in FIG. 1 is constructed by connecting a reception frame counter 30, a reception address conversion circuit 31, a data latch 32, and a three-state buffer 33. Further, the bit synchronization circuit 21 and the frame synchronization circuit 24 are each connected to a received frame counter 30.

The transmission timing control circuit 15 in FIG.
connected to and configured. The control logic circuit 43 is connected to various controllers in order to generate and send out signals synchronized with the timing of transmission.

The transmission exchange control circuit 16 shown in FIG. 1 is configured by connecting a control memory 50 and a three-state buffer 51. That is, the transmission address conversion circuit 4
2 to the control memory 50, and also to other internal circuits via a control memory address bus for time division. Also,
The control memory 50 is connected to other internal circuits via a control memory data bus for time sharing.

The transmitter 17 in FIG. 1 is composed of a parallel-to-serial conversion shift register 60 and a line driver 61. It is also connected from the clock generator 40 to the line driver 61.

The operation of the loop delay compensation circuit constructed in this manner will be explained with reference to the time chart shown in FIG. 3 together with FIG. 2.

The received signal is input to the line receiver 20, and the bit synchronization circuit 21 extracts the bit clock component of the received signal to reproduce the bit synchronization clock. On the other hand, the received signal is demodulated into an information code in the code demodulation circuit 22 to obtain a demodulated received signal A as shown in FIG. Here, f of the demodulated received signal A
D(f, k) the kth word of the frame
One word is made up of 8 bits, and symbols 0 to 7 are attached. The demodulated received signal A is converted by the serial/parallel conversion shift register 23 into serial/parallel shift register outputs B1 to B8. A frame synchronization circuit 24 detects a word for each synchronization frame period from the signals of the serial and parallel shift register outputs B1 to B8, and obtains a frame synchronization signal. This frame synchronization signal and the reception timing signal of the bit synchronization clock drive a reception frame counter 30 to obtain a counter output representing the timing within a frame of the reception signal. on the other hand,
The data latch 25 latches 1-bit signals of the serial-parallel shift register outputs B1 to B8,
When the data latch 25 outputs D(f,k)0 to 7 for each frame period, the reception frame counter 30 outputs a signal representing the reception timing. This output signal is converted by the reception address conversion circuit 31 into an address signal for the data memory 10 storing the reception data, and the data latch 3
A received data address signal C is applied to the data memory 10 via the data memory 10 via the data memory 10. Here, data latch 2
Numerals 5 and 32 are latches for absorbing timing differences between transmission and reception, which cause a delay of less than one bit cycle (not shown), and 3-state buffers 26 and 32.
33 is the data bus 12 and address bus 11
This is for time-sharing use. In Figure 3, the received data starts with address An, and
The kth word is stored at An+kth, and at time _t2 , the received data D(f,k)
is stored in the An+kth position of the data memory 10.

Next, a case will be described in which the data stored in the data memory 10 is retrieved and transmitted after a certain period of time. First, the transmission frame counter 41 is driven by the output clock of the clock generator 40, and the Ak is output as the transmission frame counter output D, which is the timing for transmitting the k-th word. This output Ak generates a control signal for each part in the control logic circuit 43, and the control signal is output in synchronization with the transmission timing of the transmitter 7.
Further, the output Ak is converted by the transmission address conversion circuit 42 into an address for storing transmission exchange control data in the control memory 50, and this reads out the transmission data address signal E of the control memory 50. The control memory 50 realizes exchange processing by selecting an arbitrary address in the data memory 10 for transmission data according to its stored data, but when transmitting received data as is, the transmission data address The signal E becomes the An+k address where the kth word of the received signal is stored when the transmission frame counter output D is Ak. This transmission data address signal E is time-divisionally processed by the three-state buffer 51 and input to the data memory 10, where the transmission data at the specified address is read. The transmission data read from the data memory 10 is loaded in parallel into the parallel-to-serial conversion shift register 60 at time _t3 , where it is shifted by the transmission bit clock to obtain the parallel-to-serial conversion shift register output F. Then, the signal is code-modulated by the line driver 61, and the transmission data is output to the transmission line in accordance with the transmission timing signal from the clock generator 40.

That is, the time T ₀ from time t ₁ to _{t 4} in FIG.
represents the delay from the 0 signal of D(f,k) in the demodulated received signal A to the output F of the parallel-to-serial conversion shift register, and most of the delay is caused by the data memory 10. Furthermore, since the time from time t ₄ to _{t 5} is T ₁ and the frame period is T ₂ (=T ₀ +T ₁ ), the parallel-to-serial conversion shift register output F passes through the line driver 61 to other communication controllers. The time T ₃ it takes to go around the transmission loop containing the signal and return as the demodulated reception signal A via the line receiver 20 and the code demodulation circuit 22 is calculated by adding the time T ₁ to an integral multiple (1) of the frame period T ₂ . Become something. That is, the time T ₃ becomes T ₃ =T ₂ ×I+T ₁ . Therefore, the round trip delay of the entire transmission loop
T ₄ is the time from the code demodulation circuit output (demodulated received signal A) to the parallel-serial conversion shift register output F
It is equal to the sum of T ₀ and the delay time T ₃ from the parallel/serial conversion shift register output F to the code demodulation circuit output. Therefore, T ₄ = T ₀ + T ₃ = T ₀ + T ₂ I + T ₁ . Here, since T ₂ =T ₀ +T ₁ , T ₄ =T ₂ +T ₂ I=T ₂ (I+1), and it can be seen that the loop delay compensation function is realized.

In the above embodiment, the exchange control function is shown in which the reception data address signal C is fixed and the transmission exchange control circuit 16 is used to select the transmission data from the data memory 10 by the transmission data address signal E. However, other methods may be used. Similar effects can also be obtained by, for example, fixing the transmission data address signal E and selecting the reception data address signal C.

[Effects of the Invention] As is clear from the above embodiments, according to the present invention, the loop transmission delay in a loop type time division multiplex data way can be reduced by using an exchange control data memory commonly used in time division multiplex communication. By adjusting the transmission delay time using the frame period of the exchange control data memory, the buffer memory for adjusting the transmission delay time can be omitted. Furthermore, by storing received data and reading out transmitted data, the circuit scale can be reduced and the cost and burden on hardware can be reduced.

For example, one communication controller in the data way is installed in the master controller, and the other communication controller is installed in the child controller, and all exchange processing including the transmission timing is controlled by the received data address signal (C). If control is performed, the parent controller and slave controllers can have similar circuit configurations, making it easy to share most of the hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing loop delay compensation in the loop time division multiplex dataway communication system of the present invention, and FIG. 2 is a circuit block diagram showing a preferred embodiment of the loop delay compensation circuit in the communication system of the present invention. 3 is a time chart showing the timing of signals in each part of the block diagram in FIG. 1 is a block diagram illustrating conventional loop delay compensation in a dataway of FIG. 10...Data memory, 13...Receiver, 14
... Reception timing control circuit, 15 ... Transmission timing control circuit, 16 ... Transmission exchange control circuit, 1
7...Transmitter.

Claims (1)

[Claims] 1. The received data is stored in an exchange control data memory used for an interface with a multiplexed transmission line in digital time division multiplex communication for each frame period by specifying an address using a received data address signal, and the exchange control data is Among the data stored in the memory, data at a predetermined address is read out at an integer multiple of the frame period using a transmission data address signal, and the data read from the exchange control data memory is transmitted using a transmission timing signal to read out the data at a predetermined address using a transmission data address signal. A loop time division multiplex data way communication system, characterized in that the data is transmitted with a delay at an integer multiple of the frame period.