SU1159170A1 - Multichannel device for transmission of digital information - Google Patents

Abstract

A MULTI-CHANNEL DEVICE FOR TRANSMITTING DISCRETE INFORMATION, containing reception blocks, a transmission block, a RAM, a synthesizer, a counter, a register, and clock generators, the outputs of the receive blocks are unified and connected to the information input of the synthesizer and the information input of the register, the clock input which is combined with the synchronizing input of the counter and connected to the output of the synthesizer, the control input of which is connected to the output of the counter, the write-read inputs of the operating unit The keys are connected to the read / write outputs of the synthesizer, counter and register, the first output of the clock generator is connected to the address inputs of the receiving units and the address input of the transmission unit, and the second output of the clock generator is connected to the clock inputs of the main memory unit and the transmission unit, different By the fact that, in order to improve noise immunity, a control pulse shaper and serially connected dangerous interval shaper, an analyzer and a block controlled delay, the information input of which is connected to the information output of the register, the output of the controlled delay block is connected to the information input of the transmission unit, the first output of the generator. (L synchronizing pulses are connected to the combined synchronizing inputs of the control pulse generator, the analyzer and the control delay block, the auxiliary output of the transmission unit is connected to the input of the control pulse generator, the output of which is connected to the second analyzer input, the third input of which is connected to the additional pulse the output of the counter, and the input of the signal conditioner of the dangerous terminal is connected to the additional output of the synthesizer.

Description

11 The invention relates to radio engineering and communications and can be used in multichannel data transmission systems, telegraphy and telemechanics. The purpose of the invention is to improve the premise resistance. Fig. 1 shows a structural electrical circuit of a multichannel device for transmitting discrete information; Fig. 2 is a structural electrical circuit of an example of making a dangerous interval signal generator; Fig. 3 is a structural electrical circuit of an exemplary embodiment of the analyzer; in fig. 4 shows the electrical circuit diagram of an example of the execution of a control driver — mp; in fig. 5 - structures on the electrical circuit of the controllable delay unit; The multi-device for transmitting discrete information contains reception units i, generator 2 clock pulses, main memory unit 3, synthesizer 4, counter 5, register 6, transfer unit 7, driver 8 signal of the dangerous interval, consisting of the first, second and third inverters 9-1I and the first and second elements 12 and 13 | (Fig. 2), an analyzer 14, consisting of a memory element 15, a register 16, an inverter 17, a first, second, a third thereof, and a fourth element 18-21 And (Fig. 3), a driver 22 of control pulses, consisting from equivalence unit 23, first and second elements 24 and 25, OR element 26 And and inverter 27 (FIG. 4), and controllable delay unit 28 consisting of the first inverter 29, first and second memory elements 30 and 31, register 32, the second inverter .33 and block 34 keys. A multichannel device for transmitting discrete information operates as follows. The information received at the input of blocks 1 is converted by the overlay method into an isochronous binary signal. Signals received in different blocks 1 are combined into one common group binary signal. The synthesizer 4, the counter 5, the register 6, and the block 3 associated with them, process the group signal, ensuring the regeneration of each individual start-stop signal. Block 7 generates 02 signal, prednaznachenny for transmission over a communication channel. In this device, the speed at which gating pulses are generated during the regeneration process and the speed at which the bits are transmitted, which are provided to one channel in a signal generated in a linear block, do not coincide. The gating pulse rate is set equal to the nominal transmission rate in the individual channel. This makes it possible to position the pulses exactly in the middle of all the packages of the start-stop mark. The speed of the bits provided to one channel in a signal generated in a linear block is set higher than the nominal one. Due to this, it is possible to transmit signals from real sources, in which the speed can deviate from the nominal both in a smaller and in a larger direction. The matching of the speeds of the gating pulses and bits provided to one channel is carried out again by block 28, analyzer 14, driver 8 and driver 22. In this case, redundant bits provided to one channel are used to extend the stop of one or another start-stop sign 22 receives from the oscillator 2 the address of the channel interval, and from block 7 the channel number whose bit is currently being output to the device. At the output of the imaging unit 22, pulses are created which mark the points in time at the positions of each channel, at which information of this channel is output to the device. The imaging unit 8 receives from the synthesizer 4 code combinations showing the state in which the synthesizer 4 is located, which is set to the zero state by a stop start transition, and then switches to the next state once per clock interval and marks the middle of the burst. The shaper of the 8th mark, a dangerous interval, usually keeps zero on its output. If a combination is received at its input from synthesizer 4, indicating that the synthesizer is in a delayed state relative to the middle of the night, then

31

The output of the driver 8 is set to one.

At the input of the analyzer 14, the dangerous interval marks are received, the checking pulses and the signal from the counter 5. This signal takes the value of the transmitter, if the counter is in the first state, it means that the starting parcel is received). The analyzer 14 contains a memory element 15, the volume of which is equal to the number of individual channels of the multichannel transmission device. If in any channel interval at the inputs of the analyzer 14 three units coincide, then a unit is recorded in the corresponding cell of the memory element 15. If the checking pulse coincides with the first state of the counter 5, and from the generator, 8 is zero at this time, then zero is recorded in the corresponding cell of the memory element 15 If there is a post on some channel uz .1

91704

the start-stop sign is then zero or one is recorded in its starting package in the corresponding cell of the memory element 15 of the analyzer 14, and in the remaining sign packages this value remains unchanged. The content of the memory element 15 of the analyzer 14 is continuously read to its output and controls the operation of the block 28 .

10 If at the output of the analyzer 14 the voltage takes the value of a logical zero, then unit 28 switches the regenerated signal from register 6 to its output; If the output

t5 analyzer 14 appears unit, then block 28 switches to its output the regenerated signal, delayed by the duration of half the parcel. The use of the invention allows to improve the noise immunity of the transmitted discrete signal due to the correction of the position of its fronts during regeneration, which can reach 48%. YY

43

ten

KSj70ff {/ f

Deloko

 ;

23

Omsonoj

phi.2

(rig, 3

7 g

kVlshgu1

YP

zs

tpuz. From fa. 2 BmSnem ut

Claims (1)

MULTI-CHANNEL DISCRETE INFORMATION TRANSMISSION DEVICE, comprising receiving units, a transmitting unit, a random access memory unit, a synthesizer, a counter, a register and synchronizing pulse generators, the outputs of the receiving units being combined and connected to the synthesizer information input and the register information input, the synchronization input of which is combined with a synchronizing input of the counter and connected to the output of the synthesizer. the control input of which is connected to the output of the counter, 'write-read inputs of the RAM block with are the same as the synthesizer, counter and register write-read outputs, the first output of the synchronizing pulse generator is connected to the address inputs of the receiving units and the address input of the transmission unit, and the second output of the synchronizing pulse generator is connected to the clock inputs of the RAM block and the transmission unit the fact that, in order to increase the noise immunity, a control pulse shaper and a dangerous interval signal shaper, an analyzer and a controlled The latency, the information input of which is connected to the information output of the register, the output of the controlled delay unit is connected to the information input of the transmission unit, the first output of the synchronizing pulse generator is connected to the combined synchronizing inputs of the control pulse generator, the analyzer and the controlled delay unit, the additional output of the transmission block is connected to the input control pulse shaper, the output of which is connected to the second input of the analyzer, the third input of which is connected to an additional the output of the counter, · and the input of the signal conditioner of the dangerous interval is connected to the additional output of the synthesizer. -SU „„ 1159170 1 1 159'1