SU1598196A1 - Device for transmitting discrete information - Google Patents

Abstract

The invention relates to a technique for transmitting discrete information and can be used in communication systems, data transmission and input-output information of a computer. The aim of the invention is to increase the amount of information transmitted. The goal is achieved by introducing into the main channel 3 the first 9 and second 10 elements AND, and in each additional channel a 4-dial block 5, the first 9 and second 10 elements AND and the first 6 and second 7 elements OR connected in series. Due to the fact that the bits of the code combinations of various messages recorded in the shift registers 8 are input to the communication line in parallel, the device provides high information content in the transmission of messages.

Description

The invention relates to techniques for transmitting discrete information and can find application in communication systems, data transfer and input / output of computer information

The aim of the invention is to increase the amount of transmitted information.

The drawing shows a structural electric circuit of the device.

The device contains a clock generator 1, a code converter 2, a main channel 3 and additional channels 4, and each main 3 and additional 4 channels contain a dial-up block 5, the first 6 and second 7 OR elements, shift register 8, the first 9 and second 10 elements AND.

- A device for transmitting discrete information works as follows "

From typesetting blocks 5, the signals of bits of code combinations of various messages are supplied to the inputs of shift registers 8 and high potentials are sent to the second inputs of elements And 9 from the gate outputs of typesetting blocks 5, which signal the readiness of code combinations of typesetting blocks 5 for transmission. The first pulse, which came from the output of the clock generator 1 to the third inputs of the elements And 9 in the presence of a high potential at the second inputs of the elements And 9 and a low potential at the first inputs of the elements And 9, passes through the elements I9 to the control inputs of the shift registers 8 and allows ( produces) a record in the latest code combinations operating at their inputs. In this case, units are written to the upper bits of the shift registers 8, zeros are written to the lower bits of the shift registers 8, and the code bits sent from the outputs of the typesetting blocks 5 to the inputs of the shift registers 8 are written to the remaining bits. As soon as the information to be transmitted is recorded in the shift registers 8, a high potential appears at the output of the upper bits of the shift registers 8 and the corresponding first elements of OR 6. The high potential from the outputs of the upper digits of the shift register 8 is supplied to the blocking inputs of the corresponding typesetting units 5, so that the code combinations dialed earlier in the typesetting units 5 are reset and permission is given for a set of new code combinations to be sent messages, 'High potential from the outputs of the first elements OR 6 arrives at the first inputs of the corresponding elements And 9 and · 10, so that the passage of clock pulses through the first elements of And 9 is prohibited and the passage of clock pulses is allowed through the second elements of AND 10. From the outputs of the lower bits of the shift registers 8, the code messages of the lower bits of the code combinations recorded in the shift registers 8, through the corresponding second elements of OR 7, go to the inputs of the converter 2 of the on-off code in 2 ^П - position (where η is the number of registers 8 shift in the device). Due to the fact that the shift of information in the shift registers 8 occurs in phase and synchronously (simultaneously) with each shift clock, η-bits of a two-position code are received at the inputs of the code converter 2. Code converter 2 converts η-input bits of a two-position code into one bit of a 2 ”-position code. From the output of the code converter 2, the signal of the 2 ^h- position code enters the communication channel.

When issuing from the outputs of the lower bits of the shift registers 8 the last unit recorded at the beginning of the transmission cycle to the upper bits of the shift registers 8, zeros are recorded in all bits corresponding to the shift registers 8. At the output of the corresponding first elements of OR 6 low potentials are established that prohibit the passage of clock pulses through the corresponding second elements of AND 10, ensure the establishment of a high potential at the outputs of the corresponding second elements of OR 7 and allow the passage of clock pulses through the corresponding first elements of AND 9 when installed on second inputs of the last high potential "

Upon receipt from the typesetting units 5 to the inputs of the respective shift registers 8 and the second inputs of the corresponding first elements AND 9 code combinations, the device operation cycle is repeated. Due to the fact that the signals of bits of codewords of different messages recorded in the shift registers 8 are inputted to the communication line in parallel, ^'5 1,598,196 device provides high information when sending a message.

The code positioning of the code converter 2 is selected based on the possibilities of practical technical implementation of the communication channel for a given reliability of message transmission and is provided by the device parameters when transmitting discrete information N = 2 where N is the required code positioning; η is the number of shift registers 8 in the device.

The number of memory cells (bits) in each shift register 8 can be arbitrary and contain a low-order cell for recording the start message (zero), a high-order cell for recording the stop message (unit) and a cell for recording information bits of message code combinations (information bit depth code combinations is determined by the type of transmitted messages). Maximum total information transfer rate by the device:

_{c = r} Ln ^ -2

η. ’

W>

where F is the frequency of the clock pulses issued by the generator 1 clock pulses;

p, is the total bit depth of each of the shift registers 8;

η is the number of shift registers 8 in the device;

i = 1,2, ... n is the number of shift register 8.

Claims (1)

Claim A device for transmitting discrete information containing a code converter, a clock pulse generator, in the main channel - a dial-up block, a shift register, sequentially connected first and second elements OR, and the bit outputs of the dial-up block are connected to the inputs of the parallel shift register code, the outputs of which are connected to the inputs of the first OR element, and in each additional channel there is a shift register, and in each main and additional channels the inputs of the lower and upper bits and the control input of the register s Whigs are combined, characterized in that, in order to increase the amount of information transmitted, the first and second AND elements are introduced in the main channel, in each additional channel there is a stacking unit, the first and second AND elements, and therefore the first and second OR elements are connected moreover, the bit outputs of the typeset block are connected to the inputs of the parallel code of the shift register, the outputs of which are connected to the inputs of the first OR element, and in each main and additional channels the outputs of the highest and lower bits of the shift register are connected s respectively, to the input of the locking unit typesetting and the second input of the second OR gate, the output of the first OR gate is connected to first inputs of first and second AND gates, whose outputs are connected respectively to the control inputs and sinhroniziruyu35 conductive shift register strobi-. The output output of the typesetting unit is connected to the third input of the first AND element, the output of the clock generator is connected to the second input 40 of the second AND element and the third input of the first AND element of each main and additional channels, and the output of the second OR element of each main and additional channels is connected to corresponding input to the code converter.