JPS6184941A - Clock synchronizing system in transmission system - Google Patents

Abstract

PURPOSE:To attain stable transmission by providing a dead band to phase adjustment of data and a clock in the reproduction of a reception clock at each node to eliminate the clock supply and phase difference adjustment at a specific node. CONSTITUTION:A reception data changing point detection section 131, a phase comparison section 132 and a clock generating section 133 are provided in a clock synchronizing circuit reproducing a reception clock RXC synchronizing with a reception data RD and the clock RXC adjusted in response to the phase difference theta is outputted. The comparison section 132 detects a phase difference thetabetween the data changing point and the clock RXC generated by the generating section 133, which changes the generated frequency (f) by + or -DELTAf around a center value f0 according to the difference theta. Thus, a dead band is provided to the phase synchronizing circuit to absorb the phase difference thereby eliminating the need for the clock supply and phase difference adjustment at the specific node.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a clock synchronization method for a data transmission system, and particularly relates to a clock synchronization method for a data transmission system, and particularly to a clock synchronization system connected in a loop. This invention relates to a clock synchronization method in a transmission system suitable for a loop transmission system, etc.

[Background of the invention]

One problem with loop transmission systems is clock synchronization. In other words, in a straight transmission line, it is sufficient to supply a clock from the most upstream and synchronize the downstream with it, but in the case of a loop, there is no most upstream or starting point.Therefore, currently, one specific node is designated as the starting point. At the end point, the phase shift due to propagation delay is adjusted at that node, but there is a problem that the mechanism is complicated and the device cannot be realized with the same device. , a loop transmission system that previously required a specific node to supply the source clock and phase adjustment is performed at each node, and the node equipment has a uniform structure.
Another object of the present invention is to provide a clock synchronization method in a transmission system that simplifies the phase adjustment mechanism.

[Summary of the invention]

The present invention provides a dead zone in the phase adjustment of the data and clock during the regeneration of the received clock performed at each node, so that when the clocks are coupled in a loop, the phase difference between the circulated clocks is absorbed by the phase difference dead zone of each node. This eliminates the need for clock supply and phase difference adjustment at special nodes.

[Embodiments of the invention]

An embodiment of the present invention will be described below.

Figure 1 shows a configuration of a loop transmission system that can maximize the effects of the present invention.1 (1'a~lc)
is a transmission control device (hereinafter referred to as a node), 2 is a transmission path, and 3 is a transmission control device (hereinafter referred to as a node).
(3A to 3B) indicate terminal devices or computers that use the transmission system, and 3A to 3B indicate 18 to 1
They communicate with each other via b.

In such a loop transmission system, data transmitted from each node is transmitted bit serially, received by a downstream node, or relayed, and transmitted further downstream.

In this case, generally, for bit-serial data, the receiving side regenerates a clock synchronized with the data, inputs it to a shift register using that clock, converts it into parallel data, or relays it downstream with a delay of about 1 bit. do.

A phase synchronized circuit (Phas) is generally used to reproduce this clock.
e 1ocked 1oop: PLL) is used.

This is because there is no need to provide a clock in addition to the data line. Fig. 2 explains the mechanism in a conventional manner, and shows the extracted parts related to clock synchronization inside node 1. 11a+11b is a transmission/reception control circuit, for example, Motorola's transmission control L
S I (MC6854) and the like are used. 13a.

13b is a clock regeneration circuit, 12 is a reference clock generation circuit, and the transmitter T of lla is a clock TXC of 12.
The receiving section R of llb transmits data according to the timing shown in FIG.

The signal is received using the clock RXC reproduced by the transmitter 13b, and the transmitter transmits using the transmission clock TXC having the same timing as RXC. In the receiving section R of lla, the clock RXC generated by the clock recovery circuit 1°3a is used in the same way as in the reception of 1b.
Receive at. In this case, of course, in 1a, a phase difference occurs between the original clock TXC and the reproduced clocks RX and C due to the time delay of the transmission path. Therefore, in 1a, it is necessary to absorb the phase difference.

Therefore, in the present invention, by providing a dead zone in the phase-locked circuit shown in FIG. 4 and absorbing the phase difference, all nodes can have the circuit configuration 1b in FIG. This eliminates the need for nodes with complicated circuit configurations.

The details will be explained below using the circuit shown in FIG.

FIG. 4 shows a clock synchronization circuit that reproduces a reception clock RXC synchronized with reception data RD, in which 131 is a reception data change point detection section, 132 is a phase comparison section, and 133 is a clock generation section. , θ, and outputs a clock RXC adjusted according to θ.

132 detects the data change point and the phase difference θ of the RXC created in 133, and 133 changes the generated frequency f by ±Af from the center value f0 according to the detected θ. Figure 5 shows its characteristics. With respect to the phase difference O between RD and RXC shown in FIG. 6, when θ is positive (advanced), f
The phase of RXC is adjusted by setting o−Af and f0+/Uf when θ is negative (lag).

At this time, the relationship between θ and f is θ as shown in FIG.

(A dead zone of -bit is provided.

That is, as shown in FIG. 6, the received data RD is
Since it is sampled at the rising point A of C, 1θ1(-b
No bit shift occurs while changing the range of it. This dead zone ±θ. is vi when connected in a loop
They become opposites, and the phases can be matched when they cycle.

The above is a case where the reception clock and transmission clock are common, but Figure 7 shows the case where they are separated.
14 is a TXC regeneration circuit, 142 is a phase difference detection section, 14
3 is a TXC generation circuit, which, like 13, generates the TXC frequency fT according to the phase difference θ7 between RXC and TXC. control.

This TXC frequency f7. Like function 13, function 7 has a dead zone θI, 7, and is effective when the dead zone of the receiving clock recovery circuit cannot be made large due to fluctuations in the waveform of received data.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to configure a loop transmission system by making each node have the same configuration, and to perform stable transmission even when some disturbance occurs, thereby making the transmission system economical. This is effective in improving the performance, compatibility of each device, and the reliability of transmission.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of a loop transmission system implementing the present invention, Fig. 2 is a block diagram showing a conventional example of a clock synchronization method, Fig. 3 is a waveform diagram showing the waveforms of Fig. 2, Figure 4 is a block diagram showing the configuration of the clock synchronization circuit of the present invention.
The figure is a relationship diagram showing its characteristics, Figure 6 is a waveform diagram showing its waveform, Figure 7 is a block diagram of a synchronization circuit that separates the reception and transmission clocks in the present invention, and Figure 8 is a waveform showing its waveform. 9 are relationship diagrams showing the characteristics. 1 (18-1c): Transmission control device, 2... Transmission line, 3
(3A-3C): Terminal device, 13th, 14th...
1st % 2 I21 Figure 3 O Arrow 4- Figure 5 yt Figure 111 →-te

Claims (1)

[Claims] 1. In a transmission system in which a plurality of transmission control devices are coupled via a transmission line, in a reception and relay transmission clock regeneration method synchronized with the reception data of each transmission control device, the change timing of received data is extracted. A clock synchronization method for a transmission system, characterized in that when detecting a phase difference with a reproduced clock and adjusting the phase of the reproduced clock to reduce the phase difference, a certain dead zone is provided with respect to the phase difference. 2. In the clock synchronization method described in item 1, a transmission system characterized in that the reception clock and the relay transmission clock are separated, the relay transmission clock is phase-synchronized with the reception clock, and a dead zone is provided for the phase difference like the reception clock. Clock synchronization method in