JPH0142177B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Technical Field> The present invention relates to a loop data communication system with improved synchronization means.

In a loop data communication system, a plurality of communication stations are connected in a loop through communication lines, and communication frames are circulated through the loop while being reproduced at each communication station. In such a data communication system,
When performing high-speed data communication, a clock is used to synchronize the data communication.

<Conventional Example> As a loop-type data communication system in which data communication is synchronized by a clock, the one described in "Yokogawa Technical Report" Vol. 26 No. 3, pages 105 to 110 is known. There is.

In this conventional example, as shown in FIG. 1, one communication station STN1 is used as a master station, and a clock circuit CLK is provided there.
The clock of this clock circuit is included in a communication frame and communicated, and downstream stations successively reproduce and use the clock, so that the entire system can be operated with a common clock.

In such conventional systems, when the system is first started up, each station's clock is set in turn to its master station.
Since the clock must match the clock of STN1, it may take about one second in some cases for the entire system to have a common clock.
This time is extremely long in a data communication system having a high communication speed of, for example, 32 Mbit/sec. If the system goes down temporarily for some reason, it will be restarted, but even then it will take a long time to start up. In addition, a failure in a clock circuit will cause a serious accident to the system, so measures are taken to improve reliability such as redundancy, but in that case, if one clock circuit fails and the other When switching to a new circuit, it takes a similar amount of time to restart the system.

<Objective> An object of the present invention is to provide a loop data communication system with a short system start-up time.

<Key Points> The present invention is a loop-type system in which a plurality of communication stations are connected in a loop through communication lines, and each communication station reproduces a communication frame received from an upstream communication station and transmits it to a downstream communication station. In a data communication system, each communication station includes a data receiver, a buffer circuit into which the output data of the receiver is input, and a clock that is regenerated from the received signal and used for the data reception operation of the data receiver. a clock regenerator that uses a signal to regulate the timing of data input operation of the buffer circuit and the timing of data input operation of the buffer circuit; a data processing circuit that processes data of the buffer circuit; and output data of the buffer circuit that has been processed by the data processing circuit. a clock circuit that generates a clock signal that regulates the timing of the data output operation of the buffer circuit and the timing of the transmission operation of the transmitter; and a clock circuit that controls the operations of the buffer circuit and the data processing circuit. The control circuit is a control circuit that causes a buffer circuit to capture only communication frame data of a received signal, and starts outputting data in the buffer circuit every time a predetermined amount of data is accumulated in the buffer circuit. The above object is achieved by a loop-type data communication system comprising a control circuit having a means for outputting dummy bits after the data in the data is used up until a predetermined amount of data is accumulated. be.

<Examples> The present invention will be described in detail below with reference to Examples.

<Configuration> FIG. 2 is a conceptual configuration diagram of an embodiment of the present invention. In FIG. 2, STN1 to STNn are communication stations connected in a loop through communication lines LIN. Each station STNi (i=1
-n) have their own clock circuits CLKi, and the frequencies fi of these clock circuits are also unique.

FIG. 3 shows the main internal configuration of one station STNj. In Figure 3, R
is the receiver, BUFF is the buffer circuit, PRO is the data processing circuit, T is the transmitter, CTL is the control circuit,
CLK is a clock circuit, and RP is a clock regeneration circuit.

Receiver R receives the signal from communication line LIN,
Supply to buffer circuit BUFF. The clock regeneration circuit RP regenerates the clock based on the clock signal included in the received signal, and converts the regenerated clock into
It is given as a signal that defines the timing of the reception operation of the receiver R and the timing of the data input operation of the buffer circuit BUFF. The frequency of this recovered clock is equal to the frequency of the clock of the upstream station STNk.

The buffer circuit BUFF has a first-in/first-out function. control circuit
CTL is buffer circuit BUFF and data processing circuit
Controls the PRO and causes it to capture received data and insert transmitted data in communication frames.
In addition, the control circuit performs control as described later on the buffer circuit BUFF and the data processing circuit PRO.

The clock circuit CLK has a unique frequency fj.
This is a unique clock circuit of the station STNj, and its clock defines the timing of the data output operation of the buffer circuit BUFF and the timing of the transmission operation of the transmitter T.

FIG. 4 shows the structure of a communication frame. A communication frame is composed of information of a fixed number of bits BF, and a frame header FH is formed at the beginning of the frame. A dummy frame of bit number BD is added to the end of each communication frame. The number of bits BD of the dummy frame is variable for each station.

A plurality of such combinations of communication frames and dummy frames circulate in series on the communication line LIN. Dummy frames form gaps between communication frames. Control circuit CTL of each station STNi
In this case, the dummy frame is discarded, only the communication frame is taken into the buffer BUFF, and the dummy frame is added to the end of the communication frame. The functions of such a control circuit are realized by a microprogram or the like.

<Operation> The operation of the system configured as described above will be explained as follows. Operation explanatory diagrams are shown in FIGS. 5 and 6. These figures are operation state diagrams of the system when the number of stations is three for convenience of explanation. In Figure 5, the station
It is assumed that STNs 1 to 3 have clock circuits with frequencies f1 to f3, respectively, and there is a relationship between the frequencies of these clock circuits as f1, f2>f3.

Now, if we focus on station STN3, this station is the upstream station.
The communication frame data received from STN2 is
It is loaded into the buffer BUFF with a clock having the same frequency as the clock of the station STN2, and is transmitted using the clock of its own clock circuit CLK. This station's clock frequency f3
is lower than the clock frequency f2 of the upstream station STN2, so in the buffer BUFF, the data output speed is slower than the data input speed.

Station STN1 receives communication frames transmitted from such station STN3.
In the buffer circuit BUFF, the frequency f
Since the data is taken in by the clock of frequency f1 and the data is output by the clock of frequency f1,
The data output speed is faster than the input speed.
Therefore, the buffer of station STN3 is
The amount of data in BUFF is
It is more than that in STN1 and 2. This situation is shown by hatching for the buffer circuit BUFF of each station.

Figure 6 shows such stations STN1~
This figure shows the state of communication between 3 and 3 in more detail. In FIG. 6, station STN2 is
Send the BF bit communication frame to station STN3 at T2 = BF/f2 time, and transmit it at the same time.
Station STN3 received at T2, T3=BF
The communication frame is transmitted to the station STN1 at time ~f3, and the station STN1 transmits the communication frame received at time T3 to station STN2 at time T1=BF~f1. Each station starts transmitting data after a predetermined amount of received data has been received. Each station has a buffer circuit
When there is no received data in BUFF, and even if there is received data, it continues to output dummy frame bits until it reaches a predetermined amount. Such operations of each station are realized by the functions of respective control circuits.

Due to the difference in the clock frequency of each station, the transmission time is T1, T2<T3.

When the station STN3 finishes transmitting the communication frame in time T3, it starts outputting a dummy frame because there is no more data in the buffer circuit BUFF, but after outputting the dummy frame with BD3 bits, the next communication starts. Since a predetermined amount of frame data is accumulated in the buffer, transmission of communication frames is started again. The same operation is repeated below.

Here, the repetition period is the buffer circuit EUFF
This is the time from when the predetermined amount of data accumulated in the dummy frame BD3 becomes zero until the predetermined amount of data is accumulated again, and is expressed as the sum of the communication time T3 of the communication frame and the communication time of the dummy frame BD3. This cycle corresponds to the transmission cycle of the upstream station STN2. The communication period of station STN2 is the sum of the communication time T2 of the communication frame and the communication time of the dummy frame BD2, and since these are equal, the length of the dummy frame BD3 is equal to the length of the communication time T3 of the communication frame. The length will be shortened. That is, the difference in communication time between communication frames is absorbed by the dummy frame, and the communication cycles are made consistent.

Similarly, the communication time of the communication frame between station STN3 and station STN1
The difference between T3 and T1 is absorbed by the lengths of dummy frames BD3 and BD1, and the communication cycles are matched. In this case, since the frame communication time T1 of station STN1 is short, the dummy frame BD
The length of 1 is increased to match the communication cycles.

The same thing applies to stations STN1 and STN2.
It is also done between. Therefore, the communication cycles of all stations are made the same, and substantial frame synchronization is performed.

When such an operation is performed, even if the station with the highest clock frequency and the station with the lowest clock frequency are next to each other, a certain amount of time is required to prevent collisions or interruptions in communication frames. conditions are required.

In other words, when the station with the highest clock frequency is upstream and the station with the lowest clock frequency is downstream, if the gap between communication frames is not appropriate, the communication frames will collide, and the station with the lowest clock frequency will When the upstream station with the highest clock frequency becomes the downstream station, if the amount of data stored in the buffer circuit is not appropriate, interruptions in communication frames will occur.

Therefore, when determining the conditions to prevent collisions between communication frames, the time required for the upstream station to communicate the communication frame BF and dummy frame BD using the clock of frequency fmax, and the time required for the downstream station to communicate the communication frame BF and the dummy frame BD. Since it is sufficient that the communication time is longer than the communication time using the clock with frequency fmin, (BF+BD)/fmax>BF/fmin (1). Therefore, from this relationship, the following condition can be obtained.

BD/BF＞fmax/fmin−1 (2) In other words, in order to prevent communication frame collisions at the other station, the upstream station must ensure that it is the station with the highest clock frequency and that the other station has the highest clock frequency. It is sufficient to assume that this is the lowest station, and add a dummy bit BD that satisfies equation (2).

Next, if we find the conditions to avoid interruptions in the communication frame, we will find that the time to complete transmitting the communication frame with the clock of frequency fmax is later than the time to complete inputting the communication frame to the buffer circuit with the clock of frequency fmin. Thus, the time to start transmitting a communication frame may be delayed by time t from the time to start receiving. Therefore, the following relationship holds true.

BF/fmax+t>BF/fmin (3) Since b=fmin·t (4) bits are accumulated in the buffer circuit within time t, t=b/fmin (5). By substituting this relationship into the relationship in (3) and sorting it out, the following relationship is obtained.

b/BF>1−fmin/fmax (6) In other words, the downstream station assumes that it is the station with the highest clock frequency, and the upstream station is the station with the lowest clock frequency, and then (6 ) It is only necessary to start transmission after the input data for bit b that satisfies the equation is accumulated in the buffer circuit.

<Effects> As described above, according to the present invention, communication frames can be synchronized even though each station uses its own clock frequency. Since each station has its own clock circuit, when the system is started, the clocks of each station start up at the same time. Therefore, the rising time of the system clock is approximately equal to the rising time of one station's clock, and is not the sum of the rising time of each station's clock, as in the conventional case. In other words, the start-up of the system is accelerated.

[Brief explanation of drawings]

Figure 1 is a conceptual configuration diagram of a conventional example, and Figure 2 is a
3 is a detailed diagram of the main parts of the communication station, FIG. 4 is a configuration diagram of a communication frame, and FIGS. 5 and 6 are operation diagrams of the embodiment of the present invention. It is an explanatory diagram. STN1~n...Communication station, CLK1~
n...Clock circuit, LIN...Communication line, R...Receiver, RP...Clock regenerator, BUFF...Buffer circuit, PRO...Data processing circuit, T...Transmitter, CTL...Control circuit, BF... Communication frame, BD... Dummy bit.

Claims (1)

[Claims] 1. A plurality of communication stations are connected in a loop by communication lines, and each communication station reproduces communication frames received from an upstream communication station and transmits the loop-shaped data to a downstream communication station. In the communication system, each communication station includes a data receiver, a buffer circuit into which the output data of the receiver is input, and a clock that is regenerated from the received signal and used for the data reception operation of the data receiver. a clock regenerator that uses a signal to regulate the timing and the timing of the data input operation of the buffer circuit; a data processing circuit that processes the data of the buffer circuit; and a clock regenerator that uses a signal to regulate the timing of data input operation of the buffer circuit; a clock circuit that generates a clock signal that regulates the timing of the data output operation of the buffer circuit and the timing of the transmission operation of the transmitter; and a clock circuit that controls the operations of the buffer circuit and the data processing circuit. The control circuit is a control circuit that allows only communication frame data of the received signal to be taken into the buffer circuit, and every time a predetermined amount of data is accumulated in the buffer circuit, it starts the data output operation in the buffer circuit, and 1. A loop type data communication system comprising: a control circuit having means for outputting dummy bits from the time when the data of the data is exhausted until the next predetermined amount of data is accumulated.