JPS622731A - External synchronizing transmission system - Google Patents

Abstract

PURPOSE:To reduce the cost of a transmission line by transmitting the clock signals at the transmitter side with omission of a period of frame timing signals and reproducing the frame timing signals at the receiver side according to an exclusive OR between the received clock signal and another clock signal delayed by a half cycle. CONSTITUTION:A double input AND gate 15 prevents the pass of the clock signal CLK on a signal line 11 while a frame pulse EP is produced. Then the clock signal CLK' which is omitted for a frame timing period is transmitted onto a transmission line 31 from an output terminal 17. The half cycle delay circuits 25 and 26 supply the signal D2 delayed by the cycle of a clock signal compared with the signal CLK' to a double input OR gate 27. At the same time, the signal CLK' and the signal D1 delayed by a half period compared with the signal CLK' are supplied to each input terminal of an exclusive OR circuit 28. Then the signal obtained by inverting the output of the circuit 28 through an inverter 29 is turned into a reproduction frame timing pulse RFP.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an externally synchronized transmission system used in short-distance data transmission systems and the like.

Conventional technology In relatively short-distance data transmission systems, such as between indoor devices, in order to simplify the transmitting and receiving equipment, a separate transmission line is used for the data instead of an internal synchronization method, and clock signals and frame timing signals are transmitted. In some cases, an external synchronization method is adopted in which the

That is, a data signal, a clock signal, and a frame timing signal indicating frame division are transmitted and received through three transmission lines of different systems.

Problems to be Solved by the Invention When the data transmission speed is approximately 100MHz or more,
It is necessary to use a coaxial cable as a transmission path, but in the conventional external synchronous transmission method described above, three expensive coaxial cables must be used, making the cost of the transmission path excessive in the entire transmission system. There is a problem with becoming.

Configuration of the Invention Means for Solving the Problems The external synchronization transmission system of the present invention, which solves the problems of the prior art described above, transmits the clock signal from the transmitting side with a corresponding period of the frame timing signal being omitted, and the receiving side Then, a clock signal is regenerated from the logical sum of the received clock signal and a clock signal delayed by an integer period, and
By regenerating the frame timing signal from the exclusive OR of the received clock signal and the clock signal delayed by half a period, only the frame timing signal can be transmitted and received with the addition of very few logic elements and delay elements. It is configured to omit the transmission line for the transmission, thereby reducing the cost of the transmission line in the entire transmission system.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a circuit diagram showing the configuration of only a portion directly related to an external synchronous transmission system to which an embodiment of the present invention is applied.

This external synchronous transmission system is comprised of a transmitting device 10°, a receiving device 20, and two transmission lines 31 and 32 connecting these transmitting devices and the receiving device.

In the receiving device 10, a lock signal CLK as shown in the waveform diagram of FIG. 2 is supplied onto the signal line 11 connected to one input terminal of the two-person gate 15. A frame pulse FP as shown in the waveform diagram of FIG. 2 is supplied onto the signal line 12 connected to the other input terminal of the two-man AND gate 15 via the inverter 14.

As a result, the two-person gate 15 uses the clock signal CL on the signal line 11 only during the appearance period of the frame pulse FP.
K is prevented from passing through, and from the output terminal 17 onto the transmission line 31,
A clock signal CLK' that is missing for a period of frame timing shown as waveform CLK'' in FIG. 2 is sent out.

On the other hand, the data signal DATA on the signal line 13 is sent out onto the transmission line 32 via the driver 16 and the output terminal 18.

This data signal DATA constitutes one frame with n bits, as illustrated in the waveform diagram of FIG.

The clock signal CLK" sent out onto the transmission path 31 passes through the input terminal 21 of the receiving device 20, undergoes level reproduction and waveform shaping at the receiver 13, and then is sent to one input terminal of the two-man OR gate 27 and the half-cycle delay circuit 25. and one input terminal of the exclusive OR gate 28.If the propagation delay time in the transmission line 31 is ignored, the clock signal CLK' supplied to each of the above parts is the same as the AND gate 1 shown in FIG.
It has the same waveform as the output of 5.

Half-cycle delay circuit 25 delays clock signal CLK' by half of its period τ and outputs a signal shown by waveform D1 in FIG. The half-cycle delay circuit 26 further delays the signal D1 by half the clock signal period τ, and as shown in FIG. to the other input terminal.

As a result, the output terminal of the two-man power OR gate 27 outputs a reproduced clock signal RCLK in which the missing bone over the frame timing pulse period is supplemented by a one-cycle delayed portion.

In parallel, each input terminal of the exclusive OR circuit 28 is supplied with the clock signal CLK' and a signal DI delayed by a half period of the clock signal CLK'.

As a result, the signal obtained by inverting the output of the exclusive OR circuit 28 by the inverter 29 becomes the reproduction frame timing pulse RFP as shown in FIG.

On the other hand, the data signal DATA sent out on the transmission path 32 passes through the input terminal 22 of the receiving device 20, and is level-regenerated and waveform-shaped at the receiver 24 to receive the received data RDAT.
A, and is reproduced in a subsequent stage circuit (not shown) in synchronization with the reproduced clock signal RCLK and the reproduced frame pulse RFP.

As described above, when reproducing the clock signal in the receiving device, the clock signal CL
Although the configuration for reproducing K is exemplified, instead of setting the delay amount to one period, it may be set to n times the period (n is an integer of 2 or more).

Effects of the Invention Since the externally synchronized transmission method of the present invention has the above-described configuration, by adding very few logic elements and delay elements, it is possible to omit the transmission line only for transmitting and receiving frame timing signals, thereby reducing the overall transmission system. The cost of transmission lines can be reduced.

Another advantage is that space utilization efficiency and system reliability are improved as the number of transmission paths is reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of only a portion directly related to this embodiment of an external synchronous transmission system to which an external synchronous transmission method according to an embodiment of the present invention is applied, and FIG. 2 is a block diagram showing the operation of the above embodiment. FIG. 2 is a waveform diagram for explaining. 10... Transmitting device, 20... Receiving device, 31° 32...
Transmission line, CLK...clock signal, FP...frame...
Pulse, DATA...data signal. CLK”...Clock signal that is missing during the period of the frame timing signal, RCLK...Regenerated clock (No. 8,
RFP: Reproduction frame pulse, RDATA: Received data signal.

Claims (1)

[Claims] In an external synchronization transmission method in which a synchronization signal is transmitted and received via a transmission line separate from that of the data signal, the transmitting side transmits and receives the clock signal with a corresponding period of the frame timing signal. The side reproduces a clock signal from the logical sum of the received clock signal and a clock signal delayed by an integer period, and also generates an exclusive logic of the received clock signal and a clock signal delayed by a half period thereof. An external synchronization transmission method characterized by regenerating a frame timing signal from a sum.