JPS6044713B2 - Data transfer control method - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a data transfer device such as an input/output control device,
In particular, it relates to a data transfer control method when input/output devices with partially different interface rules are connected simultaneously.

More specifically, the repetition period of the transfer strobe signal,
That is, the present invention relates to a control system that allows input/output devices having different data transfer rates, different time rules for the strobe signal and data bus, etc. to be connected to a system via a single input/output control device. Regarding the connection of input/output devices to a computer system, several standard interfaces have been used for each group of devices having similar attributes in order to facilitate the connection of a wide variety of devices.

In other words, as long as it complies with this standard interface, even newly developed devices can be easily incorporated into the system via existing channels or input/output control devices, and existing devices can be easily integrated into the system. It was also easy to install them in parallel. However, as such standard interfaces are used for a long time, it becomes difficult to make newly developed devices conform to all the interface regulations used by conventional models.

For example, when the data transfer rate becomes several times faster than that of conventional models, the physical interface, i.e., the type of signal wire, polarity, shape of the cable connector, etc., may need to be compatible while maintaining compatibility. , changes have to be made to details such as the time relationships between specific line numbers. Also, from the perspective of system cost, attempts were made to match devices that belonged to other device groups and had completely different interfaces to the interface of a certain device group and connect them under a single control device. . Such attempts have been made, for example, when a magnetic tape device is connected under a single-person output control device as a dump/load device for a magnetic disk device. These differences in interface conventions may have a direct impact on device performance, rather than on the basic sequence of the interface, such as device selection.
For example, this is more noticeable in a data transfer sequence.

Traditionally, when devices with different data transfer protocols are introduced into a system at the same time, it is necessary to install independent control devices for each device, or to place them under a single control device by determining the point where the specifications of each device can be met at the same time. connection was realized.

However, in the latter case, common specifications are achieved by selecting the worst point in the interface rules for each device, which makes it difficult to fully utilize the performance of newly developed devices, or reduces the interface margin. There were problems such as: Further, in FIG. 2, a strobe signal Si, which is an interface signal between the transfer control device 1 and the input/output control device 2 for executing the data transfer described above, is an internal clock signal of the transfer control device 1. occurs asynchronously.

On the other hand, internal operations in the transfer control device 1 for the transfer control device 1 to transmit and receive data to and from a host device such as a channel device (not shown) are performed in synchronization with an internal clock signal of the transfer control device 1.

Therefore, the transfer control device 1 needs to be equipped with special control means for handling the asynchronous interface signal.

Conventionally, as a method of controlling such an asynchronous interface, an asynchronous strobe signal S on the interface is used.
A transfer timing circuit was used that was configured to completely synchronize i to a clock signal within the transfer controller and then generate several types of transfer timing signals.

However, this method requires a large number of clock cycles to stably synchronize asynchronous signals and obtain transfer timing.

Therefore, when high-speed data transfer is required, the repetition period of the strobe signal that is input to the transfer timing circuit is limited, and therefore the timing circuits must be multiplexed. The disadvantage is that the circuit becomes complicated and large.

In addition, when data transfer is made faster, it is impossible to keep up with the faster transfer rate with a single configuration interface register for data transmission and reception, so it is necessary to include a buffer area. There is a method of configuring multiple registers in a shift register format, but in such a method, there is a time difference between the input and output of the interface register due to data shifting, and the shift timing control circuit becomes complicated. There were various shortcomings.

An object of the present invention is to provide a means for dynamically changing the different parts of the interface rules as described above, and more specifically, to dynamically change the functions of the hardware that controls data transfer. In addition to making it possible to connect multiple different devices to a single control device, it has a transfer timing generation circuit that has a simple configuration and can operate stably and at high speed by duplicating only the asynchronous strobe signal receiving circuit. The object of the present invention is to provide a data transfer control method.

That is, the present invention uses register values that can be set and reset from a microprogram to control strobe signal detection means, trigger means for a transfer timing generation circuit, and delay circuit for creating an asynchronous timing signal on the Internet. By making the time etc. switchable, devices with different interface rules can be connected simultaneously in an optimal state to fully bring out the original performance of each device. In other words, register values are changed by setting, resetting, etc. from microprogramming, and data is transferred between devices having substantially different hardware and different interface rules. The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an example of the configuration of an interface that is an application example of the present invention, where 1 indicates a transfer control device and 2 indicates an input/output device.

The signal lines of the interface are comprised of a strobe signal 3 and male data bus lines 5 and 6, although only those involved in data transfer are shown. FIG. 2 shows a data transfer sequence on the interface shown in FIG.

FIG. 2 shows a read operation, that is, a case where the transfer control device 1 receives data sent from the input/output device 2. In this case, the input/output device 2 issues the S1 signal 4 to inform the transfer control device 1 of the data transfer timing and sends the transfer data onto the data bus Bi6. At this time, the time before and after the Sj signal 4 and T2 are the times for ensuring skew on the interface. When the transfer control device 1 detects the Si signal 4, it receives the data on the data bus Bi6 and responds with a reception strobe signal SO3. This completes one unit of data transfer, and thereafter data transfer is performed as many times as necessary in accordance with the same procedure. FIG. 2 shows a write operation, that is, a case where data is sent from the transfer control device 1 to the input/output device 2.

At this time, the input/output device 2 issues the S1 signal 4 to inform the data transfer timing, that is, the data request, to the transfer control device. Notify 1st. After the transfer control device 1 sends data to the data bus BO5 by detecting the Si signal 4, it sends out a strobe signal SO3 while guaranteeing skew at a later time. The strobe signal SO3 is a response to the data request signal Si4 and is also a response to the data request signal Si4. Indicates that the data on the taba phantom 5 is valid, so that the input/output 2 receives the data. The transfer control device 1 turns off the SO signal 3 after a certain period of time, but the data on the data bus BO5 needs to be made valid for a period of time ζ to ensure no skew. This completes one unit of data transfer, and thereafter data transfer is performed as many times as necessary in accordance with the same procedure. In addition, Fig. 2 1
The shaded portions of the bus signals Bi and BO in and 2 are portions whose values are unstable due to bus switching during transfer of transfer units.

FIG. 3 is a block diagram for explaining one embodiment of the present invention, and numerals 1 to 6 in the figure correspond to 1 to 6 in FIG. 1, respectively.

Reference numeral 10 denotes an interface register circuit, which is composed of a pair of registers 10a and 10b connected in parallel, and an input switching circuit and an output switching circuit for these registers.

11 is a transfer timing generation circuit, 12 is a data buffer, 13 is a transfer control circuit, 14 is an interface control circuit with a host device such as a channel device, and 15 and 16 are connection buses between the data buffer 12 and the interface register 10. be.

FIG. 4 shows details of the transfer timing generation circuit in FIG. 3,
FIG. 5 is a timing chart showing the operation of the circuit shown in FIG.

In FIG. 4, 20 is an interface signal receiving circuit;
21 is an interface signal transmission circuit, 22a and 22b are delay circuits, 23 to 25 are not circuits, 26 to 28 are AND circuits, 29 and 30 are NAND circuits, 31 is an OR circuit, 3
2 to 39 are JK flip-flop circuits.

Referring to FIG. 5, the S received from the interface
The rising pulse of the l signal is detected by 22a, 23, 26 in FIG.
, 33, and 30, 28, 34,
After being semi-synchronized by alternately using the second receiving circuit 35, the signal is synchronized through the common circuits 31, 36, 37, and 38, and a timing signal is generated.

Asynchronous timing signal BOEV created by 39
N is used not only to switch the inputs of the first and second receiving circuits, but also to switch the interface registers (FIG. 3, 10a and 10b), as will be described later.

FIG. 6 shows details of the interface register circuit of FIG.
The data buses of registers 10a and 10b correspond to buses 4, 3, 15, and 16 of FIG. 3, respectively, and registers 10a and 10b of
, 10b.

In the figure, 40 is an interface signal receiving circuit, 41 is an interface signal transmitting circuit, 42 to 51 are AND circuits, and 5
2 to 54 are not circuits, and 55 to 59 are OR circuits.
In addition, the SYIE, BOEVN, and SIPLS signals are the fourth
These signals are the same as those shown in FIG. Note that the READ signal is used during the read operation described above. The WRITE signal is a signal that is turned on during a write operation. FIG. 7 shows an operation timing chart of the interface register circuit of FIG. 6.
Note that the details of the transfer timing have already been explained in FIG. In FIG. 7, the buffer access request and buffer access are as follows. FIG. 3 shows the timing of data movement to the data buffer. After the buffer is examined, if it is accessible, the buffer access is performed in the next clock cycle. The outline of the operation is as follows. (1) Read operation (see Figure 7a) - The SIPLS signal consisting of the detection of the rising edge of the Sj signal causes the data on the data bus Bi to be selected by the state of the BOEVN signal, either register 10a or register 10b. set asynchronously.

・Subsequently generated synchronization timing signal SYNCl
At the timing of buffer access, SYlEV
The output of either register 10a or register 10b, which is selected depending on the state of the signal, is stored in the data buffer.

(2) Write operation (see FIG. 7b) - By a method not shown, the registers 10a and 10b are
First data A and second data B to be sent to the interface are stored in advance.

- When sending the SO signal which is started by receiving the Si signal, the output of either the register 10a or the register 10b, which is selected depending on the state of the BOEVN signal, is enabled on the data bus (1).

・After data transmission, data bus skew (T4 in Figure 2)
BONEVN operates with sufficient delay to guarantee
The outputs of registers 10a and 10b are switched by the signal to prepare for the next data transfer.

- New transfer data is retrieved from the data buffer by data buffer access performed by the synchronization timing signals SYNCO and SYNCl, and set in either register 10a or register 10b selected by the state of the SY1EV signal.

FIG. 8 shows an example of the application environment of the present invention, where 60 is a transfer control device, 61, 62, and 63 are input/output devices A, B, and
Indicates C.

Although the input/output devices A, B, and C have the interfaces 64 illustrated in FIGS. 1 and 2 and are physically compatible, some interface rules are different.

FIGS. 2, 3, and 4 specifically show the differences in the interface rules, and illustrate write operations in input/output devices A, B, and C, respectively.

In the figure, the signals Si, SO, BO and their times correspond to Si, SO, BO and T3 to T6 in FIG.
Input/output device A is a relatively low-speed magnetic disk device intended for loading magnetic disk devices, B is a 1-day type magnetic disk device with a data transfer rate of about 1 MB/S, and C is a data transfer rate of 2. ~3MB
A magnetic disk device having /S can be considered. FIG. 9 shows an embodiment of the present invention, in which 70 is an interface signal receiving circuit, 71 is an interface signal transmitting circuit, and 72 to 9 are interface signal receiving circuits.
75 is a not circuit, 76-81 is an AND circuit, 82-8
4 is an OR circuit, 85 to 87 are delay circuits, the numbers indicate delay time NS, and 90 is set from the microprogram.
This is a resettable register.

This circuit converts the signals E and H in FIGS. 4 and 5 to
It functions to be generated by the value of the register that can be set and reset from the microprogram, and is shown at 20 in FIG.
, 21, 22a, 22b, 23, and 26.

In the example of FIG. 9, bits 0 and 1 of the register
Depending on the value of , the operation of the transfer control hardware can be switched as shown below so as to satisfy the interface rules specific to devices A, B, and C in FIG.

As described above, according to the present invention, since it is only necessary to duplicate the asynchronous strobe signal receiving circuit, the input of the strobe signal receiving circuit can be inputted using the asynchronous timing signal without completely duplicating the entire timing circuit. By switching, a synchronization circuit with a simple configuration and high speed can be obtained.

Furthermore, since a plurality of registers can be provided in parallel in the interface register circuit and used by switching, even if the data transfer rate is increased, this can be handled without complicating the hardware circuit.

In addition, it is possible to stably connect devices with different interface specifications under a single control device without degrading the original performance of the device, which not only makes it possible to realize effective system costs. The present invention can also be expected to be effective in realizing common modularized transfer hardware using LSI.

[Brief explanation of the drawing]

FIG. 1 shows an example of the configuration of an interface, FIG. 2 shows a data transfer sequence, FIG. 3 shows a block diagram for explaining an embodiment of the present invention, FIG. 4 shows a transfer timing generation circuit, and FIG. Figure 5 shows the timing chart of the transfer timing generation circuit, Figure 6 shows the interface register circuit, and Figure 7 shows the timing chart of the transfer timing generation circuit.
The figure shows an operation timing chart of the interface register circuit, FIG. 8 shows an environmental agent to which the present invention is applied, and FIG. 9 shows an embodiment of the present invention. In each figure, 1 is a transfer control device, 2, 61, 62, 63 are input/output devices, 3, 4 are strobe signals, 5, 6 are data bus lines, 10 is an interface register circuit, 10a, 1
0b and 90 are registers, 11 is a transfer timing generation circuit, 12 is a data buffer, 13 and 60 are transfer control circuits,
14 is an interface control circuit; 15 and 16 are connection buses; 20, 40, and 70 are interface signal receiving circuits;
1, 41, 71 are interface signal transmission circuits, 22a
, 22b, 85, 86, 87 are delay circuits, 23, 24,
25, 52, 53, 54, 72, 73, 74, 75 are knot circuits, 26, 27, 28, 42, 43, 44, 45
,46,47,48,49,50,51,76,77,
78, 79, 80, 81 are AND circuits, 29, 30 are NAND circuits, 31, 55, 56, 57, 58, 59, 8
2, 83, 84 are OR circuits, 32, 33, 34, 35,
36, 37, 38, and 39 are JK flip-flop circuits.

Claims (1)

[Claims] 1. It has a transfer timing signal generation means that generates a transfer timing signal synchronized with the clock of its own device based on a strobe signal, and an interface register, and also has physically compatible interfaces and allows different interfaces to use different protocols. A first strobe signal receiving circuit and a second strobe signal receiving circuit configured to be used alternately in a data transfer control device that simultaneously connects a plurality of devices having a plurality of devices on the same interface line; A synchronization circuit that generates a timing signal synchronized with the clock of the own device from the output of either one of the strobe signal receiving circuits, and a synchronization circuit that delays the strobe signal to generate a timing signal asynchronous with the clock of the own device. an asynchronous timing signal generating means, a first register and a second register connected in parallel that act as interface registers for transmitting and receiving data, and switching of the input side and the switching of the output side between the two registers are synchronized as described above. the timing and asynchronous timing for transmitting strobe signals on the interface based on the above rules and for transmitting strobe signals to the first and second strobe signal receiving circuits; A signal generating device that generates a plurality of types of timing signals for controlling the strobe signal delay amount of the signal generating device, and a switching device that switches the signal generating device according to the rules of the device that transfers the data, and Among the devices that are simultaneously connected to the data transfer device, the signal generating device is selectively switched according to the rules of the device that performs the data transfer, and the data transfer of the devices that are interface-connected to each other based on the timing signal emitted by the selected signal generating device. A data transfer control method that performs