JPH0351137B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a phase difference detection circuit that detects a change in the sequential relationship between two periodic pulses of a clock system that are asynchronous to each other, and particularly relates to The present invention relates to a phase difference detection circuit capable of detecting at an appropriate frequency even when the phase relationship of periodic pulses of two mutually asynchronous clock systems frequently changes.

(2) Background of the technology When the sampling period pulse of the signal from the calling party and the sampling period pulse of the signal from the called party are asynchronous, as in the PCM communication system, these transmitted and received signals are combined into one pulse signal. When processing in a processing circuit, it may be necessary to perform signal processing upon knowing that the timing of the generation of both periodic pulses has been reversed. For example, if the first signal processing is started when the first pulse is input and then switched to the signal processing for the second pulse input after the first pulse input, when the second pulse arrives immediately after the signal processing of the first pulse, It's like running a circuit that delays processing.

(3) Prior Art and Problems In the above system, conventionally a single-stage flip-flop was used to detect a change in the order of synchronization pulses of two mutually asynchronous clock systems. In other words, when a flip-flop receives one pulse as a clock input and the other input terminal is "1" or "0" at the rising edge of the clock, a predetermined "1" or "0" can be obtained on the output side. It was possible to detect the timing before and after the reference phase of one pulse (before and after the pulse rise time) of the other pulse. However, when the periods of both pulses are almost equal, the phase difference between them is extremely small, so the pulse rise times are almost the same, and the difference changes only slightly, resulting in 2
It is determined that the synchronization pulses of two mutually asynchronous clock systems have been swapped, and this may be repeated. Therefore, in the circuit that performs the above-mentioned signal processing, it is necessary to switch the circuit that delays the processing every time, and there is a drawback that it is difficult to switch the processing properly due to asynchronous processing.

(4) Object of the Invention The object of the present invention is to improve the above-mentioned drawbacks, and to change the phase difference between the two mutually asynchronous clock system pulses using a relatively simple circuit configuration. An object of the present invention is to provide a circuit capable of detecting switching at an appropriate frequency even when the front and back relationships of objects are frequently switched.

(5) Structure of the invention The structure of the present invention to achieve the above-mentioned object is as follows:
For two pulses: a first periodic pulse and a second periodic pulse that is asynchronous with the first periodic pulse and has a similar period, detecting an exchange of lead and lag in the phase difference of the second periodic pulse with respect to the first periodic pulse. The circuit includes delay units DL1 and DL2 that delay the first periodic pulse, and a first detection means that detects the presence or absence of the second periodic pulse in the first periodic pulse.
FF4, second detection means FF3 for detecting the presence or absence of the second periodic pulse in the first periodic pulse one bit before, the output of the first detection means and the output of the second detection means. a first gate means LG2 which compares and detects the absence of the second periodic pulse within the first periodic pulse; and presence or absence of the second periodic pulse in the delayed output pulses of the delay units DL1 and DL2. a third detecting means FF2 for detecting the second periodic pulse; a fourth detecting means FF1 for detecting the presence or absence of the second periodic pulse in the pulse of the delayed output one bit before; and an output of the third detecting means. a second gate means LG1 that compares the output of the fourth detection means and detects that the second periodic pulse is absent in the delayed pulse and that the second periodic pulse is present in the delayed pulse one bit earlier; The present invention is characterized by further comprising means for outputting a lead/lag interchange detection signal from the sum of the outputs of the first gate means and the second gate means.

(6) Embodiment of the Invention FIG. 1 is a block configuration diagram showing an embodiment of the invention, in which a pulse synchronized with the first clock system is inputted to the terminal T1, this is used as a reference pulse, and the first delay circuit is The first periodic pulse P1 is delayed by DL1. P2 is a second periodic pulse, which is synchronized with a second clock system that is asynchronous with the first clock system and has a similar period to the first periodic pulse. FIG. 2 is a time chart showing the operation of FIG. 1. 1st
A periodic pulse P1 and a second periodic pulse P2 are input as shown in FIG. Also, in Figure 1, DL
1 and DL2 are delay units that delay the first periodic pulse. FF4 detects the presence or absence of the second periodic pulse in the first periodic pulse. FF3 is 1
This detects the presence or absence of a second periodic pulse in the first periodic pulse before the bit. LG2 and FF4
The output of FF3 is compared, and the second pulse is detected within the first cycle pulse.
This gate detects the presence of a periodic pulse and the absence of a second periodic pulse within the first periodic pulse one bit before.

FF2 contains the second pulse in the delayed output pulse of DL2.
This detects the presence or absence of periodic pulses. FF1
is to detect the presence or absence of a second periodic pulse among the pulses of the delayed output of the delayed output one bit before. The outputs of FF2 and FF1 are compared, and it is detected that there is no second periodic pulse within the delayed pulse and that the second periodic pulse is present within the delayed pulse one bit earlier.

LG3 and MM output a replacement detection signal that is ahead or behind the sum of LG1 and LG2. In FIG. 2, arrows D1 and D2 indicate times indicating motion detection positions, and the rise time of the reference pulse T1 of the first clock system is defined as the detection position D2.
Therefore, D2 and pulse P1 are connected to delay circuit DL1.
There is a difference in delay time. Detection position D1 is pulse P
The position is further delayed from 1 by the delay time of the delay circuit DL2. The pulses generated at D1 and D2 are sent to the clock terminals C of flip-flops FF1 to FF4.
, the output Q of each flip-flop FF is determined by the state of the input terminal D when the input to the clock terminal C rises. FF1 and FF3 are
Compared to FF2 and FF4, each clock pulse is 1
The status after the cycle is maintained. As shown in FIG. 2, at time t1 of the detection position of D1, the pulse P2
is "1" and "0" at t2, so "1" is output from the logic operation circuit LG1. Next, a logic operation circuit LG3 and a monostable multivibrator MM are used as means for outputting a lead/lag interchange detection signal from the logical sum of logic operation circuits LG1 and LG2.
An output is obtained at the detection terminal DT.
The state of pulse P2 is “1” at time t1, t
2, the output of the detection terminal DT is "L" at t1 and "H" at t2. In that case, there is a phase difference between P1 and P2 at the detection position D1. Indicates that the sign has changed from forward to backward. For the FF1 and FF2 circuits, when the change in phase relationship is reversed,
Detection signal "H" is not generated. The time chart shown in Figure 3 is the time t1 of the time chart in Figure 2.
The state in which the relationship between and t2 is swapped is called time t3 and t
4. Swapping is detected at times t3 and t4. That is, the operations of FF3 and FF4 can be detected when the generation of pulse P2 changes from the rear to the front, using the detection position D2 as a reference. This detection output is from logic operation circuits LG2 and LG3.
is obtained through terminal DT as the output of monostable multivibrator MM.

(7) Effects of the Invention As described above, according to the present invention, since the detection positions are provided at two locations before and after a specific phase such as the rising edge of one signal, it is possible to detect whether the state of change is first → later or later. → Since the detection can be done by distinguishing between the previous case and the presence or absence of the output of the circuit that judges it, even when the generation times of the two pulses to be compared are close to each other, the frequency of switching detection does not increase. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 are operation time charts of FIG. 1. DL1, DL2...Delay circuit, FF1-FF4...Flip-flop, LG1-LG3...Logic operation circuit,
MM…Monostable multivibrator.

Claims (1)

[Claims] 1 Regarding two pulses: a first periodic pulse and a second periodic pulse that is asynchronous with the first periodic pulse and has a similar period, the phase difference of the second periodic pulse with respect to the first periodic pulse. In the circuit that detects the replacement of lead and lag, a delay unit DL1, which delays the first periodic pulse;
DL2; first detection means FF4 for detecting the presence or absence of the second periodic pulse in the first periodic pulse;
Second detection means FF for detecting the presence or absence of periodic pulses
3, the output of the first detecting means and the output of the second detecting means are compared, and it is determined whether the second periodic pulse is present within the first periodic pulse or within the first periodic pulse one bit before. a first gate means LG2 for detecting the absence of the second periodic pulse; and a third detection means FF2 for detecting the presence or absence of the second periodic pulse among the delayed output pulses of the delay units DL1 and DL2. , fourth detection means for detecting the presence or absence of the second periodic pulse in the pulse of the delayed output one bit earlier;
FF1, the output of the third detection means and the output of the fourth detection means are compared, and it is determined that there is no second periodic pulse within the delayed pulse and there is no second periodic pulse within the delayed pulse one bit earlier.
A second gate means LG1 for detecting the presence of a periodic pulse, and means LG3 and MM for outputting a lead/lag interchange detection signal from the sum of the outputs of the first gate means and the second gate means are provided. A phase difference detection circuit featuring: