JPS6086946A - Loop type data communication system - Google Patents

Abstract

PURPOSE:To ensure the synchronization of a communication frame by using a buffer circuit, a clock circuit, a control circuit, etc. and carrying out an output action of a dummy bit continuously until the data of a prescribed amount are stored after the data are used up within the buffer circuit. CONSTITUTION:At communication stations STNi (i=1,2...n), the output of a receiver R is sent to a buffer circuit BUFF under the control of a clock reproducer RP. Then the output of the BUFF is applied to a data processor PRO under the control of a control circuit CTL. The output of the PRO is transmitted to a communication line LIN by a transmitter T. Here only the data on a communication frame of a reception signal is fetched into the BUFF. Then the control CTL is carried out to perform an output action of a dummy bit BD every time a prescribed amount of data are stored in the BUFF and until a prescribed amount of the next data are stored after the data are used up within the BUFF.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a loop data communication system with improved synchronization means.

In a loop data communication system, a plurality of communication stations are connected in a loop through communication lines, and communication frames are circulated in this loop while being reproduced at each communication station.

In such a data communication system, when performing high-speed data communication, data communication is synchronized using a clock.

<Conventional example> As a loop type data communication system in which data communication is synchronized by a clock, [Yokogawa Technical Report J vol, 26 No. 3, 105-1]
The one described on page 10 is known.

In this conventional example, as shown in FIG. 1, one communication station 5TN1 is used as a master station, a clock circuit CLK is staged there, and the clock of this clock circuit is included in the communication frame for communication, and the downstream By reproducing and using clocks one after another at the stations, the entire system can be operated with a common clock.

In such a conventional system, when the system is first started up, each station's clock must be made to match the clock of its master station 5TN1 in turn. In some cases, it takes about 1 second for the data to be updated.This time is extremely long in a data communication system with a high communication speed of, for example, 32 Mbit/s. If the system goes down temporarily, it will be restarted, but even then it will take a long time to start up.Furthermore, a failure in the clock circuit can be a serious accident for the system. Measures are taken to improve reliability, such as redundancy, but in that case, even if one clock circuit fails and is switched to the other clock circuit, it will take the same amount of time to restart the system. .

<Objective> An object of the present invention is to provide a loop-type data communication system in which the start-up time of the system is short.

<Main points> The present invention provides a loop-type data communication system in which a plurality of communication stations are connected in a loop through communication lines, and each communication station reproduces communication frames received from an upstream communication station and transmits them to a downstream communication station. In the above, each communication station includes a data receiver, a buffer circuit into which the output data of the receiver is input, and a clock that is regenerated from the received signal, and the regenerated clock is used as the timing of the data reception operation of the data receiver. and a clock regenerator that uses a signal to regulate the timing of the data input horn operation of the buffer 7 circuit; a data processing circuit that processes the data of the buffer 1 circuit; and an output of the buffer circuit that has been processed by the data processing circuit. a data transmitter into which data is input, a clock circuit that generates a clock signal that regulates the timing of the data output operation of the buffer circuit and the timing of the transmission operation of the transmitter, and an ffllJ operation of the buffer circuit and the data processing circuit. A control circuit for controlling a buffer circuit, which causes a buffer circuit to capture only data of a communication frame among received signals, and starts an output operation of data in the buffer circuit each time a predetermined amount of data is accumulated in the buffer circuit; Buff 1
The above object is achieved by a loop type data communication system comprising a control circuit having a means for outputting dummy bits from the time when the data in the circuit runs out until the next predetermined amount of data is accumulated. .

<Example> Hereinafter, the present invention will be explained in detail with reference to Examples.

<composition> FIG. 2 is a conceptual configuration diagram of an embodiment of the present invention.

In FIG. 2, 5TN1 to 5TNn are communication stations connected in a loop through communication KILIN. Each station STNi (i=1 to n) has its own clock circuit CLK+, and the frequency fi of these clock circuits is also unique.

FIG. 3 shows the main internal configuration of one station 5TNj. In FIG. 3, R is the receiver, B
UFF is a buffer allopath, PR'0 is a data processing circuit,
3 is a transmitter, CTL is a control circuit, CLK is a clock circuit, and RP is a regeneration circuit.

The receiver R supplies the signal received from the communication line LIN to the buffer circuit BLJFF. The clock regeneration circuit RP regenerates a clock based on the clock signal included in the received signal, and uses the regenerated clock as a signal that defines the timing of the reception operation of the receiver R and the timing of the data input operation of the buffer 1 circuit BUFF. give as. The frequency of this recovered clock is the frequency of the upstream station ST
Equal to the frequency of the N k clocks.

The buffer circuit BUFF has a first-in/first-out function. The control circuit CTL controls the buffer circuit BUFF and the data processing circuit PRO to take in received data and insert transmitted data into a communication frame.

In addition, the control circuit performs control as described later on the buffer 1 circuit B'UFF and the data processing circuit PRO.

The clock circuit CLK is a unique clock circuit of the station 5TNj having a unique frequency fj, and its clock defines the timing of the data output operation of the buffer circuit BUFF and the timing of the transmission operation of the transmitter T. .

FIG. 4 shows the structure of a communication frame. The communication frame is
It is composed of information of a fixed number of bits BF, and a frame header FH is formed at the beginning of the frame. A dummy frame with the number of bits BD is added to the end of each communication frame. The number of bits BD of the dummy frame is variable for each station.

This combination of communication frames and dummy frames is
A plurality of them circulate in series on the communication line IN. Dummy frames form gaps between communication frames. The control circuit CTL of each station STN i discards the dummy frame, causes only the communication frame to be taken into the buffer BUFF, and adds the dummy frame to the end of the communication frame. The functions of such a control circuit are realized by a microprogram or the like.

<Operation> If we clarify the operation of a system with such a configuration, we can
It is as follows. Operation explanatory diagrams are shown in FIGS. 5 and 6. These figures are operation state diagrams of the system when the number of stations is three for convenience of explanation. In FIG. 5, stations 5TN1 to 3 each have a frequency of f1.
-3 clock circuits, and there is a relationship between the frequencies of these clock circuits: fl, f2>f3.

Now, focusing on the station 5TN3, this station processes the data of the communication frame received from the upstream station 5TN2 using a clock with the same frequency as the clock of the station 5TN2.
At the same time, it is transmitted using the clock of its own clock circuit CLK. Since the clock frequency f3 of this station is lower than the frequency f2 of the upstream station 5TN2, the buffer B U' F
In F, the data output speed is slower than the data input speed.

In the station S1'N1 that receives the communication frame transmitted from the station 5TN3, data is taken into the buffer circuit BUFF using the clock of frequency f3, and the data is read at the clock of frequency f1. Since the output is performed, the data output speed is
faster than the input speed.

Therefore, the amount of data in the buffer BUFF of the station 5TN3 is larger than that in the other stations S TN1.2. This situation is shown by hatching for the buffer circuit BUFF of each station.
0 FIG. 6 shows the state of communication between such stations 5TN1 to 5TN3 in more detail. In FIG. 6, station S 'I-N 2 is connected to BF pi
Station S T N 3, which sent a communication frame to station S T N,3 at time T2=BF/f2 and received it at the same time T2, sends a communication frame to station S T N,3 at time T2=BF/f
The communication frame is sent to station 8 TNI in 3 hours, and station 5 TNI receives the communication frame in 13 hours.
=BF/f Transmit to station 5TN2 in 1 hour. Each station starts transmission after a predetermined amount of received data has accumulated. Each station is configured to continue outputting the bits of the evening frame when there is no received data in the buffer circuit BUFF or until a predetermined amount is not reached even if there is received data. The operation of each station is realized by the operation of each control circuit.

Due to the difference in clock frequency of each station, the transmission time is T1.72<T3.

After station S T N 3 finishes transmitting the communication frame in 73 hours, it starts outputting a dummy frame because there is no more data in the buffer circuit BUFF. Since a predetermined amount of frame data has accumulated in the buffer, transmission of communication frames is started again. The same operation is repeated below.

Here, the repetition period is the time it takes for a predetermined amount of data accumulated in the buffer circuit BUFF to become zero and then accumulate again, and is the sum of the communication time T3 of the communication frame and the communication time of the dummy frame BD3. expressed. This cycle corresponds to the transmission cycle of the upstream station 5TN2. The communication cycle of station S T N 2 is between the communication frame T2 and the dummy frame BD2.
Since these are equal, the length of the dummy frame BD3 is shortened by the length of the communication time T3 of the communication frame.

That is, the difference in communication time between communication frames is absorbed by the dummy frame, and the communication cycles are made consistent.

Similarly, between the station 5TN3 and the station STN 1, the difference between the communication times T3 and 1 of the communication frames is absorbed by the lengths of the dummy frames BD3 and BDI, and the communication cycles are made equal. In this case, since the frame communication time 1-1 of the station 5TN1 is short, the length of the dummy frame BD1 is increased to match the communication cycles.

The same thing applies to stations 5TNI and S1-N2.
It is also done between. Therefore, the communication cycles of all stations are made the same, and substantial frame synchronization is performed.

When such an operation is performed, even if a station with the highest clock frequency and a station with the lowest clock frequency are adjacent to each other, it is necessary to prevent collisions or interruptions in communication frames. Certain conditions are required.

In other words, when the station with the highest clock frequency is upstream C1 and the station with the lowest clock frequency is downstream, if the gap between communication frames is not appropriate, collision of communication frames will occur, and the station with the lowest clock frequency will be downstream. If the station with the lowest frequency is upstream and the station with the highest frequency is downstream, the communication frame will be interrupted if the amount of data stored in the buffer circuit is not appropriate.

Therefore, if we include the provision fl to prevent rear-end collisions of communication frames, the time for the upstream station to communicate the communication frame BF and dummy frame BD with the clock of frequency fmax will be the same as the time for the downstream station to communicate. Since it is sufficient that the time for communicating frame BF at frequency f rnin is 0, (BF + B D ) / f m a x > t
3F/fmin(1). Therefore, from this relationship, the following condition can be obtained.

BD/BF>fmax/fmin-1 (2), that is,
In order to prevent communication frame collisions from occurring at the other station, the upstream station assumes that it is the station with the highest clock frequency and that the other station is the station with the lowest clock frequency. 2) Just write a dummy bit BD that satisfies the formula.

Next, considering the conditions for not causing interruptions in the communication frame, the time to complete transmitting the communication frame with the clock of frequency fmax is later than the time to complete inputting the communication frame to the buffer circuit with the clock of frequency rmin. In order to
It is only necessary to delay the time by one hour from 1. Therefore, the following relationship holds true.

Since 1 b=fmin-t (4) bits are accumulated in the buffer circuit within the time BF/fmax+t>BF/fmin (3), t=b/fmin (5). By substituting this relationship into the relationship (3) and sorting it out, the following relationship is obtained.

b/BF>1-fmin/fmax (6) That is, assuming that the downstream station is the station with the highest clock frequency and the upstream station is the station with the lowest clock frequency, (
6) It is only necessary to start transmission after the input data has accumulated in the buffer circuit for bit b that satisfies the formula.

Effects> As described above, according to the present invention, communication frames can be synchronized even though each station uses a clock with its own frequency. Each station has its own clock circuit, so when you start up the system,
The clocks at each station start up at the same time. Therefore, the rising time of the system clock is approximately equal to the rising time of one station's clock, and is not the sum of the rising time of each station's clock as in the conventional system. In other words, the start-up of the system is accelerated.

[Brief explanation of the drawing]

Fig. 1 is a conceptual block diagram of a conventional example, Fig. 2 is a conceptual block diagram of an embodiment of the present invention, Fig. 3 is a detailed diagram of main parts of a communication station, and Fig. 4 is a diagram of a communication frame. The configuration diagram, FIGS. 5 and 6 are explanatory diagrams of the operation of the embodiment of the present invention. 5TN1~n...Communication station CLKI~n...Clock circuit, IN...Communication line R...Receiver RP...Clock regenerator BUFF...Buffer circuit PRO...Data processing circuit゛...Transmitter CTL...Control circuit BF...Communication frame BD...Dummy pit Figure 1 Figure 3 Tail Figure 4

Claims (1)

[Claims] A loop data communication system in which a plurality of communication stations are connected in a loop by communication lines, and each communication station reproduces communication frames received from an upstream communication station and transmits them to a downstream communication station. , each communication station includes a data receiver, a buffer 7 circuit into which the output data of the receiver is input, and a clock that is regenerated from the received signal and used for the data reception operation of the data receiver. a clock regenerator that uses a signal to regulate the timing and the timing of the data input operation of the buffer circuit; a data processing circuit that processes the data of the buffer circuit; and output data of the buffer 1 circuit that has been processed by the data processing circuit. a data transmitter into which is input, a clock circuit that generates a clock signal that regulates the timing of the data output operation of the buffer 1 circuit and the transmission operation of the transmitter, and a clock circuit that generates a clock signal that regulates the operation of the buffer circuit and the data processing circuit. A control circuit that controls the buffer circuit so that only communication frame data of the received signal is taken into the buffer circuit, and every time a predetermined amount of data accumulates in the buffer circuit, the data output operation in the buffer circuit is started. 1. A loop data communication system comprising: a control circuit that outputs dummy bits after the data in the circuit runs out until a predetermined amount of data is accumulated.