JPS6292549A - Terminal clock generating system for loop communicating system - Google Patents

Abstract

PURPOSE:To generate simply and uniformly the terminal supply in which the frequency synchronization is obtained by detecting the frame period of the transmitting frame with respective stations and generating the terminal supply clock on the basis of this. CONSTITUTION:A station 2 receives the data from a loop transmission line 1 through a receiver 10. A time slot multiplex/separating circuit 30 identifies the frame constitution from the receiving data column, dissolves the time slot to the prescribed bit unit, sends to a receiving bus 40-1, assembles the prescribed bit unit information on a transmitting bus 40-2 to the time slot and sends to a transmitter 20. The transmitter 20 sends the data to the transmission line 1 by the bit serial. A terminal supply clock circuit 50 generates respective types of the clock necessary to the terminal action and supplies to respective terminal connecting adapters 60-1-60-3. By the above-mentioned constitution, in the loop communicating system constituted by the independent synchronization, the terminal supply can be generated in which the frequency synchronization is obtained between stations.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for generating a clock supplied from a station to a terminal device in a high-speed loop communication system.

[Background of the invention]

Conventionally, a loop communication system employs a dependent synchronization method in which all other stations operate in frequency synchronization with the clock pulse of one station. In this dependent synchronization method, stations are relayed in multiple stages, so jitter accumulates and the quality of audio and images deteriorates. Further, when a failure occurs, there is a problem that clock interruption occurs downstream of the failed station, and reconfiguration control such as loopback takes time.

Therefore, in order to avoid these problems, an independent synchronization system is being considered in which each station has a highly stable oscillator and operates with an independent clock. In this independent synchronization method, generation of terminal clocks with frequency synchronization between each station is a problem.

As a terminal clock generation method in a loop communication system using such an independent synchronization method, Tasaki et al. [Study of synchronization method in ring type local area network]
A system is known in which a clock is generated for each terminal according to the reception memory occupancy of the station, as described in IEICE Technical Report 5E-83-], 17 (Sho 58-11). However, this method requires a clock generation circuit for each terminal, which hinders miniaturization of the station.

[Purpose of the invention]

An object of the present invention is to provide a clock generation method that can uniformly generate terminal supply clocks with frequency synchronization between stations in a high-speed loop communication system configured with independent synchronization.

[Summary of the invention]

In a loop communication system configured with independent synchronization, the present invention detects the frame period of a transmission frame generated by a reference station at each station, and
! This is a terminal clock generation method characterized in that a clock supplied to the terminal is generated by a phase synchronized oscillator using a doubled signal. [Embodiments of the Invention] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing a configuration example of a loop communication system to which the present invention is applied. In Figure 2, 1 is a loop transmission line such as an optical fiber, 2 is a station, and P
T: Various terminals are connected, such as packet switching terminals (eg, computers, workstations, etc.), CT two-line switching terminals (telephones, facsimiles, data terminals, etc.).

FIG. 1 is an explanatory diagram of an example of a transmission frame configuration on a loop transmission line 1 showing an embodiment of the present invention. F is frame, T
S (TS#1 to TS#m) is a time slot, and FS is a frame synchronization signal, which is a signal for identifying the division of the following time slots TS. GB is a guard bit, which is a dummy bit used to adjust the frame period to a constant time since each station has a different clock frequency. Note that only one reference station generates the transmission frame, and other stations relay and transmit the frame.

For example, if a temperature-controlled crystal oscillator is used at each station, the frequency stability will be ±1 ppm (1, p
pI11 = 10-6) - However, in the worst case, there is a frequency deviation of about 2 ppm between arbitrary stations, and for this reason, within one frame period, 1, for example, 100 Mb/s (loop Transmission speed) x 2ppm x 125
A frame period error of approximately μs (1 frame time) = 0.025 bit/frame occurs. That is, 4
Addition/deletion of one guard bit occurs approximately once per o frame.

Note that in packet switching, burst data from a computer or the like is transmitted while occupying an arbitrary number of time slots TS. In line switching, transmission is performed by subdividing time slots into a plurality of channels and assigning them to terminals. Since the structure of the time slot is not directly related to the present invention, a detailed explanation will be omitted.6 FIG. 3 is a block diagram showing an example of the structure of the station 2 showing an embodiment of the present invention. In FIG. 3, station 3 receives data from loop transmission path 1 via receiver 10, extracts a clock from the received data string, and reproduces the data.

2o is a transmitter that sends data to the transmission line 1 in a bit-serial manner. 30 is a time slot multiplexing/demultiplexing circuit that identifies the frame structure shown in FIG. It has the function of being assembled into a slot. 50 is a terminal supply clock generation circuit that generates various clocks necessary for terminal operation and supplies them to each terminal connection adapter 60. 4o is for reception (40-1
), is an information exchange bus for transmission (40-2), and, for example, information in 8-bit units, timing signals, etc. are periodically transferred. Reference numeral 60 denotes a terminal connection adapter, which controls terminal-compatible interfaces, packet exchange/line exchange, and the like.

FIG. 4 is a block diagram showing one embodiment of the time slot multiplexing/separating circuit 30. 301 is a clock generator that extracts a clock from data received by the receiver 10; 302;
is the frame synchronization signal F in the frame configuration shown in FIG.
Frame synchronization is detected based on S. A time slot reception control circuit 303 identifies the time slot based on the frame synchronization signal, specifically generates and supplies a time slot synchronization signal and data transfer timing on the reception bus. 304 is a delay circuit for frame synchronization signals, which corrects logical delays in the path between the receiver 10, the reception bus 40-1, the terminal connection adapter 60, the transmission bus 4o-2, and the transmitter 20. A flip-flop 305 is a circuit that synchronizes the frame synchronization signal delayed by the reception clock with the transmission clock. 30B is a serial/parallel conversion circuit, and 307 is a buffer register.

Reference numeral 308 denotes a memory circuit, which, like the frame synchronization delay circuit 304 described above, corrects logical delays for data. 309 is a transmission clock oscillator, which generates a clock! It operates independently from the reception clock of 301. 310 is a time slot transmission control circuit, which uses the frame synchronization signal from the receiving side and the transmission clock.
For controlling the frame assembly shown in FIG. 2, 311 is a guard bit generation circuit, 312 is a buffer register, a parallel-to-serial conversion circuit, and 313 and 314 are selectors.

Next, using the timing chart of FIG. 5, the operation of frame period control using guard bits in the station will be explained. Figure 5 shows the time to (reception clock a and transmission clock d) at any station.
is in a specific state in which phase synchronization is achieved and time tn (because the clock frequency on the receiving side is a little high, to ``”” t n
(a state in which the detection point of the frame synchronization signal C on the receiving side and the sending command point e of the frame synchronization signal on the transmitting side differ by 1 bit or more between
In FIG. 5, time slot multiplexing/demultiplexing circuit 30, transmitting/receiving bus 40 . Logical delays within the terminal connection adapter 6o are omitted to simplify the explanation. Also, to simplify the explanation, the frame synchronization signal is shown in the case of 4 bits, but
It is also possible to configure it with an arbitrary bit length.

The time "to" corresponds to the case where the receiving clock and the transmitting clock are the same, and even in the case of the independent synchronization method that is the object of the present invention, such a state occurs in the process of frequency slip.
In the example shown in FIG. 5, this state is the initial state. Since the reception clock frequency is higher than that of the transmission, the frame synchronization signal C detected on the reception side gradually moves in the direction of the arrow in the diagram. (FIG. 5 is illustrated with the transmission clock as a reference). However, if this amount of movement is smaller than 1 bit, sampling can be performed in the flip-flop 305 using the α pulse of the transmission clock d, so the time slot The frame synchronization signal e input to the transmission control circuit 310 is output at the same time position as time to.

After time has elapsed, at time t11, the amount of movement of the frame synchronization signal C, ie, the cumulative value of the transmission/reception clock frequency error, becomes 1 bit or more, and it is sampled with the β pulse of the transmission clock d. In this case, the transmission of the guard bit GBj is stopped and the frame synchronization signal bit FSI is immediately transmitted. Therefore, at time t4, a frame with one bit less than that in the steady state is transmitted, and the cumulative value due to the clock frequency error is reset.

Note that although this example shows the case where the frequency deviation of the transmitting/receiving clock is small, it goes without saying that the same concept can be applied to the case where the frequency deviation is large. Specifically, each time a frame synchronization signal is detected, the cumulative value of the clock frequency error (expressed in terms of the number of bits) is checked, and a transmission frame is configured by adding/deleting guard bits corresponding to an integer value. .

FIG. 6 shows a terminal supply clock generation circuit that generates a terminal clock using this frame period, specifically a digitally processed phase synchronized oscillator. Note that the frequency of the terminal clock varies widely.

Basically, the speed that is supported as a public network,
For example 1.2, 2.4. ......, 48,64゜1
If it is possible to achieve speeds such as 92, 384, and 768 kb/s, most terminals will be able to connect.

A flip-flop 501 is set by the output C of the frame synchronization signal detection circuit 302 shown in FIG. 4, and reset by the output of the frequency division counter 507. 502 is AN
A D gate, 503 is a counter, and 504 is an average value circuit over an arbitrary number of frames of the counter value, and controls the voltage controlled oscillator 506 so that the output value of this average value circuit is constant. 505 is a digital-to-analog (DA) conversion circuit. 508 is a frequency divider for generating terminal clocks for the various speed classes described above. When generating the terminal clock frequency of the speed class mentioned above, for example, the output of the voltage controlled oscillator 506 is set to 6.144 MH
If it is set to z, it can be generated using only a frequency dividing circuit without multiplication.

〔Effect of the invention〕

According to the present invention, in a loop communication system configured by independent synchronization, it is possible to easily and uniformly generate terminal supply with frequency synchronization between stations, thereby reducing the size of station hardware. There is an effect that it can be done.

[Brief explanation of drawings]

FIG. 1 is a frame configuration of an embodiment of the present invention, FIG. 2 is a loop communication system configuration diagram to which the present invention is applied, FIG. 3 is a station configuration diagram of an embodiment of the present invention, and FIG. 4 is a diagram of the present invention. A detailed configuration diagram of a time slot multiplexing/demultiplexing circuit according to an embodiment of the invention, FIG. 5 is an operation timing chart for explaining the guard bit control method, and FIG. 6 is a terminal supply clock generation circuit according to an embodiment of the invention. FIG. 1... Loop transmission line, 2... Station, 1o.
...Receiver, 20...Transmitter, 30...Time slot multiplexing/separation circuit, 40...Transmission/reception bus, 5o...
...Terminal supply clock generation circuit, 60...Terminal connection adapter. 301... Clock generator, 3o2... Frame synchronization detection circuit, 303... Time slot reception control circuit, 304... Frame synchronization signal delay circuit, 305...
・Flip-flop, 306...Serial-to-parallel conversion circuit, 3
07... Buffer 7 register, 30 B... Memory circuit, 3o9... Transmission clock oscillator, 310... Time slot transmission (+1 control circuit, 311... Guard bit generation circuit, 312... Normal Direct conversion/buffer register, 313°31, /l...Selector, 501...
・Flip-flop, 502 ・A N r) Game 1-
,503-...Counter, 5o4...Average value circuit, 5
05...1) A conversion circuit, 506... Voltage controlled oscillator, 507.508... Frequency divider.

Claims (1)

[Claims] 1. In a loop communication system consisting of a plurality of terminals, a station that accommodates these terminals and executes information transfer, and a transmission line that connects the stations, the frame period of the transmission frame is determined by each station. 1. A terminal clock generation method for a loop communication system, characterized in that each station is regenerated and relayed using an independent clock oscillation source, and each station generates a terminal clock using the frame period as a reference signal. 2. In claim 1, when each station relays the frame period, the cumulative value of the clock frequency difference between the stations is patch-checked every time a frame synchronization signal is detected, and the cumulative value corresponds to the integer number of bits. A terminal clock generation method that relays frame cycles by adding/deleting guard bits.