JPS63149935A - Synchronizing pulse transmission system - Google Patents

Abstract

PURPOSE:To reduce the number of signal lines and pins by transmitting a signal obtained by exclusive OR between a clock pulse and a synchronizing pulse from a transmitting side, and recovering the clock pulse and the synchronizing pulse at the reception side based on the signal transmitted from the transmission side. CONSTITUTION:The transmitting side 10 uses an EX-OR gate 11 to synthesize the clock pulse CK with the synchronizing pulse SYNC, the result is transmitted through a signal line 40 and a pulse recovery section 22 recovers it at the reception side 20. Thus, the number of signal lines is decreased and the number of pins is reduced when the constitution between the transmission section 10 and the reception section 20 is formed as an LSI. Since the pulse S1 transmitted via the signal line 40 is the superimposition of the synchronizing pulse SYNC on the clock pulse CK, the possibility of introduction of phase shift between them is precluded.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Field of Industrial Application) This invention is applicable to devices that need to transmit synchronization pulses and clock pulses in addition to data, such as PCM terminal equipment. This article relates to a synchronous pulse transmission method that can be used.

(Prior art) For example, in the PCM C0DEC, as shown in FIG. 4, data in units of 8 bits is originally sent out as serial data (a), and synchronization pulses (b) are given at a cycle of 125 μsec. At the same time, a clock (C) is applied in synchronization with each bit of the serial data (a). In this case, in the conventional synchronous pulse transmission method,
Serial data (a), synchronization pulse (b), clock (
Since C) was transmitted through separate signal lines, the number of signal lines was large, and when the transmitter and receiver were integrated into an LSI, the number of pins increased.

Furthermore, if there is a difference in signal propagation time between signal lines, it is necessary to adjust the phase between the synchronizing pulse (b) and the clock (C) on the receiving side, which is troublesome.

(Problems to be Solved by the Invention) As mentioned above, in the conventional synchronous pulse transmission method, the synchronous pulse (b) and clock CC) were sent via separate signal lines, so the number of signal lines was large. Also, the L of the transmitter/receiver section
When converting to SI, there was a drawback that the number of pins increased. Also,
On the receiving side, it is sometimes necessary to adjust the phase between the synchronization pulse (b) and the clock (C), which has the drawback of being cumbersome.

The present invention was made in an attempt to eliminate the drawbacks of the conventional synchronous pulse transmission method, and its purpose is to reduce the number of signal lines and pins, and to reduce the number of signal lines and pins, and to reduce the number of synchronous pulses and clocks on the receiving side. An object of the present invention is to provide a synchronous pulse transmission method that does not require phase adjustment.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, a signal obtained by an exclusive OR operation of a clock pulse and a synchronization pulse is transmitted on a transmitting side, and a signal obtained by the exclusive OR operation of a clock pulse and a synchronizing pulse is transmitted on a receiving side. The clock pulse and synchronization pulse are regenerated based on the signal transmitted from the side.

(Function) According to the above-mentioned synchronous pulse transmission method, when the transmitting side sends a signal, the clock pulse and the synchronous pulse are combined, so it can be transmitted through a single signal line, and the clock pulse due to the propagation time difference There is no longer a phase difference between the pulse and the synchronization pulse.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. In the figure, 10 is a transmitter, 20 is a receiver, and the transmitter 10
and the receiving section 20 are coupled by a signal line 30.40. The transmitter 10 transmits, for example, an octet signal via a signal line 30 as serial data. The receiving section 20 is provided with a PCM C0D E C21,
Serial data is transmitted via the signal line 30 to the PCM
It is applied to the data terminal DATA of C0DEC21. The transmitter 10 is also equipped with an EX'-OR gate 11, and the clock pulse OK and the synchronization pulse 5YNC are given to the EX-OR gate 11 as a pulse S1 created by an exclusive OR operation. , are sent out via the signal line 40. The receiving section 20 is provided with a pulse reproducing section 22, and the pulse S1 is applied to an input terminal IN of the pulse reproducing section 22 via a signal line 40.

The pulse regenerator 22 is configured as shown in FIG. In the same figure, 221 indicates an EX-OR gate, one input terminal of this EX-OR gate 221 is given a pulse S1, and the EX-OR gate 22
The output signal of the EX-NOR gate 223 is applied to the other input terminal of the EX-NOR gate 223.

The output signal S2 of the EX-OR gate 221 is output from the delay line 22.
given to 2. This delay line 222 provides a delay of half a cycle of the clock pulse GK. The output signal S4 of the delay line 222 is applied to the clock terminal of the PCM CODEC 21 and also applied to one input terminal of the EX-NOR gate 223. The other input terminal of the EX-NOR gate 223 is given a pulse S1. E
The output signal of the X-NOR gate 223 is sent to the inverter 224.
PCM
It is given to the synchronization terminal of C0DEC21. The operation of this pulse generator 22 will be explained based on the timing chart of FIG. 3. When a pulse S1 with a synchronization pulse present in the Pl portion arrives via the signal line 40, initially E
Since the output signal of the X-NOR gate 223 is at H level, the output signal S2 of the EX-OR gate 221 is
The signal is an inversion of the pulse S1, and the output of the delay line 222 is an output signal S4 that is obtained by delaying the output signal S2 by 1/2 the phase.

Due to the presence of the synchronizing pulse in the Pl portion, the output signal S4 becomes H level and the pulse S1 becomes L level at the P2 position of the output signal 84, so the EX-NOR gate 2
The output of 23 becomes L level, which is the output of inverter 224.
The synchronizing pulse P3 can be reproduced as the output signal S3.

On the other hand, in the EX-OR gate 221, the synchronizing pulse P3 of the output signal S3 and the Pl portion of the pulse S1 are subjected to an exclusive OR operation, so that the output signal S4 is reproduced as a clock pulse with the same period as the original. It becomes what is given.

In this way, in this embodiment, the clock pulse CK and the synchronization pulse 5YNC are controlled by the EX-OR gate 11 on the transmitting side.
The signals are combined and transmitted through a single signal line 40, and on the receiving side, the pulse reproducing section 22 reproduces the signal.

Therefore, the number of signal lines can be reduced, and the transmitter 10
When the configuration of the receiver section 20 and the receiver section 20 are integrated into an LSI, the number of pins can be reduced. Moreover, the pulse S1 sent via the signal line 40 is a synchronized pulse 5YN with the clock pulse CK.
Since the weight of C is increased, there is no possibility that a phase shift will occur between them.

[Effects of the Invention] As explained above, according to the present invention, the clock pulse and the synchronization pulse are made into a 1 signal by exclusive OR operation, and this is sent. Moreover, since no phase shift occurs between the two pulses, the troublesome process of adjusting the phase on the receiving side can be eliminated.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a system to which the present invention is applied;
The figure is a block diagram of the main parts of the system in Figure 1, and Figure 3 is a block diagram of the main parts of the system in Figure 2.
FIG. 4 is a timing chart for explaining the operation of the configuration shown in the figure, and FIG. 4 is a diagram showing the relationship between data, clock pulses, and synchronization pulses. 10... Transmitting section 11, 221... EX-OR gate 20... Receiving section 21... PCM C0DEC 22... Pulse reproducing section 222... Delay line

Claims (1)

[Claims] A transmitting side transmits a signal obtained by an exclusive OR operation of a clock pulse and a synchronizing pulse, and a receiving side reproduces the clock pulse and synchronizing pulse based on the signal transmitted from the transmitting side. Characteristic synchronous pulse transmission method.