JPS6276338A - High-speed data transmission and synchronization system - Google Patents

Abstract

PURPOSE:To facilitate frame synchronization by using a phase changeover circuit to switch the phase of a clock signal when no frame synchronization is taken for a prescribed period and using the clock signal at the phase when the frame synchronization is taken to key received data. CONSTITUTION:When the frame synchronization is not taken for a prescribed period in a frame synchronization circuit 11, a changeover control signal CS is fed to a phase changeover circuit 12 from a changeover protection circuit 13 to invert a flip-flop 15. Then the phase of the clock signal CK is changed over. Thus, since the rising phase of the clock signal CK is nearly at the center of data, the data is keyed and the frame synchronization is taken in the frame synchronization circuit 11. When the frame synchronization is taken, since a frame synchronization detection signal FD is fed to the change-over protection circuit 13, the changeover control signal CS by the overflow of a counter 14 is not outputted to allow the phase changeover circuit 12 to hold the phase of the clock signal CK as it is. Thus, the high-speed data transmission of 500MHz is attained.

Description

[Detailed Description of the Invention] [Summary] High-speed data frame synchronization is performed based on a clock signal,
If frame synchronization cannot be achieved even after a predetermined period of time has elapsed, it is determined that the phase between the high-speed data and the clock signal is not appropriate, and the phase of the clock signal is switched to reestablish frame synchronization and frame synchronization is achieved. High-speed data punching is performed using a clock signal with a phase of 117
Gb/S level 0 high speed data''. 6T- also easy'.7'
−”Synchronization: This is to enable bit synchronization.

[Industrial Application Field]: The present invention relates to a high-speed data transmission synchronization method that can relatively easily synchronize high-speed data.

On the receiving side during data transmission, frame synchronization and bit synchronization are usually achieved. In order to synchronize these,
A clock signal is required, but as data transmission technology becomes faster and more integrated, there is a need for a more effective synchronization method with a simple configuration.

[Conventional technology]

There are two methods for achieving this type of synchronization: a clock signal synchronized with the data is transmitted in parallel with the data, and on the receiving side, the clock signal is used to synchronize the received data, and the other method is to extract the clock signal from the received data string. However, there is a method of synchronizing using that clock signal.

[Problem that the invention seeks to solve]

When the data transmission speed becomes high, such as 100 Mb/S or more, the period becomes 10 nS or less, so a slight phase difference between the data and the clock signal may cause synchronization to fail. Therefore, in the above-mentioned method of transmitting data and clock signals in parallel, synchronization can be achieved with slight variations of the number of nanoseconds or less in the delays of the elements and transmission paths of the respective transmission systems for data and clock signals. Therefore, it is necessary to limit the transmission distance to a level where variations can be ignored, or to finely adjust the length of the transmission path, the amount of delay in the operation of the elements, etc. so as to correct the variations in delay. but,
Since this fine adjustment is an adjustment of several nanoseconds or less, it has the disadvantage that it is not easy.

Furthermore, in a method for extracting a clock signal from a received data string, a configuration in which a phase locked loop (PLL) circuit is used to extract the clock signal is common. This PLL
When the circuit is used for high-speed clock signal extraction of 100 Mb/s or more, the configuration is different from that of a normal logic circuit.
The drawback was that it was difficult to integrate into an integrated circuit.

An object of the present invention is to transmit high-speed data and a clock signal in parallel so that bit synchronization and frame synchronization can be achieved on the receiving side with a simple configuration.

[Means for solving problems]

The high-speed data transmission synchronization method of the present invention performs data punching using a clock signal of the phase when frame synchronization is achieved. The received data is applied to the frame synchronization circuit 1 via the phase switching circuit 2, and when frame synchronization cannot be achieved for a predetermined period of time, a switching control signal is sent from the frame synchronization circuit 1 to the frame synchronization circuit 1. 2 to change the phase of the clock signal, e.g.
This is to switch to 90 degrees or 180 degrees and re-establish frame synchronization. Then, data received by the flip-flop 3 is punched out using a clock signal having a phase when frame synchronization is established, thereby achieving bit synchronization.

[Effect]

If the phases of the received data and clock signal are not appropriate, frame synchronization will not be achieved. Therefore,
When it is detected that frame synchronization cannot be achieved for a predetermined period of time, the phase of the clock signal is switched to another phase and frame synchronization is reestablished. Since there is a relationship, frame synchronization can be achieved. Therefore, when frame synchronization is achieved, the phase relationship between the data and the clock signal is appropriate, and the received data is punched out using the clock signal of that phase to achieve bit synchronization.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, with FFI~
FF2 is a flip-flop, 11 is a frame synchronization circuit,
12 is a phase switching circuit, 13 is a switching protection circuit, 14 is a counter, 15 is a flip-flop, 16 is an inverter, 1
7 to 19 are gate circuits. flip flop FFI
The flip-flop FF2 is for punching the received data Din using the clock signal CK, and the flip-flop FF2 is for punching the data output from the flip-flop FFI using the clock signal CK to produce output data Dout. The flip-flop FF3 is used to punch out the frame pulse detected by the frame synchronization circuit 11 using the clock signal CK and apply it to the subsequent circuit as a frame pulse FP.

The frame synchronization circuit 11 has a configuration to achieve frame synchronization by detecting a frame pulse included in received data based on the clock signal CK, and the detected frame pulse is applied to the flip-flop FF3.

Further, the frame synchronization detection signal FD is applied to the switching protection circuit 13.

The phase switching circuit 12 is composed of a flip-flop 15, an inverter 16, and gate circuits 17 to 19, and switches between outputting the received clock signal CL as it is, or inverting it with the inverter 16 and outputting it. This shows that.

Note that it is also possible to adopt a configuration in which the phase is switched to 90 degrees, 45 degrees, etc., or a configuration in which the phase is switched to three or more different phases.

The switching protection circuit 13 has a configuration that performs forward protection and backward protection of frame synchronization, and includes, for example, a counter 14 that counts the clock signal CK, and is reset by the frame synchronization detection signal FD to prevent frame synchronization. In this state, the switching control signal C8 is not output because the ° counter 14 is reset at the frame cycle. However, if the state in which the frame synchronization detection signal FD is not applied continues for a predetermined period, the counter 14 that counts the clock signal GK overflows and the switching control signal CS is output. Therefore, if frame synchronization cannot be achieved even after a predetermined period has elapsed since the start of the frame synchronization pull-in operation, the switching control signal CS is output. Further, if a period in which frame pulses cannot be detected for some reason continues for a predetermined period after frame synchronization is achieved, the switching control signal CS will be output.

In the phase switching circuit 12, the flip-flop 15 performs an inverting operation every time the switching control signal CS is applied. For example, when the Q terminal output of the flip-flop 15 is "1", the gate circuit 17. '19, receive clock signal CL
A clock signal CK having a phase of is output. In addition, the flip-flop 15 is inverted by the switching control signal CS, and Q
When the terminal output becomes "0", the clock signal CK is output from the inverter 16 via the gate circuits 18 and 19.
This clock signal CK is obtained by inverting the phase of the received clock signal CL.

FIG. 3 is an explanatory diagram of the operation, and (a) is the received data I.
)in, (b) is a part of the expanded data, (C1 is the clock signal CK of the received clock signal CL phase, (dl
indicates the phase-inverted clock signal CK, and the frame pulse FO+F1. ..., for example, "101110
00'' pattern is used.

Also t. is the clock signal period, 1. is data jitter, t2
indicates clock signal jitter.

For the received data Din, as shown in (C),
When the rising phases of the clock signals CK are almost the same, the data Din cannot be accurately punched out by the flip-flop FFI due to respective jitters. As a result, frame synchronization cannot be achieved in the frame synchronization circuit 11.

If frame synchronization cannot be achieved for a predetermined period in this way, the switching control signal CS is sent from the switching protection circuit 13 to the phase switching circuit 1.
2, and the flip-flop 15 performs an inverting operation.

As a result, the phase of the clock signal CK is switched,
The clock signal phase shown in FIG. Frame synchronization can be achieved in the synchronization circuit 11.

When frame synchronization is achieved, the frame synchronization detection signal FD is applied to the switching protection circuit 13, so that the switching control signal C8 due to the overflow of the counter 14 will not be output, and the phase switching circuit 12 will maintain the phase of the clock signal CK as it is. I will do it.

Regarding the relationship between data and clock signals, the conditions for accurately punching out data with the flip-flop FFI are: (t o / 2) t + t z t, where the setup time of the flip-flop FFI is t3.
3>0-(1). For example, clock signal f
When tJ1to is 2nS (500MHz), data jitter t1 and clock signal jitter t2 are each 0.
．． 1 n S, and when the cent amplifier time t3 of the flip-flop FFI is 0.2 n S, the condition of the fl1 formula is satisfied, so high-speed data transmission of 500 Mf (z) is possible. The logic circuit can be easily realized using, for example, an ECL (emitter coupled logic) circuit.

Furthermore, since it can be constructed from only logic circuits, it is easy to integrate it into an integrated circuit.

FIG. 4 is a block diagram applied to a frame aligner, and the frame synchronizer 21 includes received data,
signal and a reference first frame signal, frame synchronization of the data is achieved based on the clock signal,
The phase difference between the first frame when synchronization is established and the reference first frame signal is detected, and a phase control signal is output. The configuration shown in FIG. 2 is used for frame synchronization, and can easily achieve frame synchronization and bit synchronization of 3U1 even for high-speed data.

The output data of the frame synchronizer 21 and the phase control signal are added to the frame phase correction buffer 22.

The frame phase correction buffer 22 includes a plurality of stages of flip-flops 23 and a selector 24 that selects their outputs.
The selector 24 performs a selection operation according to a phase control signal. The selected output of the selector 24 becomes output data via a flip-flop 25.

FIG. 5 is an explanatory diagram of the operation, where fal is received data and FO, Fl, . . . , F7 are frame pulses. Further, (bl is the reference first frame signal, fc) is the output data. Frame pulse FQ+ F,,...
・The pattern of F7 is “1011100” as mentioned above.
0'', it is possible to identify the first frame, and if the phase difference between the first frame when frame synchronization is established and the reference first frame signal is n-to, then the signal will follow this phase difference. A phase control signal is applied to the selector 24. In the case of a phase difference of n-to, the selector 24
Since the output of the n-stage flip-flop 23 is selected and output, the first frame of the output data can be output in agreement with the reference first frame signal, as shown in FC+.

FIG. 6 is a block diagram of an example of application to a time division communication channel.
This shows the case of TST configuration. In the same figure, T
a1~Ta4. Tb1 to Tb4 are time switches, Sal to Sa4. Sbl to Sb4 are space switches, 31 to 34 are frame forming circuits, and 35 to 46 are frame aligners, each having the configuration shown in FIG.

Further, 51 is a timing control circuit that controls the switch timing of the time switch and the space switch, and 52 is a clock generation circuit that generates a clock signal.

Data from each highway is transferred through time switches Ta1-Ta
4, the time slots are exchanged by the timing signal from the timing control circuit 51 according to the exchange connection information, and the frame circuits 31 to 34 convert the received data as shown in FIG. 5(a). , frame pulses Fo, F, . . . are inserted to form a frame. This framed data is sent to the spatial switch Sal.
~Sa4 frame aligners 35 to 38 correct for variations in highway transmission delays. Therefore, there is no need to differ the switch timing phases corresponding to the space switches Sal to Sa4, and the highway exchange connection can be performed using the timing signal from the timing control circuit 51 according to the exchange connection information.

Space switches Sa 1 to Sa 4. Although Sb 1 to Sb4 are interconnected and have different lengths of transmission paths, frame aligners 39 of space switches Sbl to Sb4
.about.42 corrects variations in transmission delay in the same way as in the case of the space switches Sal to Sa4 described above, and allows exchange connection to be performed in accordance with the timing signal from the timing control circuit 51.

Also, in the time switches Tbl to Tb4, variations in transmission delay can be corrected by the frame aligners 43 to 46, so time slots are exchanged according to the timing signal from the timing control circuit 51.

The operating speed in a conventional time-division communication channel is about 8 MHz, but as mentioned above, by providing a frame aligner to which the present invention is applied, time-division exchange can be performed at an operating speed of several GHz. This makes it possible to construct a large-scale, high-speed time-division communication path.

[Effects of the Invention] As explained above, in the present invention, when the frame synchronization circuit I cannot achieve frame synchronization for a predetermined period, the phase switching circuit 2
The phase of the clock signal is switched, frame synchronization is reestablished based on the clock signal, and the received data is punched using the clock signal having the phase when the frame synchronization is achieved. This has the advantage that frame synchronization can be easily achieved even if there is a phase difference between the received data and the clock signal due to variations in delay in the transmission path or the like. Therefore, it is possible to correct variations in transmission delays in various high-speed data transmission systems and achieve frame synchronization and bit synchronization, so it can be applied to frame aligners and the like.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation, Fig. 4 is a block diagram of the frame aligner, and Fig. 5 is the operation of the frame aligner. The explanatory diagram, FIG. 6, is a block diagram of an example of application to a time division communication path. 1 is a frame synchronization circuit, 2 is a phase switching circuit, 3 is a flip-flop, 11 is a frame synchronization circuit, 12 is a phase switching circuit, 13 is a switching protection circuit, 14 is a counter, 15 is a flip-flop, 16 is an inverter, FFI~ FF3 is a flip-flop.

Claims (1)

[Claims] A phase switching circuit (2) is provided to switch the phase of a clock signal applied to the frame synchronization circuit (1), and when the frame synchronization circuit (1) cannot achieve frame synchronization for a predetermined period, the phase switching circuit (2) Synchronous circuit (1
) A high-speed data transmission synchronization method characterized in that the phase of the clock signal applied to the frame synchronization circuit (1) is switched, and the clock signal having the phase when frame synchronization is achieved in the frame synchronization circuit (1) is used as the clock signal for data punching.