JPH08340312A - Frame synchronization control circuit - Google Patents

Abstract

PURPOSE: To keep an error between reception and transmission timing within a permissible deviation for a long time even when an oscillation circuit with a low stability is in use by following the phase of a reception frame timing signal with the phase of a recovery frame timing. CONSTITUTION: An oscillated frequency of an oscillation circuit 1 is frequency- divided by a variable frequency divider circuit 2, the result is used for a reception timing signal and it is fed to a frame timing recovery circuit 3. When the circuit 1 has low stability, a deviation is produced between a recovery and a reception frame timing with the elapse of time. An error detection circuit 4 detests a phase error between a recovery frame timing signal being an output of the circuit 3 and a reception frame timing signal being an output of the circuit 2 receiving the reception signal for each prescribed time based on a recovered frame timing signal, an averaging circuit 5 processes the phase error into an error timewise mean value, which is given to a frequency division ratio control circuit 6. Then the circuit 6 applies feedback control to a frequency division ratio of the circuit 2 to allow the reception frame timing to follow the recovery frame timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization control of a receiver in a communication system in which a plurality of data are transmitted from a transmitting station in a time division multiplexed frame, and a receiving station receives only necessary frames from transmission data. Regarding the circuit.

[0002]

2. Description of the Related Art In the case of receiving only necessary data frames by performing intermittent reception from a time division multiplex frame, it is necessary for a receiving station to synchronize frame timing for each received frame. For synchronization of this frame timing, there is a method of shortening the synchronization acquisition time of the next received frame by holding the supplemented frame timing using an oscillation circuit with high frequency stability. Is expensive and the device itself is expensive.

There is also a method of using an oscillation circuit having low frequency stability and widening the synchronization detection range in the next reception frame to perform synchronization acquisition. However, this method lengthens the operating time of the receiver. However, it consumes a large amount of electric power, becomes a problem when it is used in a portable terminal, etc., and also increases a risk rate of causing false synchronization.

[0004]

As described above, according to the conventional frame synchronization method of this type, when a receiver oscillator circuit having low frequency stability is used, the synchronization acquisition time becomes long and erroneous synchronization occurs. There is a problem that the device configuration becomes expensive when the transmission rate circuit having a high frequency stability is used because of a high risk rate.

The present invention has been made to solve the above problems, and is similar to the case where an oscillator circuit having a low frequency stability is used as an oscillator circuit of a receiver while an oscillator circuit having a high frequency stability is used. It is an object of the present invention to provide a frame synchronization control circuit that can perform synchronization acquisition in a short time.

[0006]

A frame synchronization control circuit according to the present invention outputs a reproduction frame timing signal at a transmission frame timing obtained from a reception signal, and a reception clock signal generated by an oscillation circuit. A variable frequency dividing circuit that divides and outputs a reception frame timing signal, an error detection circuit that detects a phase error between the reception frame timing signal and the reproduction frame timing signal at predetermined intervals, and at a predetermined interval by this error detection circuit. An averaging circuit that outputs the temporal average value of the phase error detected by the feedback control of the frequency division ratio of the variable frequency dividing circuit by the output of the averaging circuit, and the phase of the received frame timing signal is adjusted to the reproduction frame. It is characterized in that it is provided with means for appropriately following the phase of the timing signal.

Further, it is characterized in that the phase error detection interval performed by the error detection circuit is variable.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, 1 is an oscillating circuit, 2 is a variable frequency dividing circuit, 3 is a frame timing reproducing circuit, 4 is an error detecting circuit, 5 is an averaging circuit, and 6 is a frequency dividing ratio control circuit.

Next, the operation will be described. The received signal is input to the frame timing reproduction circuit 3, and the received frame timing signal is synchronously captured by the synchronization signal included in the received signal, and the reproduced frame timing signal is output. On the other hand, the oscillating frequency from the oscillating circuit 1 is divided by the variable frequency dividing circuit 2 and input to the frame timing reproducing circuit 3 as a received frame timing signal. However, if the stability of the oscillating circuit 1 is low, it is reproduced with the passage of time. There is a discrepancy between the frame timing and the received frame timing.

Therefore, in the frame synchronization control circuit of this embodiment, the reproduction frame timing signal from the frame timing reproduction circuit 3 and the reception frame timing signal from the variable frequency dividing circuit 2 are input to the error detection circuit 4, and this error detection is performed. The circuit 4 detects the phase error of the received frame timing signal with reference to the reproduction frame timing signal at a predetermined interval and inputs it to the averaging circuit 5, and the time average value of the error is input to the division ratio control circuit 6. The frequency division ratio control circuit 6 feedback-controls the frequency division ratio of the variable frequency division circuit 2 to control the reception frame timing to follow the reproduction frame timing.

FIG. 2 is a time chart showing an operation when the stability of the oscillation circuit 1 is low and the reception clock frequency is lower than the transmission clock frequency. If the reproduction frame timing is synchronized with the reception frame timing at time T0, FIG. At time T1, since the reception clock frequency is low, a phase difference of Δt1 occurs between the reproduction (transmission) frame timing and the reception frame timing, and this phase difference Δt1 is input to the averaging circuit 5. In this way, the temporal average value Δt of the error detected by the error detection circuit 4 (not shown) is input from the averaging circuit 5 to the division ratio control circuit 6 at predetermined intervals between times T0 and T2. Dividing ratio control circuit 6
Operates and the frequency division number of the variable frequency dividing circuit 2 decreases. As a result, at time T2, the phase error can be reduced to Δt2, and the reception frame timing can be made to follow the reproduction frame timing, and the synchronization acquisition can be performed in a short time. You will be able to do it. The interval at which the error detection circuit 4 detects the phase error between the reception frame timing and the reproduction frame timing may be variable in consideration of the stability of the oscillation circuit 1.

[0012]

As described above, the frame synchronization control circuit of the present invention can appropriately follow the reception frame timing with the transmission frame timing while using the oscillator circuit with low stability, so that the reception operation is stopped. There is an effect that the error between the reception frame timing and the transmission frame timing can be kept within the long-term allowable deviation.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the present invention.

[Explanation of symbols]

 1 oscillator circuit 2 variable frequency divider circuit 3 frame timing reproduction circuit 4 error detection circuit 5 averaging circuit 6 frequency division ratio control circuit

Claims (2)

[Claims] 1. A frame synchronization control circuit used in a receiver that receives only necessary frame data from a time division multiplexed frame by intermittent reception, and a frame that outputs a reproduction frame timing signal at a transmission frame timing obtained from a reception signal. A timing recovery circuit, a variable frequency divider circuit that outputs a reception frame timing signal by dividing the reception clock signal generated by the oscillation circuit, and a phase error between the reception frame timing signal and the reproduction frame timing signal at predetermined intervals. An error detection circuit for detecting, an averaging circuit for outputting the temporal average value of the phase error detected by the error detection circuit at predetermined intervals, and a feedback of the division ratio of the variable frequency dividing circuit by the output of the averaging circuit. Control the phase of the received frame timing signal to the playback frame timing. Frame synchronization control circuit, characterized in that it comprises means, to follow appropriately No. phases. 2. A frame synchronization control circuit having a structure in which a phase error detection interval performed by the error detection circuit is variable.