JP3094632B2 - Data receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving apparatus used for mobile communication such as a digital car telephone.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional data receiving apparatus. In FIG. 3, reference numeral 1 denotes a modulator, and transmission data 5
1. Transmission transmission clock 52 generated by the oscillator 2 on the transmission side
Generates a modulated wave 53. A transmitter 3 generates a transmission radio wave 54 from the modulated wave 53 and transmits the transmission radio wave 54 from the transmission antenna 4. Reference numeral 5 denotes a receiver, which generates a reception wave 55 from the transmission radio wave 54 received by the reception antenna 6. Reference numeral 7 denotes a demodulator which detects the received wave 55 and outputs the reproduced clock reference signal 5.
6 as well as detecting the reception wave 55 at the timing of the reproduction transmission clock 59 to generate reproduction data 57. Reference numeral 8 denotes a transmission clock recovery circuit, which is a PLL (Phase
Lock loop 9 and variable frequency dividing circuit 11 to generate reproduced transmission clock 59. An oscillator 12 on the receiving side supplies an operation clock 58 to the variable frequency dividing circuit 11. Reference numeral 14 denotes a control circuit of the data receiving device.

[0003] The above configuration will be described in further detail below together with its operation. On the data transmission side, the modulator 1 generates a modulated wave 53 from the transmission data 51 and the transmission transmission clock 52 supplied from the oscillator 2, and sends it to the transmitter 3. The transmitter 3 generates a transmission radio wave 54 from the modulated wave 53 and transmits it from the transmission antenna 4.

On the other hand, on the data receiving side, the transmission radio wave 54
Is received by the receiver 5 via the receiving antenna 6, and the received wave 5
5 is transmitted to the demodulator 7. The demodulator 7 receives the received wave 5
5 to generate a reproduction clock reference signal 56, and at the timing of the reproduction transmission clock 59 transmitted from the variable frequency dividing circuit 11 of the transmission clock reproduction circuit 8, detect the reception wave 55 to generate reproduction data 57. , Control circuit 14
Send to

The variable frequency dividing circuit 1 of the transmission clock reproducing circuit 8
1 variably divides the operation clock 58 from the oscillator 12 to generate a reproduction transmission clock 59. The control circuit 14 manages, based on the content of the reproduced data 57, the timing of intermittent reception for receiving one to several frames during the superframe when the mobile station waits for an incoming call. In the received frame, the PLL 9 operates according to the control signal 60 from the control circuit 14, and the PLL 9 detects the phase difference between the reproduction clock reference signal 56 and the reproduction transmission clock 59 so that the variable frequency dividing circuit 11 follows the phase.
Sends a control signal 61 to The variable frequency dividing circuit 11 normally divides the frequency to 1 / n, but the control signal 61 changes the frequency dividing ratio from 1 / n to 1 / l (l> n) or 1 / m (m <n).
To perform variable frequency division. Therefore, even when the transmission clock 52 and the operation clock 58 on the receiving side are asynchronous, the reproduction transmission clock 59 synchronized with the transmission clock 52 can be generated. In the non-received frame, the PLL 9 is stopped by the control signal 60 from the control circuit 14, and the variable frequency dividing circuit 11 is controlled to perform fixed frequency division (1 / n).

As described above, in the conventional data receiving apparatus, the reproduction transmission clock 5 following the transmission clock 52 on the transmission side is used.
8 can be generated.

[0007]

However, in the above-mentioned conventional data receiving apparatus, the receiver 5 and the demodulator 7 are stopped and the clock recovery operation is stopped in the non-reception frame of the intermittent reception. 11 is a fixed frequency division of the oscillator 12 on the receiving side. Therefore, when the time of the non-reception frame becomes longer, a phase difference occurs between the transmission transmission clock 52 and the reproduction transmission clock 59 due to the relative accuracy between the transmission side transmission clock 52 and the reception side variable frequency divider operating clock 58, An error occurs during intermittent reception. Further, in order to suppress the occurrence of the phase difference, it is necessary to have the oscillators 2 and 12 with high accuracy.

The present invention solves such a conventional problem, and reduces the phase difference between the reproduction transmission clock and the transmission transmission clock without having a high-precision oscillator, thereby reducing the non-reception frames of intermittent reception. Therefore, it is possible to reduce power consumption, reduce the weight of the battery, extend the standby time, and reduce the size and cost of the oscillator in a mobile communication device. It is an object of the present invention to provide a data receiving device capable of performing the above.

[0009]

In order to achieve the above object, the present invention provides a receiving means for receiving a transmission radio wave, a reproduction clock reference signal generated from the reception radio wave, and a reproduction data reference signal at a reproduction transmission clock timing. Demodulating means for generating a reproduction clock; dividing the operation clock to generate the reproduction transmission clock; detecting a phase difference between the reproduction clock reference signal and the reproduction transmission clock; And a control signal transmitted from the phase difference detecting means to the variable frequency dividing means. The phase difference detecting means counts a control signal transmitted from the phase difference detecting means to the variable frequency dividing means. Counting means for outputting a control signal to the variable frequency dividing means, and switching the control signal outputted from the phase difference detecting means and the counting means to the variable frequency dividing means. It is obtained by a switching means for output.

[0010]

Therefore, according to the present invention, the reproduction clock reference signal is generated by the demodulation means from the radio wave received by the reception means, and the reproduction data is generated at the timing of the reproduction transmission clock. During continuous reception, the switching means connects the phase difference detecting means to the variable frequency dividing means, detects the phase difference between the reproduced clock reference signal and the reproduced transmission clock by the phase difference detecting means, and performs phase tracking. , The phase of the reproduced transmission clock is corrected, and a reproduced transmission clock that follows the transmission clock on the transmission side can be generated. In the meantime, the control means counts the control signal from the phase difference detecting means to the variable frequency dividing means by the counting means, and connects the counting means to the variable frequency dividing means by the switching means immediately before the reception frame during the intermittent reception. By outputting the control signal to the variable frequency dividing means, it is possible to correct a phase shift between the transmission clock and the reproduction clock generated in the non-reception frame during the intermittent reception.

[0011]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing a data receiving apparatus according to one embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a modulator, which generates a modulated wave 53 based on transmission data 51 and a transmission clock 52 generated by an oscillator 2 on the transmission side. A transmitter 3 generates a transmission radio wave 54 from the modulated wave 53 and transmits the transmission radio wave 54 from the transmission antenna 4. Reference numeral 5 denotes a receiver, and a receiving antenna 6
A reception wave 55 is generated from the transmission radio wave 54 received in step (1). 7
Is a demodulator, which detects a received wave 55 to generate a reproduced clock reference signal 56 and a reproduced transmission clock 59
The reception wave 55 is detected at the timing of (1), and the reproduction data 57 is generated. Reference numeral 8 denotes a transmission clock recovery circuit, which is a PLL.
(Phase Lock Loop) 9, a switch 10, and a variable frequency dividing circuit 11.
Generate An oscillator 12 on the receiving side supplies an operation clock 58 to the variable frequency dividing circuit 11. Reference numeral 13 denotes a counter, and 14 denotes a control circuit of the receiving apparatus.
Controls the PLL 9, the switch 10, and the counter 13. That is, the PLL 9 operates or stops in response to the control signal 60 from the control circuit 14, and outputs a control signal 61 to the variable frequency dividing circuit 11 via the switch 10 during operation. Further, the counter 13 switches the switch 1 from the PLL 9 by the measurement timing signal 62 from the control circuit 14.
Control signal 61 sent to the variable frequency dividing circuit 11
And outputs a control signal 64 to the variable frequency dividing circuit 11 through the switch 10 according to the output timing signal 63 from the control circuit 14. The switch 10 is controlled to be switched by a control signal 65 from the control circuit 14, and selectively sends a control signal 61 from the PLL 9 and a control signal 64 from the counter 13 to the variable frequency dividing circuit 11.

The above configuration will be described in further detail below together with its operation. On the data transmission side, modulator 1
Generates a modulated wave 53 from the transmission data 51 and the transmission transmission clock 52 supplied from the oscillator 2, and sends it to the transmitter 3. The transmitter 3 generates a transmission radio wave 54 from the modulated wave 53 and transmits it from the transmission antenna 4.

On the other hand, on the data receiving side, the transmitting radio wave 54 is received by the receiver 5 via the receiving antenna 6 and the receiving radio wave 55
Is generated and sent to the demodulator 7. The demodulator 7 receives the received wave 55
To generate a reproduction clock reference signal 56, and at the same time as the reproduction transmission clock 59 transmitted from the variable frequency dividing circuit 11 of the transmission clock generation circuit 8,
5 to generate reproduced data 57 and send it to the control circuit 14.

When the mobile station waits for an incoming call, the control circuit 14 determines from the content of the reproduced data 57 that the mobile station 1
The timing of intermittent reception for receiving several frames is managed. The control circuit 14 performs continuous reception before moving to intermittent reception. At this time, the switch 1
0 is switched to the PLL 9 side, and the PLL 9 is operated by the control signal 60. The PLL 9 detects a phase difference between the reproduction clock reference signal 56 and the reproduction transmission clock 59,
The variable frequency dividing circuit 1 via the switch 10 so that the reproduction transmission clock 59 follows the phase of the reproduction clock reference signal 56.
1 to output a control signal 61. The variable frequency dividing circuit 11 normally divides the operating clock 58 from the oscillator 12 by 1 / n to generate a reproduced transmission clock 59, but the control signal 61
Divide ratio from 1 / n to 1 / l (l> n) or 1
/ M (m <n). Therefore, even when the transmission clock 52 and the operation clock 58 on the receiving side are asynchronous, the reproduction transmission clock 59 synchronized with the transmission clock 52 can be generated. Also, the control circuit 1
4 sends a measurement timing signal 62 to the counter 13 to count the control signal 61 during one superframe 102 composed of a plurality of frames 101 at the time of continuous reception shown in FIG. The counter 13 counts the control signal 61 sent from the PLL 9 to the variable frequency dividing circuit 11 during the measurement timing.

In the non-reception frame 103 during intermittent reception shown in FIG.
The LL 9 is stopped, and the variable frequency dividing circuit 11 controls the operation clock 58 sent from the oscillator 12 to perform fixed frequency division (1 / n). The control circuit 14 switches the switch control signal 65 immediately before the reception frame 104 shown in FIG.
Switches the switch 10 to the counter 13 side, and sends the output timing signal 63 to the counter 13. The counter 13 generates a control signal 64 corresponding to the control signal 61 generated during the continuous reception of one superframe 102 by the output timing signal 63, and outputs the control signal 64 to the variable frequency dividing circuit 11 via the switch 10. The variable frequency dividing circuit 11 generates the reproduced transmission clock 59 synchronized with the transmission transmission clock 52 and performs the phase correction generated in one superframe 102 in the same manner as described above.

The control circuit 14 again switches the switch 10 to the PL level by the switch control signal 65 during the reception frame.
Switch to L9 side, and control signal 60
Operate L9. Accordingly, as described above, the PLL 9
Is transmitted to the variable frequency dividing circuit 11 via the switch 10, and the variable frequency dividing circuit 11 generates a reproduction transmission clock 59 synchronized with the transmission transmission clock 52.

As described above, according to the above embodiment, the phase difference between the transmission clock 52 and the reproduction clock 59 generated in the non-reception frame 103 during intermittent reception is variably divided into 105 immediately before the reception frame 104. Since the correction can be performed on the circuit 11 by the control signal 64 generated by the counter 13, it is possible to suppress the occurrence of an error generated by the clock phase shift in the reception frame 104.

[0020]

As described above, according to the present invention, the reproduction clock reference signal is generated by the demodulation means from the radio wave received by the reception means, and the reproduction data is generated at the timing of the reproduction transmission clock. During continuous reception, the switching means connects the phase difference detecting means to the variable frequency dividing means, detects the phase difference between the reproduced clock reference signal and the reproduced transmission clock by the phase difference detecting means, and performs phase tracking. , The phase of the reproduced transmission clock is corrected, and a reproduced transmission clock that follows the transmission clock on the transmission side can be generated. During this time, the control means counts the control signal from the phase difference detection means to the variable frequency dividing means by the counting means, and connects the counting means to the variable frequency dividing means by the switching means immediately before the reception frame during intermittent reception,
By outputting a control signal corresponding to the count number to the variable frequency dividing means, it is possible to correct a phase shift between the transmission clock and the reproduction clock generated in the non-reception frame during the intermittent reception. Since the phase difference of the transmission clock generated in the non-reception frame during the intermittent reception can be corrected immediately before the reception frame, the non-reception time of the intermittent reception can be extended even if the accuracy of the oscillator is low. it can. Therefore, it is possible to reduce the power consumption, reduce the weight of the battery, increase the standby time, and reduce the size and the cost of the oscillator in a mobile communication device.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a data receiving apparatus according to an embodiment of the present invention.

FIG. 2A is an explanatory diagram of a continuous receiving operation in the data receiving device; FIG. 2B is an explanatory diagram of an intermittent receiving operation in the data receiving device;

FIG. 3 is a schematic block diagram showing a conventional data receiving device.

[Description of Code] 1 Modulator 2 Oscillator 3 Transmitter 4 Transmitting antenna 5 Receiver 6 Receiving antenna 7 Demodulator 8 Transmission clock recovery circuit 9 PLL (Phase Lock Loop) 10 Switch 11 Variable frequency divider 12 Oscillator 13 Counter 14 Control Circuit 51 Transmission data 52 Transmission transmission clock 53 Modulation wave 54 Transmission radio wave 55 Reception wave 56 Reproduction clock reference signal 57 Reproduction data 58 Variable frequency dividing circuit operation clock 59 Reproduction transmission clock 60 PLL control signal 61 Variable frequency division circuit control signal (PLL output 62 Measurement timing signal 63 Output timing signal 64 Variable frequency divider circuit control signal (counter output) 65 Switch control signal

Claims (1)

(57) [Claims] 1. A receiving means for receiving a transmission radio wave, a demodulation means for generating a reproduction clock reference signal from the reception radio wave and generating reproduction data at the timing of a reproduction transmission clock, and dividing the operation clock to generate the reproduction signal A variable frequency dividing means for generating a transmission clock; detecting a phase difference between the reproduced clock reference signal and the reproduced transmission clock; transmitting a control signal to the variable frequency dividing means; Phase difference detecting means for performing correction, counting means for counting a control signal sent from the phase difference detecting means to the variable frequency dividing means, and outputting a control signal to the variable frequency dividing means according to the count number; A data receiving apparatus comprising: a switching unit that switches the control signal output from the phase difference detecting unit and the counting unit and sends the control signal to the variable frequency dividing unit.