JP3103604B2 - Frequency control method in delay detection demodulator for π / 4 shift QPSK modulated wave signal - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to .pi. / 4 which is recommended from the viewpoint of efficient use of frequencies in digital mobile communication.
The present invention relates to frequency control in a shift detection four-phase shift keying (QPSK) type differential detection demodulator.

[0002]

2. Description of the Related Art As a modulation system in digital mobile communication, particularly in a car telephone, in order to efficiently use a frequency, a circuit configuration is simple as a modulator / demodulator used here, and a phase transition trajectory of a carrier wave is originated. Since the signal does not pass through the band, the attenuation characteristic out of the band is good, and the π / 4 shift QPSK method is considered to be promising. As a demodulator, the error rate characteristic at the time of static transmission is good, and the error under the Rayleigh fading is good. The delay detection method is promising as one that satisfies the condition that the rate does not deteriorate.

However, on the other hand, the error rate characteristic due to the frequency deviation of the carrier wave is inferior to that of the synchronous detection system, and this frequency change affects the configuration and performance of the entire apparatus. It is necessary to provide control means for matching the carrier wave to be transmitted, that is, a frequency adjustment function.

In the frequency correction control circuit of the π / 4 shift QPSK differential detection type demodulator shown in FIG. 3, (1) the baseband transmission signal first demodulated by the IF band differential detection demodulator is temporarily multiplied by 4 and modulated. Then, the signal is amplified through a loop filter to obtain a phase difference output proportional to the carrier frequency offset, and the control voltage changes the sample clock of the delay element to correspond to the carrier frequency offset. The frequency is to be corrected based on the delay amount obtained.

Next, in the conventional frequency adjusting circuit shown in FIG. 4, (2) A / D conversion of each of I and Q baseband signals, and after passing through a carrier offset detector, the symbol clock signal _CL and mode control are performed. after passing through the pre presettable selector SEL which got the up / down digital counter and a channel gate signals S ₁ is the signal input from the vessel MC, VCO to adjust the local oscillator frequency converting D / a (VCXO) that to obtain a control signal S ₂ are known.

However, according to the method (1), the frequency of the π / 4 shifted QPSK signal is not easy to correct because the amplitude of the collapse line is not constant. It is necessary to reproduce the signal for frequency correction, and it is inevitable that the circuit configuration becomes large. In the method (2), the amount indicating the frequency offset of each of the I and Q baseband signal outputs is A / D converted. In order to increase the speed of the digital operation performed from the beginning, the digitizing circuit becomes unnecessarily large.

Therefore, in the conventional method of controlling the frequency of the delay detection demodulator for a π / 4 shift QPSK modulated wave signal, the circuit configuration is complicated as shown in FIGS. And the frequency stability required by the communication system is 10 pp.
It is difficult to correct the frequency shift of m, and these difficulties have not yet been solved from the viewpoint of the production efficiency of the demodulator and the like.

[0008]

SUMMARY OF THE INVENTION The present invention eliminates the above-mentioned conventional problems, and simplifies the circuit configuration required for reading a baseband signal of a π / 4 QPSK modulated carrier intermediate frequency. The frequency control method is capable of reducing the amount of processing required for calculation.

[0009]

The π / 4 shift Q
After separating the PSK modulation intermediate frequency into I and Q baseband signals by a π / 2 phase shifter and converting them into digital signals, a processor having an arithmetic processing and determination function by storing past received signals as data, The frequency control is performed in two stages before and after the signal is read by the multiplication of the temperature-compensated voltage controlled oscillator that directly controls the local oscillation frequency to be adjusted via the local oscillator.

Hereinafter, the frequency control method of the present invention will be described in detail with reference to FIGS. First, FIG. 1 is a frequency control circuit of the [pi / 4 shift QPSK delay detection demodulator implementing the frequency control method of the present invention, [pi / 4 shift QPSK intermediate carrier mixers M ₁ and M ₂ and [pi / 2 phase shifter upon receipt of The baseband signals are separated into I and Q baseband signals by a filter, and only the frequencies of the baseband signals are separated into loop filters LPF ₁ and LF, respectively.
Analog / Digital converter A after extraction by PF ₂
/ D to obtain baseband signals I _D and Q _D , respectively, and input them to a processor PRCS having a RAM for sequentially storing received signals, and output the digital / analog signals to a D / A converter. Temperature-compensated TCXO via a loop filter LPF ₃ which converts the noise and removes noise or jitter, that is, a VCO (voltage controlled oscillator)
A return loop is formed.

The OSC is a local oscillator (local oscillator) for generating a local oscillation frequency of the mixer. The OSC has a multiplication function with the VCO, and scans the VCO until the local oscillation frequency is finely adjusted to 10 ppm to ± 0.

[0012] transmitting side and the preamble signal and the ID code signal is sent via a control channel as a signal format in one burst, the receiver data signals, i.e. I on the control channel, Q baseband signals are transmitted up
The processor determines whether or not it can be read as a reamble signal and an ID code signal . Here the processor
As a first step adjustment, the data signal becomes readable.
To sweep the so that VCO. When the data signal becomes readable, it sends a reply to the transmitting side. Next, the VCO is generated by a known signal added to the audio data through the communication channel.
Fine-tune the output frequency as a second stage adjustment.

FIG. 2 is a spatial diagram of the amplitudes of the baseband signals I and Q. The eight values of π / 4 QPSK are expressed as “1” in which each value of I and Q takes one of 1, −1, and 0. With a single circle,
The state “2” of + 1 / √2 or -1 / √2 is represented by a double circle, respectively, and the transmitted signal is that the I and Q signals which alternately repeat the states “1” and “2” transition. Means.

If the frequencies completely match in state "1", the I or Q signal is ± 1 and the other signal is 0, but in reality there is an error in the frequency. The value of ± 1 becomes small, and the other does not become 0 but has a certain value. That is, the values of I and Q are originally (I, Q) = (1,
0), (I, Q) = (0, 9, 0.4)
Assuming that the result is 4), the value of Q is not 0 but 0.4.
4 means that there is a frequency offset, and that this value is positive means that the frequency is transiting in the positive direction, that is, clockwise, and that at a certain time the state of the frequency of the I and Q signals If it is known what value of “1” takes, of the I and Q signals,
It is determined whether the frequency is shifted in the plus or minus direction only by the positive and negative signs.

In the present invention, the future I and Q values are not predicted at the time of data transmission, but the arrangement of the preamble signal is fixed. Can be determined, and this can be left to the determination function of the processor.

For example, if the I signal is 1 → 0 → 1, the Q signal is 0 →
When changing from 1 to 1, the set of 1, Q values is I = 1, when Q = 0, "1", the set of I = 0, Q = 1 is "2", I = 1, Q =
Since the set of 1 represents the information transition of “3”, the detection output (I, Q) is (1, 0) → (−1 / √2, −1 /
(2) → (0, -1), and the state of “3” is I =
When the Q signal is 1, and the I signal is positive, the frequency is shifted to the negative side, and when the signal is negative, the TCXO, which is the VCO, is shifted to the positive side.
Is fine-tuned.

[0017]

According to the present invention, after a baseband signal is generated from a π / 4 shift QPSK modulation intermediate frequency, a carrier wave reproducing circuit, a data timing reproducing circuit, a discriminator, and a serial / parallel circuit which are conventionally required in terms of circuit configuration. A processor that replaces an auxiliary circuit such as a converter is incorporated in a control loop including a VCO that controls the local oscillation frequency in two steps, so that I and Q values can be predicted from the transition pattern of the baseband signal. It is possible to quickly control the deviation of the local oscillation frequency in the demodulator of the detection system, and to prevent deterioration of the error rate characteristic of the signal caused by this deviation. Therefore, the delay frequency corresponding to the offset of the π / 4-shifted QPSK carrier wave enables the local oscillation frequency to be incorporated in the frequency control feedback loop with a delay detection demodulator having an extremely simple configuration, and is excellent in mass productivity without troublesome adjustment steps during production. Thus, an economical frequency control method can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram for implementing a frequency control method in a delay detection demodulator for a π / 4 shift QPSK modulated wave signal of the present invention.

FIG. 2 is a spatial diagram of baseband I and Q signals, showing states “1” and “2” of signals input to a processor after passing through each loop filter.

FIG. 3 is a circuit configuration diagram of a conventional delay detection diversity demodulator.

FIG. 4 is a configuration diagram of a conventional frequency adjustment circuit.

[Explanation of symbols]

MIX ₁ , MIX ₂ Mixer A / D Analog / Digital Converter PRCS Processor D / A Digital / Analog Converter LPF ₁ , LPF ₂ , LPF ₃ Loop Filter OSC Local Oscillator (Local Oscillator) TCXO VCO (Voltage Controlled Oscillator) π / 2PS π / 2 phase shifter I, Q Baseband signal

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 27/00-27/38 H04B 7/26

Claims (1)

(57) [Claims] In a method for controlling the frequency of a delay detection demodulator for a π / 4 shift QPSK modulated wave signal, a communication signal format is transmitted through a control channel as a preamble and an ID code as data during one burst. Upon receiving the modulated carrier, the modulated carrier is converted into I and Q baseband signals, and the baseband signals are input respectively.
The processor to be activated is the local oscillator frequency as the first adjustment
Frequency sweep by command to voltage controlled oscillator
While monitoring the baseband signal, the baseband signal
Is returned to the transmitting side when the data becomes readable as the above data , and then, among the signals transmitted via the communication channel, the known signal of the pattern added to the audio data is used. The output frequency of the voltage controlled oscillator
A frequency control method in a delay detection demodulator for a π / 4 shift QPSK modulated wave signal, which is finely adjusted as a two-step adjustment .