JP3274203B2 - Clock recovery circuit of MSK demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MSK demodulator used, for example, for a receiver of an MSK digital transmission system using a communication satellite, and more particularly to a clock recovery circuit for recovering a clock for MSK demodulation from a received signal. Regarding improvement.

[0002]

2. Description of the Related Art As is well known, one of the frequency shift keying systems is an MSK (Minimum Shift Keying) modulation system. This MSK modulation method modulates two frequencies f1 and f2 with a modulation index of 0.5 at a time width interval of T = 1 / f0 obtained by equally dividing one second by f0. is there. The MSK demodulator for demodulating the MSK modulated wave needs to reproduce a clock synchronized with the MSK modulated wave.

A conventional clock recovery circuit of an MSK demodulator inputs an MSK modulated wave to a waveform shaping filter (normalized bandwidth B · Ts = 1.0 to 1.2) 11 as shown in FIG. After removing all clock harmonic components, the FM detection circuit 12 performs FM detection. Therefore, the only frequency component that can be used as a reference for the phase comparator 13 is the clock frequency.

On the other hand, a VCXO (voltage controlled crystal oscillator) 1
Reference numeral 4 denotes an oscillator which oscillates and outputs a frequency signal (2 / T) four times the clock frequency of the MSK modulated wave.
The error signal obtained by the phase comparator 13 is supplied to 14 as a control voltage for correction by the loop filter 15, thereby forming a clock recovery phase-locked oscillator. The required clock component (reproduced clock: 1 / 2T) is VCX
It is obtained by dividing the output of O14 by 4 with the 1/4 frequency divider 16. The output of the waveform shaping filter 11 is subjected to quadrature detection with a reproduced carrier by the quadrature detector 17 to obtain demodulated data, and the eye pattern can be viewed.

However, the conventional MSK as described above
In the clock recovery circuit of the demodulator, the clock frequency is used as the reference frequency of the phase comparator.
Looking at the spectrum of the modulated wave, since the clock frequency is in the main lobe, the spectrum due to random modulation becomes a noise component, and there is a problem in clock reproduction with low C / N.

[0006]

As described above, in the clock recovery circuit of the conventional MSK demodulator, it is difficult to realize the clock recovery at a low C / N due to the influence of the spectrum by the random modulation.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to provide a clock recovery circuit of an MSK demodulator which is less affected by a spectrum due to random modulation and can recover a clock at low C / N. With the goal.

[0008]

In order to achieve the above object, a clock recovery circuit of an MSK demodulator according to the present invention comprises:
A frequency shift keying method in which a time width interval of T = 1 / f0 in which two frequencies of f1 and f2 are equally divided by one second of f0 on the time axis corresponds to information to be transmitted, and a modulation index of 0.5 A channel filter used for an MSK demodulator for demodulating an MSK modulated wave, passing only a second harmonic component of the MSK modulated wave, and an output of the channel filter
An FM detector for M detection, a low-pass filter for attenuating the main lobe from this detection output, and an oscillation frequency four times as high as the clock frequency of the MSK modulated wave, and the oscillation frequency is changed according to the control voltage. A variable voltage controlled oscillator, a first 分 frequency divider for dividing the oscillation output by 2, and a phase output of the ２ frequency divider based on the output of the low-pass filter. A phase comparator that extracts the error signal by comparing,
A loop filter for converting the error signal obtained by the phase comparator into a control voltage of the voltage controlled oscillator, and a second for obtaining a reproduced clock by further dividing the output of the first 1/2 frequency divider by two. １ ／ frequency divider.

[0009]

In the clock recovery circuit of the MSK demodulator having the above configuration, the second harmonic component of the clock is extracted by the channel filter, and the main lobe component of the MSK spectrum is attenuated by the low-pass filter before being input to the phase comparator. Thus, the C / N of the second harmonic component of the clock is improved. In addition, a signal whose C / N is improved is input to a phase comparator as a comparison frequency, and the oscillation frequency of a phase locked oscillator configured with a loop filter, a voltage controlled oscillator, and a first 1/2 frequency divider is controlled. Thus, the operation of the phase locked oscillator is stabilized even at the time of low C / N, and the jitter of the reproduced clock is reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIG.

FIG. 1 shows a clock recovery circuit of an MSK demodulator according to the present invention. In FIG. 1, an input MSK modulated wave is supplied to a channel filter 21 of B · Ts 2.0. This channel filter 21
For example, it is constituted by a Butterworth filter, and passes only the second harmonic component of the clock. The output of the channel filter 21 is supplied to an FM detector 22.

The FM detector 22 is constituted by, for example, a ratio detection circuit, and performs FM detection on an input signal. This detection output has its main lobe attenuated by the low-pass filter 23 and is supplied to the phase comparator 24 as a reference signal.

On the other hand, the VCXO 25 has an oscillation frequency (2 / T) that is four times the clock frequency, and the error signal obtained by the phase comparator 24 is given as a control voltage for correction by the loop filter 26. Thus, a clock recovery phase-locked oscillator is formed. The output of the VCXO 25 is divided by 2 (1 / T) by a 1/2 divider 27, supplied to a phase comparator 24, and compared with a reference signal. The necessary clock component (reproduced clock) can be obtained by further dividing the output of the 1/2 frequency divider 27 by a 1/2 frequency divider 28 (1 / 2T).

The output of the channel filter 21 is subjected to quadrature detection by a quadrature detector 29 using a reproduced carrier, thereby obtaining demodulated data. This demodulated data is supplied to the waveform shaping filter 30. This waveform shaping filter 30
Is composed of, for example, a Gaussian filter and shapes the waveform of demodulated data. An eye pattern can be seen from the demodulated data whose waveform has been shaped.

That is, the clock recovery circuit having the above configuration extracts the second harmonic component of the clock by using B · Ts 2.0 for the channel filter 21, and outputs the main lobe of the MSK spectrum before inputting it to the phase comparator 24. The components are attenuated by the low-pass filter 23. by this,
The C / N of the second harmonic component of the clock can be improved.

The signal having the improved C / N is input to a phase comparator 24 as a comparison frequency, and the oscillation frequency of a phase-locked oscillator constituted with a loop filter 26, a VCXO 25, and a 1/2 frequency divider 27 is obtained. By controlling
The operation of the phase-locked oscillator can be stabilized even at a low C / N, and a reproduced clock with less jitter can be obtained.

However, since the channel filter 21 having a wide bandwidth of B.Ts 2.0 is used, it is necessary to limit a noise band. This is provided in a waveform shaping filter (baseband low-pass filter) after quadrature detection. This can be achieved by:

Therefore, the clock recovery circuit of the MSK demodulator having the above configuration can stably recover the clock at a low C / N, and can perform the MSK demodulation at a low C / N. Since the reproduced clock has little jitter, it is possible to perform MSK demodulation with little fixed deterioration even when the C / N is not low. It should be noted that the present invention is not limited to the above-described embodiment, and can be similarly implemented by various modifications without departing from the gist of the present invention.

[0019]

As described above, according to the present invention, it is possible to provide a clock recovery circuit of an MSK demodulator capable of recovering a clock at a low C / N with little influence of spectrum due to random modulation.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing an embodiment of a clock recovery circuit of an MSK demodulator according to the present invention.

FIG. 2 is a block circuit diagram showing a configuration of a clock recovery circuit of a conventional MSK demodulator.

[Explanation of symbols]

11: Waveform shaping filter, 12: FM detector, 13: Phase comparator, 14: VCXO, 15: Loop filter, 1
6 1/4 frequency divider 17 17 quadrature detector 21 channel filter 22 FM detector 23 low-pass filter 2
4 ... Phase comparator, 25 ... VCXO, 26 ... Loop filter, 27 ... 1/2 frequency divider, 28 ... 1/2 frequency divider, 29 ...
Quadrature detector, 30 ... waveform shaping filter.

Claims (2)

(57) [Claims] 1. A frequency shift keying method in which a time width interval of T = 1 / f0 in which two frequencies f1 and f2 are equally divided by f0 into one second on a time axis changes according to information to be transmitted.
A channel filter that is used in an MSK demodulator that demodulates an MSK modulated wave having a modulation index of 0.5 and passes only the second harmonic component of the MSK modulated wave, and an FM detector that performs FM detection on the output of the channel filter. A low-pass filter for attenuating the main lobe from the detection output, and having an oscillation frequency four times as high as the clock frequency of the MSK modulated wave;
A voltage controlled oscillator that varies an oscillation frequency according to a control voltage, a first 1/2 frequency divider that divides the oscillation output by 2,
A phase comparator for extracting the error signal by comparing the phase of the frequency-divided output of the 分 frequency divider based on the output of the low-pass filter, and converting the error signal obtained by the phase comparator into A loop filter for converting to a control voltage of a voltage controlled oscillator,
A second half frequency divider for further dividing the output of the first half frequency divider by two to obtain a reproduced clock.
Clock recovery circuit of demodulator. 2. The apparatus according to claim 1, further comprising a quadrature detector for quadrature-detecting the output of the channel filter with a reproduction carrier, and a waveform shaping filter for shaping the quadrature detection output to obtain a phase pattern of MSK demodulated data. The clock recovery circuit of the MSK demodulator according to claim 1, wherein