JP2002353835A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver with less number of components that can prevent frequency from being detuned and reduce the effect of a DC offset voltage. SOLUTION: The receiver having a function of converting an RF signal with a frequency fRF of 426 MHz-470 MHz into an IF signal, is configured to comprise a frequency synthesizer 6 that outputs a local signal with a frequency fLO within a band of fRF±fIF (fIF is a frequency decided depending on a channel width and an occupied band) with respect to the frequency fRF of the RF signal, a quadrature mixer 5 that mixes the local signal outputted from the frequency synthesizer 6 with the RF signal to convert the RF signal into the IF signal, a filter 7 that extracts a desired frequency band signal of a positive or a negative frequency from the IF signal outputted by the quadrature mixer 5 and a demodulator 11 that demodulates the signal extracted by the filter 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver for use in wireless communication, and more particularly to a receiver capable of extracting a signal in a desired frequency band with high accuracy, reducing costs and saving space. About technology.

[0002]

2. Description of the Related Art A superheterodyne system is known as a conventional communication system. FIG. 8 is a block diagram showing a configuration of a receiver using the single superheterodyne method. As shown in FIG.
An antenna 102 and an RF BPF (bandpass filter) 103 for extracting a signal in a desired frequency band from an RF signal (high-frequency signal) received via the antenna 102
, A low noise amplifier 104, a mixer 105 for converting an RF signal into an IF signal (intermediate frequency signal), and a local oscillator 10
6, an IF BPF 107 for extracting a signal in a desired frequency band from a signal converted into an IF signal, and a demodulator 108
And a crystal oscillator 109.

The RF received by the antenna 11
The signal is supplied to a mixer 105 via an RF BPF 103 and a low-noise amplifier 104. Further, since the mixer 105 is provided with a local signal output from a local oscillator 106, the RF signal is converted into an IF signal. , And then sent to a subsequent circuit.

In the receiver 101 configured as described above,
It is desired that the components from the low-noise amplifier 104 to the demodulator 108 except for the crystal oscillator 109 be constituted by one IC circuit, but it is difficult to incorporate the IF BPF 107 into the IC circuit.

That is, in the receiver 101 shown in FIG. 8, in order to effectively remove the channel interference signal and the spurious interference signal, the IF BPF 107 is required to have a highly accurate filter performance. In particular, in order to satisfy the standards of STD-T67 and ST30, it is necessary to mount a high-performance inductance. In this case, it is difficult to mount the inductance in an IC circuit.
Must be prepared separately. In other words, the portion surrounded by the chain line “A” shown in FIG. 8 is a component that is integrated into an IC, and the IF BPF 107 is not incorporated in the IC circuit.

For this reason, there have been problems that not only the number of parts is increased, the size of the apparatus is increased, but also the cost is increased.

A receiver 111 using the direct conversion method shown in FIG. 9 is known as a device which does not use the IF BPF 107 described above. The receiver 11
1 is an FS that can simply configure the demodulator 123.
A K (frequency shift keying) modulation method is adopted.

In the receiver 111, a low noise amplifier 112, quadrature mixers 113 and 114, a local oscillator 115, filters 116 and 117, an amplifier 11
8, 119, limiters 120, 121, FSK demodulator 1
23 can be mounted in one IC circuit,
Compared with the receiver 101 shown in FIG. 8, there is no need to attach the IF BPF 107 as an external component, so that the circuit configuration can be simplified and the cost can be reduced.

However, in the receiver 111 shown in FIG.
The reference frequency output from the crystal oscillator 124 may change due to a change in temperature or the like. In this case, detuning occurs between the transmitter and the receiver, and the reception sensitivity deteriorates. There is. To solve this problem, it is necessary to mount an automatic frequency adjustment circuit.

Normally, a DC component noise signal appears in the IF signal after frequency conversion. Therefore, in the direct conversion method, a high-order high-pass filter capable of effectively removing only the DC component and passing only the signal component as much as possible, or a circuit for canceling the DC offset voltage is required. In particular, ST
In order to satisfy narrow band specifications, such as the D-67,30 standard, mounting a high-order high-pass filter increases the scale of an IC circuit and further increases current consumption. Leads to

Therefore, the great advantage of the direct conversion, that is, the advantage of realizing a simple circuit configuration cannot be enjoyed.

[0012]

As described above, in order to satisfy the standard of STD-67, 30 in the conventional receiver, the receiver 101 using the single superheterodyne system is not suitable. There is a problem that mounting parts are required, and the receiver 111 using the direct conversion method is vulnerable to frequency detuning, and the circuit scale is inevitably large in order to remove a DC offset voltage peculiar to the direct conversion method. There was a drawback that it was made.

The present invention has been made to solve such a conventional problem, and has as its object to reduce the number of parts, prevent frequency detuning, and reduce DC. An object of the present invention is to provide a receiver capable of reducing the influence of an offset voltage.

[0014]

In order to achieve the above object, according to the first aspect of the present invention, the frequency fRF is 426.
A function of converting an RF signal in a band of MHz to 470 MHz into an IF signal, and adding or subtracting the band of the frequency fIF of the IF signal to or from the frequency fRF of the RF signal. Local signal generating means for outputting a signal, a quadrature mixer for mixing the local signal output from the local signal generating means and the RF signal, and converting the RF signal into an IF signal, and an output from the quadrature mixer And a demodulator that demodulates a signal extracted by the filter from a desired frequency band signal of one of a positive frequency and a negative frequency from the IF signal to be obtained. It is characterized by satisfying the condition of c).

(A) ｛(channel width) − (exclusive band)
/ 2｝ / 2 = lower limit of fIF band (b) ｛(channel width) + (proprietary band) / 2｝ / 2 =
Upper limit of fIF band (c) When the channel width is 12.5 kHz, the exclusive band is 8.5 kHz or less.

When the channel width is 25 kHz, the occupied band is 8.5 kHz or more and 16 kHz or less.

According to a second aspect of the present invention, the RF signal is modulated by any one of DBPSK, FSK, DQPSK and GFSK, and a demodulator for demodulating the modulation is provided. Features.

According to a third aspect of the present invention, there is provided a clock reproducing means for reproducing a clock frequency at the time of transmitting the RF signal,
Clock synchronizing output means for outputting data from the demodulator in synchronization with the clock signal reproduced by the clock reproducing means.

According to a fourth aspect of the present invention, the received R
RS that outputs an analog signal according to the signal strength of F signal
It is characterized by having SI generation means.

A fifth aspect of the present invention is characterized in that some of the components of the receiver according to the first to fourth aspects are external components, and the other components are integrated into an IC.

According to a sixth aspect of the present invention, the filter is a real band-pass filter for removing unnecessary waves, and one of a positive frequency signal and a negative frequency signal of a signal passed through the real band pass filter. , Which is characterized by comprising an asymmetric polyphase filter for removing

According to a seventh aspect of the present invention, the filter is constituted by an asymmetric polyphase filter for removing one of a positive frequency signal and a negative frequency signal of the IF signal.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a receiver according to an embodiment of the present invention. As shown in the figure, the receiver 1 has a carrier frequency fRF (fRF = 426
(MHz to 470 MHz) RF signal, and a BPF (Band Pass Filter) 3 for extracting a desired frequency component from the RF signal received by the antenna 2
A low-noise amplifier 4 for amplifying an output signal of the BPF 3;
It has a quadrature mixer 5.

Further, a desired signal is obtained from a frequency synthesizer (local signal generating means) 6 for outputting local signals in the I-axis and Q-axis directions to the quadrature mixer 5 and a signal (IF signal) frequency-converted by the quadrature mixer 5. A filter 7 for extracting a signal in a frequency band, and limiters 8 and 9 for binarizing a signal in an I-axis direction and a signal in a Q-axis direction are provided.

When the receiver 1 is not operated for a predetermined time, the shutdown circuit 1 switches to a standby mode.
2 and an RSSI generator (RSSI generator) for monitoring the output levels of the limiters 8 and 9 and switching from the standby mode to the normal operation mode when the output level exceeds a predetermined value.
10 and a demodulator 11 for restoring the IF signal binarized by the limiters 8 and 9 into a baseband signal.

Further, a clock reproducing section (clock reproducing means) 1 for reproducing a clock signal included in the demodulated signal.
4, a clock synchronization output unit (clock synchronization output means) 13 for outputting a demodulated signal in synchronization with the clock signal reproduced by the clock reproduction unit 14, and a remaining amount of a battery (not shown) is monitored. A battery monitor circuit 16 that performs
A reset circuit 15 for transmitting a reset signal to the external CPU when the battery voltage drops.

The components surrounded by a chain line "B" shown in FIG. 1 are mounted on one IC circuit.

FIG. 2 is a block diagram showing a detailed configuration of the quadrature mixer 5 and the filter 7. As shown in the figure, the filter 7 extracts a desired frequency band component of the I-axis signal output from the quadrature mixer 5.
F71 and B for extracting a desired frequency band component of the Q-axis signal
It has a PF 72 and an asymmetric polyphase filter 73 composed of passive elements.

Incidentally, the filter 7 is, as shown in FIG.
Active asymmetric polyphase filter 73 'comprising active elements
May be provided as a filter 7 '. In this case, the BPFs 71 and 72 become unnecessary.

FIG. 4 is a block diagram showing a detailed configuration of the frequency synthesizer 6. As shown in FIG. 4, the frequency synthesizer 6 uses a fraction-N type PLL system, An oscillation circuit 61 that converts the output vibration into a pulse signal and outputs the pulse signal, and crystal correction data for correcting the initial deviation of the crystal oscillator 17 are input, and the frequency is divided according to a shift in the oscillation frequency of the crystal oscillator 17. A correction register 62 for holding ratio correction data, a channel register 63 for storing data (channel setting signal) corresponding to the channel interval, and setting a desired channel frequency in accordance with the channel interval; a correction register 62; A frequency division ratio control unit 64 for setting the frequency division ratio in accordance with the output signal of the register 63.

Further, the variable frequency divider 67 and the variable frequency divider 6
Phase comparator (PFD) 6 for comparing the frequency divided by 7 with the frequency of the pulse signal output from oscillation circuit 61
5, a charge pump 66 that outputs a voltage signal corresponding to the phase shift determined by the phase comparator 65, a loop filter 68, and a voltage-controlled oscillator 69 that outputs a local signal having a reference frequency fLO. I have.

In the present invention, the reference frequency fLO is set in accordance with the standards of STD-T67 and STD-T30. This STD
In the standards of −67 and 30, the channel width and the exclusive band are set as shown in Table 1 below.

[0033]

[Table 1] That is, the exclusive bandwidth is 8.5 with a channel width of 12.5 kHz.
The exclusive band is set to 8.5 kHz to 16 kHz with a channel width of 25 kHz or less or a channel width of 25 kHz.

Then, the frequency fIF of the IF signal is set so as to fall within the ranges shown by the following formulas 1 (lower limit) and 2 (upper limit), and a reference frequency fLO corresponding to the frequency fIF is set.

[0035]

(Equation 1)

(Equation 2) The charge pump 66 has a function of switching the output current in response to an external control signal (charge pump current control signal). By increasing the charge pump current until the PLL loop is locked, The control voltage is increased so that the voltage controlled oscillator 69 oscillates a signal of a desired frequency in a short time. Further, after the loop is locked, the charge pump current is reduced so that the voltage
In addition, the change of the output frequency is prevented and the power consumption is reduced.

FIG. 5 is a block diagram showing a specific configuration of the demodulator 11. The demodulator 11 is, for example, a DBPS
For demodulating an RF signal modulated by a modulation method such as K, FSK, DQPSK, GFSK, etc., a delay unit 21, a multiplier 22, an adder 23, an LPF
(Low-pass filter) 24, multiplexer 25, and limiter 26.

The I-axis signal is multiplied by a first-order delay, a second-order delay, and a third-order delayed Q-axis signal by a multiplier 22. The multiplier 22 multiplies the delayed and third-order delayed I-axis signals respectively. Thereafter, an addition process is performed by the three adders 23, a signal having the highest signal level is selected from these three signals, and the selected signal is output from the multiplexer 25.

Next, the operation of the present embodiment configured as described above will be described. First, the operation of the frequency synthesizer 6 shown in FIG.
The output vibration is converted into a pulse signal by the oscillation circuit 61, and the pulse signal is supplied to the phase comparator 65. The local signal output from the voltage controlled oscillator 69 is divided by the variable frequency divider 67,
5 is supplied. The phase comparator 65 calculates a phase shift between the frequency of the pulse signal output from the oscillation circuit 61 and the frequency of the pulse signal output from the variable frequency divider 67.

The charge pump 66 outputs a voltage signal corresponding to the magnitude of the obtained phase shift. This voltage signal is supplied to a voltage controlled oscillator 69 after unnecessary frequency components are removed by a loop filter 68. Is done. The voltage controlled oscillator 69 outputs a local signal having a desired reference frequency fLO based on the voltage signal.

The correction register 62 receives a crystal correction signal for correcting the initial deviation of the crystal oscillator 17, and stores frequency division ratio correction data corresponding to the deviation of the oscillation frequency of the crystal oscillator 17. You. Then, the division ratio correction data is output to the division ratio control unit 64. Further, the channel register 63 receives a channel setting signal for setting a channel interval and a desired channel, and stores frequency division ratio data corresponding to the channel frequency. And
This division ratio data is output to the division ratio control unit 64.

The frequency division ratio controller 64 sets the frequency division ratio according to the frequency division ratio correction data supplied from the correction register 62 and the frequency division ratio data supplied from the channel register 63.

Next, the operation of the circuit shown in FIG. 1 will be described.
The antenna 2 shown in FIG.
When the RF signal (470 MHz) is received, a signal of a desired band is extracted from the RF signal by the BPF 3 and amplified by the low noise amplifier 4.

Next, the amplified RF signal is supplied to the quadrature mixer 5, and the quadrature mixer 5 supplies the frequency fLO having the I / Q signal (fLO = fRF ±
Since the local signal (fIF) is supplied from the frequency synthesizer 6, they are mixed. As a result, the received RF signal is frequency-converted into an IF signal having a frequency fIF having an I / Q signal (a frequency having a lower limit and an upper limit shown in Equations 1 and 2).

After that, the IF signal is filtered by the filter 7 to remove the interfering wave component, and is binarized by the limiters 8 and 9. The detailed operation of the filter 7 will be described later. Then, the binarized signal is supplied to the demodulator 11. As shown in FIG. 5, the demodulator 11 obtains three delayed signals using the delay unit 21, and selects the signal having the maximum level among them. Thus, occurrence of detuning can be prevented.

As the demodulator 11, FSK (GFSK)
Using I / Q signal for demodulating frequency modulated waves such as
A K quadrature detector or an I / Q signal quadrature detector is used. It is also possible to use a demodulator for demodulating a phase-modulated wave such as DPSK or DQPSK.

The clock reproducing section 14 shown in FIG. 1 reproduces a clock frequency from the demodulated signal and outputs the clock frequency signal to the clock synchronous output section 13. The clock synchronization output unit 13 outputs demodulated data synchronized with the reproduced clock signal to a subsequent device.

Further, since the RSSI generator 12 outputs an analog signal corresponding to the signal strength of the received signal,
The strength of the received signal can be known according to the output signal. By using this signal, the system can be switched between the standby mode and the normal operation mode. That is, in the shutdown circuit 12, the power consumption is reduced by switching the system to the standby mode,
Thereafter, when the signal level detected by the RSSI generator 13 exceeds a predetermined value, the standby mode can be canceled and the mode can be switched to the normal operation mode.

Next, the filter 7 (BPF7) shown in FIG.
1, 72, and the operation of the asymmetric polyphase filter 73) will be described. FIG. 6 is a spectrum arrangement diagram of a signal output from the quadrature mixer 5. In the figure, the horizontal axis represents the magnitude of the frequency, and the vertical axis represents the magnitude of the spectrum. Further, the center of the horizontal axis is a point where the frequency becomes zero.

FIG. 9 shows a spectrum generated when a local signal (S2) having a frequency fLO (= fRF + fIF) is mixed with an RF signal (S1) having a frequency fRF. By using the quadrature mixer 5, ideally, the negative frequency component of the local signal becomes zero, but actually, the negative local signal (S5) which does not become zero but has a frequency (-fLO) is generated. Exists.

Therefore, the spectrum S7 of the frequency fIF is
This is a signal obtained by adding the component S7a based on the image signal indicated by reference sign S3 and the component S7b based on the negative RF signal having the frequency (-fRF) indicated by reference sign S4.

Similarly, the spectrum S of the frequency (-fIF)
8 is the result of adding the component S8a of the positive RF signal of the frequency fRF shown by the symbol S1 and the component S8b of the negative image signal shown by the symbol S6.

Then, in the filter 7 shown in FIG.
The desired IF signal is extracted by passing only the frequency band indicated by the reference symbol S7 from the frequency spectrum indicated by (1). That is, the BPFs 71 and 72 shown in FIG.
6, the frequency bands shown in the regions R1 and R2 in FIG. 6 are selectively passed, and the spectrum of the frequency band shown in the region R3 is suppressed by the asymmetric polyphase filter 73. As a result, it is possible to extract only the spectrum component of the desired frequency fIF. Note that the image signal component shown by the symbol S7b is an unnecessary component and needs to be removed.
Since the image signal component is at a lower level than the desired IF signal, no removal processing is performed.

On the other hand, in the filter 7 'shown in FIG. 3, a desired IF signal is extracted by passing only the frequency band shown by the symbol S7 in the frequency spectrum shown in FIG. That is, the active asymmetric polyphase filter shown in FIG. 3 selectively passes the frequency band indicated by reference symbol R4 in FIG. As a result, similarly to the filter 7, only the spectrum component of the desired frequency fIF can be extracted.

Next, a specific embodiment will be described.
Now, the frequency fIF of the IF signal is 4.8 KHz, and the carrier frequency (RF signal frequency) fRF of the desired wave is 426.0.
The case of 5 MHz will be described as an example. In this configuration,
Channel width 12.5kHz, exclusive bandwidth 8.5kHz
In the case of the following standard, the frequency fIF is included in the range defined by the above-described equations (1) and (2). The frequency fLO of the local signal output from the frequency synthesizer 6 is 426.0548 MHz depending on the setting of the channel setting terminal.
Is output. In this case, the image frequency fimg (= fRF + 2 * fIF) is 426.0596.
MHz, which is set within the band used in the STD-T67, 30 standard.

That is, the channel interval is 12.5 KHz (the exclusive band is 8.5 KHz or less), or the channel interval is 25 KHz.
When the frequency is set at KHz (exclusive band 8.5 kHz to 16 kHz), an IF signal can be extracted without affecting adjacent channels. In Japan, there are no radio signals other than the STD-T67,30 standard transceiver in this frequency band.

Therefore, in an environment where a radio using the receiver is used, a radio having the same standard is very close to the radio, and except for the case where an adjacent channel is used, a strong interference wave in the image frequency can be obtained. Is extremely rare, and a signal of a desired frequency can be selectively extracted.

In the above-described embodiment, an example in which the frequency fIF of the IF signal is set to 4.8 KHz has been described.
An out-of-band interference wave can be effectively removed in a form conforming to the standards of IBSTD-T67,30.

As described above, the receiver 1 according to the present embodiment does not require external parts, as compared with the conventional superheterodyne receiver, so that the circuit can be implemented by one IC (FIG. 1).
(A range surrounded by “B” shown in FIG. 3).
Therefore, cost reduction and space saving can be achieved.

Further, since the frequency fIF of the IF signal is set within the range of the lower limit and the upper limit shown in the above-described equations (1) and (2), the frequencies (positive and negative) slightly separated from the point where the frequency becomes zero
Or negative), a spectrum of the IF signal is generated. Therefore, the desired frequency component can be selectively extracted without being affected by the DC component and without being affected by the adjacent channel. Therefore, a circuit for removing the DC component is not required, and the circuit configuration can be simplified.

Further, the demodulator 11 generates three delayed signals, and selects and demodulates the signal having the maximum signal level, so that detuning occurs between the transmitter and the receiver. Even in this case, this can be corrected. Therefore,
It is possible to prevent the reception sensitivity from deteriorating without using the automatic frequency adjustment function.

Although the receiver 1 of the present invention has been described based on the illustrated embodiment, the present invention is not limited to this, and the configuration of each unit may be any configuration having the same function. Can be replaced by

For example, in the above-described embodiment, as shown in FIG. 6, an example has been described in which the negative IF signal is suppressed and the positive IF signal is selectively extracted.
The present invention is not limited to this.
It is also possible to suppress the F signal and extract the negative IF signal.

[0063]

As described above, according to the first and second aspects of the present invention,
According to the invention, the received RF signal is converted into an IF signal by a quadrature mixer, and one of a positive frequency and a negative frequency of the IF signal is selectively extracted by a filter. . Therefore, unlike a conventional superheterodyne receiver, there is no need to externally attach a bandpass filter, and the configuration can be simplified. Further, unlike the conventional direct conversion method, there is no need to mount a circuit for removing a DC component, and space and cost can be reduced.

According to the third aspect of the present invention, the clock signal included in the received RF signal is reproduced and the demodulated data is output, so that the baseband signal synchronized with the received signal can be reproduced.

According to the fourth aspect of the present invention, the strength of the received signal can be monitored by the RSSI generating means, which is useful when switching between the standby mode and the normal mode.

According to the fifth aspect of the present invention, some of the constituent elements constituting the receiver are external parts, and the others are I / O parts.
Since it is C, the entire apparatus can be simply configured.

According to the sixth aspect of the present invention, since the filter is composed of a real band-pass filter and an asymmetric polyphase filter composed of passive elements, unnecessary components are removed.
Only the desired wave can be reliably taken out.

According to the seventh aspect of the present invention, since the filter is configured using the asymmetric polyphase filter using the active element, unnecessary components can be removed and only the desired wave can be reliably extracted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a receiver according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating configurations of a quadrature mixer and a filter.

FIG. 3 is a block diagram illustrating a configuration of a filter using an active asymmetric polyphase filter.

FIG. 4 is a block diagram illustrating a configuration of a frequency synthesizer.

FIG. 5 is a block diagram illustrating a configuration of a demodulator.

FIG. 6 is a signal arrangement diagram of a receiver according to one embodiment of the present invention.

FIG. 7 is a signal arrangement diagram when an active asymmetric polyphase filter is used.

FIG. 8 is a block diagram showing a configuration of a conventional single superheterodyne receiver.

FIG. 9 is a block diagram showing a configuration of a conventional direct conversion receiver.

[Explanation of symbols]

 Reference Signs List 1 receiver 2 antenna 3 BPF (bandpass filter) 4 low-noise amplifier 5 quadrature mixer 6 frequency synthesizer 7, 7 'filter 8, 9 limiter 10 RSSI generator 11 demodulator 12 shutdown circuit 13 clock synchronization output unit 14 clock regeneration unit Unit 15 reset circuit 16 battery monitor 21 delay unit 22 multiplier 23 adder 24 LPF (low-pass filter) 25 multiplexer 26 limiter 61 oscillation circuit 62 correction register 63 channel register 64 division ratio control unit 65 phase comparator 66 charge pump 67 variable Frequency divider 68 Loop filter 69 Voltage controlled oscillator 71, 72 Bandpass filter 73 Asymmetric polyphase filter 73 'Active asymmetric polyphase filter

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Jean-Chlor Aberlie, Belgium B-3001 Kaperd Leaf 60 Inside Anthem Nbuy F-term (reference) 5K004 AA01 AA04 AA05 AA08 BA02 EH01 EH07 FH01 FH08 FK09 JH05 5K020 DD11 DD22 EE05 FF00 GG01 GG04 GG09 GG10 GG11 HH13 MM04 NN08

Claims (7)

[Claims] 1. A frequency fRF of 426 MHz to 470 MH
a function of converting an RF signal in a band of z into an IF signal, and adding or subtracting a band of the frequency fIF of the IF signal to or from a frequency fRF of the RF signal to convert a local signal of a frequency of a band obtained by adding or subtracting the band. A local signal generator for outputting, a quadrature mixer for mixing the local signal output from the local signal generator with the RF signal and converting the RF signal into an IF signal, and an output from the quadrature mixer From the IF signal,
A filter for extracting a desired frequency band signal of one of a positive frequency and a negative frequency, and a demodulator for demodulating a signal extracted by the filter, and satisfying the following conditions (a) to (c): A receiver, characterized in that: (A) {(channel width) − (exclusive band) / 2} / 2 =
Lower limit of fIF band (b) {(channel width) + (proprietary band) / 2} / 2 =
Upper limit of fIF band (c) When the channel width is 12.5 kHz, the exclusive band is 8.5 kHz or less. When the channel width is 25kHz, the exclusive band is 8.5k
Hz or more and 16 kHz or less. 2. The RF signal includes DBPSK, FSK,
A receiver modulated by any one of DQPSK and GFSK, and comprising a demodulator for demodulating the modulation scheme. 3. A clock recovery means for recovering a clock frequency at the time of transmitting the RF signal, and a clock synchronization output means for outputting data from the demodulator in synchronization with the clock signal recovered by the clock recovery means. 3. The receiver according to claim 1, further comprising: 4. The receiver according to claim 1, further comprising RSSI generating means for outputting an analog signal according to the signal strength of the received RF signal. 5. A receiver characterized in that some of the components of the receiver according to claim 1 are used as external parts, and the other components are integrated into an IC. 6. A real band-pass filter for removing unnecessary waves, and an asymmetric polyphase filter for removing one of a positive frequency signal and a negative frequency signal of a signal passing through the real band-pass filter. The receiver according to any one of claims 1 to 5, comprising: 7. The filter according to claim 1, wherein the filter comprises an asymmetric polyphase filter for removing one of a positive frequency signal and a negative frequency signal of the IF signal. The receiver according to claim 1.