JPH05276087A - Data receiver - Google Patents

Abstract

PURPOSE:To extend a reception frame of intermittent reception by absorbing a phase difference of transmission clocks caused in a non-reception frame during an intermittent reception state. CONSTITUTION:A demodulator 7 generates a recovered clock reference signal 56 from a received radio wave and generates reproduction data 57 in a timing of a recovered transmission clock 59 from a variable frequency divider circuit 11. A switch 10 is used to connect a PLL 9 to the variable frequency divider circuit 11 at the continuous reception state, the PLL 9 is used to detect a phase difference between a recovered clock reference signal 56 and the recovered transmission clock 59 and to control the variable frequency divider circuit 11 for phase tracking. A counter 13 counts a control signal 61 of the PLL 9. The switch 10 is used to connect the counter 13 to the variable frequency divider circuit 11 just before a reception frame during intermittent reception thereby correcting the phase of the recovered transmission clock 59 generated by the variable frequency divider circuit 11 based on a control signal 64 in response to the count.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data receiving device used for mobile communication such as a digital car telephone.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional data receiving apparatus. In FIG. 3, reference numeral 1 is a modulator, and transmission data 5
1. Transmission transmission clock 52 generated by the oscillator 2 on the transmission side
To generate a modulated wave 53. A transmitter 3 generates a transmission radio wave 54 from the modulated wave 53 and transmits it from the transmission antenna 4. Reference numeral 5 denotes a receiver, which generates a reception wave 55 from the transmission radio wave 54 received by the reception antenna 6. A demodulator 7 detects the received wave 55 and reproduces the reference clock signal 5
6 is generated, the reception wave 55 is detected at the timing of the reproduction transmission clock 59, and reproduction data 57 is generated. 8 is a transmission clock recovery circuit, which is a PLL (Phase
Lock Loop) 9 and a variable frequency dividing circuit 11 to generate a reproduction transmission clock 59. Reference numeral 12 is an oscillator on the receiving side, which supplies an operation clock 58 to the variable frequency dividing circuit 11. Reference numeral 14 is a control circuit of the data receiving device.

The above structure will be described in more detail below along with the operation thereof. On the data transmission side, the modulator 1 generates a modulated wave 53 from the transmission data 51 and the transmission transmission clock 52 supplied from the oscillator 2 and sends it to the transmitter 3. The transmitter 3 generates a transmission radio wave 54 from the modulated wave 53 and transmits it from the transmission antenna 4.

On the other hand, on the data receiving side, the transmitted radio wave 54
Is received by the receiver 5 via the receiving antenna 6, and the received wave 5
5 is generated and sent to the demodulator 7. Demodulator 7 receives wave 5
5 is detected to generate a reproduction clock reference signal 56, and the reception wave 55 is detected at the timing of the reproduction transmission clock 59 sent from the variable frequency dividing circuit 11 of the transmission clock reproduction circuit 8 to generate reproduction data 57. , Control circuit 14
Send to.

Variable divider circuit 1 of transmission clock recovery circuit 8
Reference numeral 1 variably divides the operation clock 58 from the oscillator 12 to generate a reproduction transmission clock 59. Based on the content of the reproduction data 57, the control circuit 14 manages the intermittent reception timing of receiving one to several frames in the super frame when the mobile station waits for an incoming call. In the reception frame, the PLL 9 operates according to the control signal 60 from the control circuit 14, and the PLL 9 detects the phase difference between the reproduction clock reference signal 56 and the reproduction transmission clock 59 and follows the phase by the variable frequency dividing circuit 11.
To the control signal 61. The variable frequency dividing circuit 11 normally divides the frequency into 1 / n, but the frequency dividing ratio is changed from 1 / n to 1 / l (l> n) or 1 / m (m <n) by the control signal 61.
And switch to variable frequency division. Therefore, even if the transmission transmission clock 52 and the operation clock 58 on the reception side are asynchronous, the reproduction transmission clock 59 synchronized with the transmission transmission clock 52 can be generated. In the non-reception frame, the PLL 9 is stopped by the control signal 60 from the control circuit 14, and the variable frequency dividing circuit 11 is controlled to perform fixed frequency division (1 / n).

As described above, in the conventional data receiving apparatus, the reproduction transmission clock 5 that follows the transmission clock 52 on the transmission side is used.
8 can be generated.

[0007]

However, in the above-mentioned conventional data receiving apparatus, the receiver 5 and the demodulator 7 are stopped and the clock recovery operation is stopped in the non-reception frame of the intermittent reception, so that the variable frequency dividing circuit is used. 11 is a fixed frequency division of the oscillator 12 on the receiving side. Therefore, when the time of the non-reception frame becomes long, a phase difference occurs between the transmission transmission clock 52 and the reproduction transmission clock 59 due to the relative accuracy of the transmission side transmission clock 52 and the reception side variable frequency dividing circuit operation clock 58. An error occurs during intermittent reception. Further, in order to suppress the occurrence of the phase difference, it is necessary to have the oscillators 2 and 12 with high accuracy.

The present invention solves such a conventional problem by reducing the phase difference between the regenerative transmission clock and the transmission transmission clock without using a highly accurate oscillator, and thereby eliminating non-reception frames for intermittent reception. Therefore, the power consumption can be reduced, the weight of the battery can be reduced, the standby time can be extended, and the oscillator can be downsized and the price can be reduced. It is an object of the present invention to provide a data receiving device that can be used.

[0009]

In order to achieve the above object, the present invention provides a receiving means for receiving a transmission radio wave, a reproduction clock reference signal from the reception radio wave, and reproduction data at the timing of the reproduction transmission clock. , A variable frequency dividing means for dividing the operating clock to generate the reproduction transmission clock, a phase difference between the reproduction clock reference signal and the reproduction transmission clock, and a control signal for the variable frequency division. The phase difference detecting means for sending the frequency division ratio to the means and changing the division ratio to correct the phase of the reproduction transmission clock, and the control signal sent from the phase difference detecting means to the variable frequency dividing means are counted, and are counted according to the count number. To the variable frequency dividing means by switching the counting means for outputting a control signal to the variable frequency dividing means and the control signal output from the phase difference detecting means and the counting means. It is obtained by a switching means for output.

[0010]

Therefore, according to the present invention, the demodulation means generates the reproduction clock reference signal from the radio wave received by the reception means, and the reproduction data is generated at the timing of the reproduction transmission clock. During continuous reception, the phase difference detecting means is connected to the variable frequency dividing means by the switching means, the phase difference detecting means detects the phase difference between the reproduction clock reference signal and the reproduction transmission clock, and the variable frequency dividing means is adapted to follow the phase. Can be controlled to correct the phase of the regenerated transmission clock, and a regenerated transmission clock that follows the transmission clock of the transmitting side can be generated. During this period, the counting means counts the control signal from the phase difference detecting means for the variable frequency dividing means, and the switching means connects the counting means to the variable frequency dividing means immediately before the reception frame during the intermittent reception, and the control means responds to the count number. By outputting the control signal to the variable frequency dividing means, it is possible to correct the phase shift between the transmission transmission clock and the reproduction transmission clock generated in the non-reception frame during intermittent reception.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing a data receiving apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a modulator, which generates a modulated wave 53 by transmission data 51 and a transmission transmission clock 52 generated by the oscillator 2 on the transmission side. A transmitter 3 generates a transmission radio wave 54 from the modulated wave 53 and transmits it from the transmission antenna 4. 5 is a receiver, and a receiving antenna 6
A reception wave 55 is generated from the transmission radio wave 54 received in. 7
Is a demodulator, which detects the received wave 55 to generate a reproduction clock reference signal 56 and also reproduces the transmission clock 59.
The reception wave 55 is detected at the timing of, and the reproduction data 57 is generated. 8 is a transmission clock recovery circuit, which is a PLL
(Phase Lock Loop) 9, a switch 10, and a variable frequency dividing circuit 11,
To generate. Reference numeral 12 is an oscillator on the receiving side, which supplies an operation clock 58 to the variable frequency dividing circuit 11. Reference numeral 13 is a counter, and 14 is a control circuit of the receiving device.
Controls the PLL 9, switch 10 and counter 13. That is, the PLL 9 operates or stops according to the control signal 60 from the control circuit 14, and outputs the control signal 61 to the variable frequency dividing circuit 11 via the switch 10 during operation. In addition, the counter 13 is switched from the PLL 9 to the switch 1 by the measurement timing signal 62 from the control circuit 14.
Control signal 61 sent to the variable frequency dividing circuit 11 via 0
Is output, and a control signal 64 for the variable frequency dividing circuit 11 is output via the switch 10 according to the output timing signal 63 from the control circuit 14. The switch 10 is switched and controlled by a control signal 65 from the control circuit 14, and selectively sends the control signal 61 from the PLL 9 and the control signal 64 from the counter 13 to the variable frequency dividing circuit 11.

The above construction will be described in more detail below along with the operation thereof. On the data transmission side, modulator 1
Generates a modulated wave 53 from the transmission data 51 and the transmission transmission clock 52 supplied from the oscillator 2 and sends it to the transmitter 3. The transmitter 3 generates a transmission radio wave 54 from the modulated wave 53 and transmits it from the transmission antenna 4.

On the other hand, on the data receiving side, the transmitted radio wave 54 is received by the receiver 5 via the receiving antenna 6, and the received wave 55 is received.
Is generated and sent to the demodulator 7. The demodulator 7 receives the received wave 55
Of the received wave 5 at the timing of the reproduced transmission clock 59 transmitted from the variable frequency dividing circuit 11 of the transmission clock generation circuit 8.
5 is detected and reproduction data 57 is generated and sent to the control circuit 14.

Based on the content of the reproduction data 57, the control circuit 14 determines whether 1 to 1 in the super frame when the mobile station waits for an incoming call.
It manages the timing of intermittent reception for receiving several frames. The control circuit 14 performs continuous reception before shifting to intermittent reception. At this time, the switch 1 is switched by the switch control signal 65.
0 is switched to the PLL 9 side and the PLL 9 is operated by the control signal 60. The PLL 9 detects the phase difference between the reproduction clock reference signal 56 and the reproduction transmission clock 59,
The variable frequency dividing circuit 1 via the switch 10 so that the reproduction transmission clock 59 follows the reproduction clock reference signal 56 in phase.
The control signal 61 is output to 1. The variable frequency dividing circuit 11 normally divides the operation clock 58 from the oscillator 12 into 1 / n to generate a reproduction transmission clock 59.
The division ratio is 1 / n to 1 / l (l> n), or 1
/ M (m <n). Therefore, even if the transmission transmission clock 52 and the operation clock 58 on the reception side are asynchronous, the reproduction transmission clock 59 synchronized with the transmission transmission clock 52 can be generated. Also, the control circuit 1
4 counts the control signal 61 during one superframe 102 composed of a plurality of frames 101 at the time of continuous reception shown in FIG. The counter 13 counts the control signal 61 sent from the PLL 9 to the variable frequency dividing circuit 11 during the measurement timing.

In the non-reception frame 103 during the intermittent reception shown in FIG.
The LL9 is stopped, and the variable frequency dividing circuit 11 controls the operation clock 58 sent from the oscillator 12 so as to perform a fixed frequency division (1 / n). The control circuit 14 outputs the switch control signal 65 at 105 immediately before the reception frame 104 shown in FIG.
The switch 10 is switched to the counter 13 side, and the output timing signal 63 is sent to the counter 13. The counter 13 generates a control signal 64 according to the control signal 61 generated during continuous reception of one superframe 102 by the output timing signal 63, and outputs the control signal 64 to the variable frequency dividing circuit 11 via the switch 10. Similarly to the above, the variable frequency dividing circuit 11 generates the reproduction transmission clock 59 synchronized with the transmission transmission clock 52 and corrects the phase generated in one super frame 102.

The control circuit 14 again switches the switch 10 to the PL by the switch control signal 65 during the reception frame.
Switch to L9 side and PL by control signal 60
Operate L9. As a result, PLL9
The control signal 61 from 1 is transmitted to the variable frequency dividing circuit 11 via the switch 10, and the variable frequency dividing circuit 11 generates the reproduction transmission clock 59 synchronized with the transmission transmission clock 52.

As described above, according to the above embodiment, the phase difference between the transmission transmission clock 52 and the reproduction transmission clock 59 generated in the non-reception frame 103 during intermittent reception is variable-divided immediately before the reception frame 104. Since the correction can be performed on the circuit 11 by the control signal 64 generated by the counter 13, it is possible to suppress the occurrence of an error caused by the phase shift of the clock in the reception frame 104.

[0020]

As described above, according to the present invention, the demodulation means generates the reproduction clock reference signal from the radio wave received by the reception means, and the reproduction data is generated at the timing of the reproduction transmission clock. During continuous reception, the phase difference detecting means is connected to the variable frequency dividing means by the switching means, the phase difference detecting means detects the phase difference between the reproduction clock reference signal and the reproduction transmission clock, and the variable frequency dividing means is adapted to follow the phase. Can be controlled to correct the phase of the regenerated transmission clock, and a regenerated transmission clock that follows the transmission clock of the transmitting side can be generated. During this time, the count means counts the control signal from the phase difference detection means for the variable frequency division means, and the switching means connects the count means to the variable frequency division means immediately before the reception frame during the intermittent reception,
By outputting the control signal corresponding to the count number to the variable frequency dividing means, it is possible to correct the phase shift between the transmission transmission clock and the reproduction transmission clock generated in the non-reception frame during intermittent reception. Since the phase difference of the transmission clock generated in the non-reception frame during intermittent reception can be corrected immediately before the reception frame in this way, the non-reception time of intermittent reception can be lengthened even if the accuracy of the oscillator is low. it can. Therefore, it is possible to reduce the power consumption, reduce the weight of the battery, extend the standby time, and reduce the size and cost of the oscillator in a mobile device for mobile communication.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a data receiving device according to an embodiment of the present invention.

FIG. 2A is an explanatory diagram of a continuous reception operation of the data receiving device, and FIG. 2B is an explanatory diagram of an intermittent reception operation of the data receiving device.

FIG. 3 is a schematic block diagram showing a conventional data receiving device.

[Explanation of symbols]

 1 modulator 2 oscillator 3 transmitter 4 transmitting antenna 5 receiver 6 receiving antenna 7 demodulator 8 transmission clock recovery circuit 9 PLL (Phase Lock Loop) 10 switch 11 variable frequency divider circuit 12 oscillator 13 counter 14 control circuit 51 transmission data 52 Transmitted transmission clock 53 Modulated wave 54 Transmitted wave 55 Received wave 56 Reproduced clock reference signal 57 Reproduced data 58 Variable frequency divider circuit operation clock 59 Regenerated transmission clock 60 PLL control signal 61 Variable frequency divider circuit control signal (PLL output) 62 Measurement timing signal 63 Output timing signal 64 Variable divider circuit control signal (counter output) 65 Switch control signal

Claims (1)

[Claims] 1. A receiving means for receiving a transmission radio wave, a demodulation means for generating a reproduction clock reference signal from the reception radio wave and generating reproduction data at a timing of a reproduction transmission clock, and an operation clock for dividing the reproduction clock to reproduce the reproduction data. A variable frequency dividing means for generating a transmission clock, a phase difference between the reproduction clock reference signal and the reproduction transmission clock is detected, a control signal is sent to the variable frequency division means, and the frequency division ratio is switched to change the phase of the reproduction transmission clock. Phase difference detection means for performing correction, counting means for counting control signals sent from the phase difference detection means to the variable frequency dividing means, and outputting control signals to the variable frequency dividing means according to the number of counts, A data receiving apparatus comprising: the phase difference detecting means and a switching means for switching a control signal output from the counting means and sending the control signal to the variable frequency dividing means.