KR0141641B1 - Data recovery circuit of data communication system - Google Patents

Abstract

[Technical field to which the invention described in the claims belong]

The present invention relates to a circuit for restoring data at a receiving side of a data communication system that performs data communication between data terminals via a data communication network.

[Technical Problem to Solve]

When the data transmission network does not have a large transmission speed difference, an error occurs when restoring data, or when a specific frame is generated and transmitted, the efficiency of the transmission path is reduced and the redundancy is increased.

[Summary of the solution of the invention]

The reception clock signal recovered from the reception data is divided at a predetermined division ratio to generate a recovery clock signal according to the data terminal. The phase of the recovery clock signal is synchronized with the local clock signal, and the reception data is shifted for one period of the reception clock signal. . After detecting whether the synchronization pattern is correct or not, one of the original received data and the shifted received data is selected and restored according to the detection result.

[Important Uses of the Invention]

It is used for DCE of data communication system that does not have big difference in data transmission speed or generates and transmits specific frame.

Description

Data restoration circuit of data communication system

1 is a block diagram of a general data communication system

2 is a transmission timing diagram of FIG.

3 is a timing diagram of reception and data recovery of FIG.

4th frame format diagram of the Eurocom class 1

5 is a block diagram of a data recovery circuit according to the present invention.

6 is an operation timing diagram of the DPLL circuit 30 of FIG.

7 is a data recovery timing diagram of FIG.

* Explanation of symbols for main parts of the drawings

18: dividing circuit 20: counter

22: phase comparison church 24: shift circuit

26: data restoration circuit 28: synchronization pattern detection circuit

30: DPLL circuit

The present invention relates to a data communication system for performing data communication between data terminals via a data communication network, and more particularly to a data recovery circuit for restoring data at a receiving side.

In general, when a data terminal having a transmission speed such as 2.4 kbps, 4.8 kbps, 9.6 kbps, or 19.2 kbps is intended for data communication via a data communication network having a transmission speed of 16 kbps or 32 kbps, the transmission speed of the data terminal and the transmission of the communication network are Since speed is not proportional, restoring overlapping data from the network is not straightforward.

1 is a block diagram of a general data communication system for communicating between data terminals via a data communication network. Assuming that the first data terminal 10 transmits to the second data terminal 16 in FIG. 1, the first data circuit-terminating equipment (DCE) 12 transmits from the first data terminal 10. The data is transmitted to the data communication network at a baud rate of 32 kbps. At this time, the second DCE 14 restores 32 kbps of data at the transmission rate of 9.6 kbps and transmits the data to the second data terminal 16. FIG. 2 shows the data recovery timing of the second DCE 14 at the receiving side in the data communication system as described above, (A) shows transmission data of 9.6 kbps, and (B) shows that the 2DCE 14 has data. Data received via the communication network is shown, (C) shows the recovery clock signal of the second DCE 14, (D) shows the recovered data. As can be seen in Figure 2, there is a restoration data error.

On the other hand, as a conventional data restoration method, there is a RMVD (Running Majerity Voting Decoding) method. In the RMVD method, when data is multi-sampled in DCE and transmitted, the multi-sampled data is received in DCE again, and the multi-sampled result is decoded in the third side. 3 is a reception and data recovery timing diagram. FIG. 3A shows reception data, and FIG. 3B shows multisampling with a clock of 32 kbps. However, the RMVD method is suitable when the data transmission speed of the data terminal and the data communication network are large, but is not suitable for transmitting data of 9.6kbps and 19.2kbps at the data communication speed of 16kbps or 32kbps.

Another method for restoring data is to create a specific frame and carry 9.6kbps data in the frame, an example of which is shown in FIG. FIG. 4 has the advantage of restoring to some extent an error on a transmission path in the same manner as Class 4 of EUROCOM. However, there is a disadvantage in that redundancy is increased because only 9.6kbps of actual data is transmitted in a transmission capacity of 32kbps. In addition, there is a disadvantage in that many circuits are required to configure such a data recovery circuit.

Accordingly, an object of the present invention is to provide a data recovery circuit capable of recovering data accurately even when the transmission speed of the data communication network is not large.

Another object of the present invention is to provide a recovery circuit that can improve transmission efficiency and reduce redundancy even when generating and transmitting a specific frame.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 shows a block diagram of a data recovery circuit according to the present invention. In FIG. 5, the frequency divider 18 divides the received clock signal RCLK of 32 KHz recovered from the received data into 10 to generate a clock signal of 3.2 KHz. The counter 20 and the phase comparator 22 constitute a digital phase locked loop (hereinafter referred to as a DPLL) and synchronize a 3.2 KHz clock signal with a 4 MHz local clock signal SCLK. The counter 20 counts up and down the local clock signal SCLK corresponding to the phase comparison result of the phase comparison circuit 22 to generate clock signals of phase synchronized 3.2KHz and 9.6KHz. The phase comparison circuit 22 compares and detects the phase of the 3.2 KHz clock signal of the frequency divider circuit 18 and the counter 20. The shift circuit 24 shifts the reception data for one period by the reception clock signal RCLK. The data recovery circuit 26 selects and restores the correct reception data from the original reception data and the shifted reception data. The sync pattern detecting circuit 28 detects whether the sync pattern is correct from the output data of the data restoring circuit 26 and generates a selection signal for selecting one of the original received data and the shifted received data according to the detection result. It is applied to the restoration circuit 26.

In the configuration of FIG. 5, the data recovery circuit 26 and the synchronization pattern detection circuit 28 use circuits commonly used in data communication systems.

FIG. 6 is an operation timing diagram of the DPLL 30 of FIG. 5, where (A) shows a clock signal of 3.2 KHz output from the frequency divider circuit 18, and (B) shows 3.2 KHz output from the counter 20. FIG. (C) shows the clock signal output from the counter 20 at 9.6 KHz.

FIG. 7 is a data recovery timing diagram of FIG. 5, where (A) shows received data directly inputted to the data recovery circuit 26 via path 1, and (B) is shifted by the shift circuit 24. FIG. Receive data input to the data recovery circuit 26 via path 2, (C) is a clock signal of 9.6KHz output from the counter 26, (D) is a data recovery circuit 26 The restored data is shown.

An operation example of FIG. 5 according to the present invention will now be described in detail with reference to the timing diagrams of FIGS. 6 and 7.

First of all, the basic algorithm of the present invention is to recover the data by tracking the phase of the transmitting data by using the DPLL.

The recovery clock signal RCLK input to the frequency division circuit 18 and the shift circuit 24 of FIG. 5 is a 32 KHz clock signal recovered from 32 kbps data received from the data communication network, and the local clock signal SCL is a 4 MHz local signal generated by the DCE. Clock signal.

When the 4 MHz local clock signal SCLK is divided by 10, a clock signal of 3.2 KHz is generated, which has no phase relationship with the recovery clock signal RCLK of 32 KHz. However, in order to restore the data, it is necessary to constantly adjust the phase between the two clock signals. Therefore, the recovery clock signal RCLK is divided by 10 in the division circuit 18 to generate a 3.2KHz clock signal, and the 3.2KHz clock signal generated locally with this clock signal is compared with the phase comparison unit 22 and the up / down counter 20. The phase is adjusted by the DPLL 30 constructed by using.

Therefore, the 9.6 KHz clock signal as shown in FIG. 6 (C) output from the counter 20 has a constant phase relationship P with the recovery clock signal RCLK as shown in FIG. However, even if the reception data and the clock signal of 9.6KHz have a constant phase relationship P, if the reception data is latched to the clock signal of 9.6KHz as shown in Fig. 7, a data error occurs.

Accordingly, the shift circuit 24 shifts the received data by one period of 32 KHz by the recovery clock signal RCLK, and selects the correct path by synchronizing the original received data and the shifted received data with the sync pattern detection circuit 28. The data restored from the received data through the selected path is recognized as the correct restoration data. FIG. 7 shows an example in which data inputted to the data recovery circuit 26 through the path 2 after being shifted by the shift circuit 24 is recognized as correct data and restored.

As described above, the present invention has the advantage of not only restoring data accurately even when the transmission speed difference of the data communication network is not large, but also improving the efficiency of the transmission path and reducing redundancy even when generating and transmitting a specific frame. .

Claims (4)

A data recovery circuit of a data communication system, comprising: a division means for dividing a reception clock signal recovered from reception data at a predetermined division ratio to generate a recovery clock signal according to a data terminal; and a phase of the local clock signal and a phase of the recovery clock signal. Clock synchronizing means for synchronizing, shifting means for shifting the received data for one period of the received clock signal, data restoring means for selecting and restoring the correct received data from the original received data and the shifted received data; A synchronization pattern detection means for detecting whether the synchronization pattern is correct from the output data of the data recovery means and generating a selection signal for selecting one of the original received data and the shifted received data according to the detection result and applying it to the data recovery means. And a data recovery circuit. A data recovery circuit according to claim 1, wherein said clock synchronizing means is a digital phase synchronizing circuit. A data recovery circuit of a data communication system, comprising: a divider means for dividing a 32 KHz received clock signal recovered from received data to generate a 3.2 KHz restored clock signal corresponding to a data terminal, and a phase of the restored clock signal of 4 MHz; Clock synchronizing means for synchronizing with a local clock signal, shifting means for shifting the received data for one period of the received clock signal, and data restoration for selecting and restoring the correct received data from the original received data and the shifted received data; Means for detecting whether the synchronization pattern is accurate from the output data of the data recovery means, and generating and applying a selection signal for selecting one of the original received data and the shifted received data to the data recovery means according to the detection result. A data restoration circuit comprising a pattern detecting means. The counter according to claim 3, wherein the clock synchronizing means up / down counts the local clock signal by a predetermined control signal to synchronize the phase of the recovery clock signal and generate a clock signal of 9.6 KHz; And a phase comparator for comparing a phase of a clock signal of 3.2 KHz of a counter to detect a phase difference and controlling an up / down counter of the counter in response to the phase difference.