KR970004502A - Data restoration circuit of data communication system - Google Patents

Data restoration circuit of data communication system Download PDF

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Publication number
KR970004502A
KR970004502A KR1019950017099A KR19950017099A KR970004502A KR 970004502 A KR970004502 A KR 970004502A KR 1019950017099 A KR1019950017099 A KR 1019950017099A KR 19950017099 A KR19950017099 A KR 19950017099A KR 970004502 A KR970004502 A KR 970004502A
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KR
South Korea
Prior art keywords
data
clock signal
received
received data
phase
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Application number
KR1019950017099A
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Korean (ko)
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KR0141641B1 (en
Inventor
김규학
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김광호
삼성전자 주식회사
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Priority to KR1019950017099A priority Critical patent/KR0141641B1/en
Publication of KR970004502A publication Critical patent/KR970004502A/en
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Publication of KR0141641B1 publication Critical patent/KR0141641B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

데이타 통신망을 경우하여 데이타단말간 데이타통신을 하는 데이타 통신시스템의 수신측에서 데이타를 복원하는 회로에 관한 것이다.The present invention relates to a circuit for restoring data at a receiving side of a data communication system that performs data communication between data terminals in a data communication network.

2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention

데이타 통신망의 전송속도차가 크지 않은 경우에 데이타 복원시 오류가 발생하거나 특정 프레임을 생성하여 전송할 경우전송로의 효율이 저하되며 용장도가 커지는 것을 개선한다.When the data transmission network does not have a large transmission speed difference, an error occurs when restoring data, or when a specific frame is generated and transmitted, the efficiency of the transmission path is reduced and the redundancy is increased.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

수신데이타로부터 복원한 수신클럭신호를 미리 설정된 분주비로 분주하여 데이타단말에 따른 복원클럭신호를 생성한후 복원클럭신호의 위상을 국부클럭신호와 동기시키며 수신데이타를 수신클럭신호의 1주기동안 쉬프트시킨다. 그리고 동기패턴의 정활여부를 검출하고 검출 결과에 따라 원래의 수신데이타와 쉬프트된 수신데이타중 하나를 선택하여 복원한다.The received clock signal recovered from the received data is divided at a predetermined division ratio to generate a restored clock signal according to the data terminal, and then the phase of the recovered clock signal is synchronized with the local clock signal and the received data is shifted for one period of the received clock signal. . Then, whether the synchronization pattern is smoothed is detected and one of the original reception data and the shifted reception data is selected and restored according to the detection result.

4. 발명의 중요한 용도4. Important uses of the invention

데이타 통신망의 전송속도차가 크지 않거나 특정 프레임을 생성하여 전송하는 데이타 통신시스템의 DCE에 사용된다.It is used for DCE of data communication system that does not have big difference in data transmission speed or generates and transmits specific frame.

Description

데이타 통신시스템의 데이타 복원회로Data restoration circuit of data communication system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도는 본 발명에 따른 데이타 복원회로의 블럭구성도, 제6도는 제5도의 DPLL회로(30)의 동작 타이밍도, 제7도는 제5도의 데이타 복원 타이밍도.5 is a block diagram of a data recovery circuit according to the present invention, FIG. 6 is an operation timing diagram of the DPLL circuit 30 of FIG. 5, and FIG. 7 is a data recovery timing diagram of FIG.

Claims (4)

데이타 통신시스템의 데이타 복원회로에 있어서, 수신데이타로부터 복원한 수신클럭신호를 미리 설정된 분주비로 분주하여 데이타단말에 따른 복원클럭신호를 생성하는 분주수단과, 상기 복원클럭신호의 위상을 국부클럭신호와 동기시키는 클럭동기수단과, 상기 수신데이타를 상기 수신클럭신호의 1주기동안 쉬프트시키는 쉬프트수단과, 상기 원래의 수신데이타와 쉬프트된 수신데이타중 정확한 수신데이타를 선택하여 복원하는 데이타 복원수단과, 상기 데이타 복원수단의 출력 데이타로부터 동기패턴의 정확여부를 검출 하고 검출 결과에 따라 원래의 수신데이타와 쉬프트된 수신데이타중 하나를 선택하는 선택신호를 발생하여 상기 데이타 복원수단에 인가하는 동기패턴 검출수단을 구성하는 것을 특징으로 하는 데이타 복원회로.A data recovery circuit of a data communication system, comprising: a division means for dividing a reception clock signal recovered from reception data at a predetermined division ratio to generate a recovery clock signal according to a data terminal; and a phase of the local clock signal and a phase of the recovery clock signal. Clock synchronizing means for synchronizing, shifting means for shifting the received data for one period of the received clock signal, data restoring means for selecting and restoring the correct received data from the original received data and the shifted received data; A synchronization pattern detection means for detecting the accuracy of the synchronization pattern from the output data of the data recovery means and generating a selection signal for selecting one of the original received data and the shifted received data according to the detection result and applying it to the data recovery means. And a data recovery circuit. 제1항에 있어서, 상기 클럭동기수단이 디지탈 위상동기회로인 것을 특징으로 하는 데이타 복원회로.A data recovery circuit according to claim 1, wherein said clock synchronizing means is a digital phase synchronizing circuit. 데이타 통신시스템의 데이타 복원회로에 있어서, 수신데이타로부터 복원한 32KHz의 수신클럭신호를 10분주하여 데이타단말에 따른 3.2KHz의 복원클럭신호를 생성하는 분주수단과, 상기 복원클럭신호의 위상을 4MHz의 국부클럭신호와 동기시키는 클럭동기 수단과, 상기 수신데이타를 상기 수신클럭신호의 1주기동안 쉬프트시키는 쉬프트수단과, 상기 원래의 수신데이타와 쉬프트된 수신데이타중 정확한 수신데이타를 선택하여 복원하는 데이타 복원수단과, 상기 데이타 복원수단의 출력 데이타로부터 동기패턴의 정확여부를 검출하고 검출 결과에 따라 원래의 수신데이타와 쉬프트된 수신데이타중 하나를 선택하는 선택신호를 발생하여 상기 데이타 복원수단에 인가하는 동기패턴 검출수단으로 구성하는 것을 특징으로 하는 데이타 복원회로.A data recovery circuit of a data communication system, comprising: a divider means for dividing a 32 KHz received clock signal recovered from received data to generate a 3.2 KHz restored clock signal corresponding to a data terminal, and a phase of the restored clock signal of 4 MHz; Clock synchronizing means for synchronizing with a local clock signal, shifting means for shifting the received data for one period of the received clock signal, and data restoration for selecting and restoring the correct received data from the original received data and the shifted received data; Means for detecting whether the synchronization pattern is accurate from the output data of the data recovery means, and generating and applying a selection signal for selecting one of the original received data and the shifted received data to the data recovery means according to the detection result. A data restoration circuit comprising a pattern detecting means. 제3항에 있어서, 상기 클럭동기수단이 상기 국부클럭신호를 소정 제어신호에 의해 업/다운카운트하여 상기 복원 클럭신호의 위상을 동기시키며 9.6KHz의 클럭신호를 발생하는 카운터와, 상기 분주수단과 카운터의 3.2KHz의 클럭신호의 위상을 비교하여 위상차를 검출하고 위상차에 대응하여 상기 카운터의 업/다운 카운트를 제어하는 위상비교기로 구성하는 것을 특징으로 하는 데이타 복원회로.The counter according to claim 3, wherein the clock synchronizing means up / down counts the local clock signal by a predetermined control signal to synchronize the phase of the restored clock signal and generate a clock signal of 9.6 KHz; And a phase comparator for comparing a phase of a clock signal of 3.2 KHz of a counter to detect a phase difference and controlling an up / down count of the counter in response to the phase difference. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950017099A 1995-06-23 1995-06-23 Data recovery circuit of data communication system KR0141641B1 (en)

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KR1019950017099A KR0141641B1 (en) 1995-06-23 1995-06-23 Data recovery circuit of data communication system

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Application Number Priority Date Filing Date Title
KR1019950017099A KR0141641B1 (en) 1995-06-23 1995-06-23 Data recovery circuit of data communication system

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KR970004502A true KR970004502A (en) 1997-01-29
KR0141641B1 KR0141641B1 (en) 1998-07-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7113380B2 (en) 2003-01-09 2006-09-26 Samsung Electronics Co., Ltd. Power supply device and control method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7113380B2 (en) 2003-01-09 2006-09-26 Samsung Electronics Co., Ltd. Power supply device and control method thereof

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KR0141641B1 (en) 1998-07-01

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