JPH06296184A - Clock regenerating circuit - Google Patents

Abstract

PURPOSE:To provide the clock regenerating circuit with short synchronization pull-in time and insusceptible to effect of jitter with respect to the clock recovery circuit recovering a clock signal subjected to phase synchronization with an input signal. CONSTITUTION:The circuit is provided with a 1/N frequency division counter means 14 frequency-dividing a master clock to generate, a phase adjustment means 4 discriminating a lead/lag of a phase of the recovered clock with respect to the input signal an generating the master clock whose number of pulses is controlled so that the recovered clock approaches a phase of the input signal by a 1/N clock period per one recovered clock period based on the result of discrimination, and a reset means 5 detecting a phase difference between the input signal and the regenerated clock and resetting forcibly the 1/N frequency division counter 14 so that the phase of the recovered clock is synchronously with the phase of the input signal at a succeeding recovery clock period when the phase difference exceeds a prescribed inspection range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit having a large jitter suppressing effect and a short pull-in time.

When demodulating a digital modulation signal such as FSK or PSK, it is necessary to identify and determine the analog signal obtained by demodulation at the optimum timing and convert it into a binary code. A clock recovery circuit (hereinafter, abbreviated as BTR: Bit Timing Recovery) is used for generation.

As a method of realizing this BTR, a method using an analog circuit using a non-linear element such as a rectifier and a filter, a method using a digital circuit using a digital phase locked loop (hereinafter abbreviated as DPLL), and both methods. Some of them are mixed, but in the field of mobile communication in recent years, downsizing of mobile communication terminals is indispensable. For this purpose, it is indispensable to make each part of the device LSI.
TR is also required to be realized by a completely digital circuit.

Further, since the frequency used for wireless communication is finite, the TDMA method is used in the digital portable / car phone system in order to efficiently use it by a large number of users. It is necessary to extract the symbol timing within a predetermined time for each of the burst waves sent from the communication partner and generate a recovered clock that is phase-synchronized with the received signal. Therefore, the BTR is required to have the capability of establishing symbol timing synchronization in a short time and maintaining stable synchronization even under a fading environment peculiar to mobile communication.

[0005]

2. Description of the Related Art FIG. 5 shows a block diagram of a clock recovery unit to which the present invention is applied. This is used for reception demodulation in a mobile communication system using, for example, a QPSK modulation method, and a signal IFD obtained by converting a received radio signal into an intermediate frequency is input to reproduce a symbol timing for data identification. Is.

In the figure, the differential detection circuit 3 is a QPSK.
The IF frequency phase change point is detected from the input IF data IFD of the intermediate frequency 455KHZ of the method, and it is detected at the symbol period of 21KHZ.
It generates a change point detection signal DETD in which "H" and "L" are inverted. That is, the differential detection circuit 3 extracts the phase change detection signal whose level changes in synchronization with the symbol period from the QPSK modulation signal.

The clock recovery unit uses two clock recovery circuits having different loop gains in combination. In FIG. 5, reference numeral 1 is a high-speed BTR having a large loop gain, that is, a small inertia and performing synchronous pull-in at a high speed but a small jitter suppression effect, and 2 is a small loop gain, that is, a large inertia and a large jitter suppression effect, This is a low-speed BTR2 having a long synchronization pull-in time. Then, at the time of initial synchronization pull-in, the high-speed BTR1 is supplied from the high-speed BTR enable signal XHSSTB.
To establish synchronization at high speed, add this phase to the low-speed BTR2 as an initialization signal, and preset as the initial phase to pull in the low-speed BTR2 at high speed.
In the subsequent synchronization state, only the low speed type BTR2 is operated independently to realize a low jitter clock recovery circuit. At this time, the maximum time is defined so that the reproduction clock can be pulled in even when the phase of the received signal is deviated to the maximum during the period in which the high-speed BTR is operated, that is, the period in which the high-speed BTR enable signal XHSSTB is active. Therefore, even if the pull-in is completed early, the preset signal is sent to the low-speed type B during this maximum time.
It continues to output to TR.

FIG. 6 shows a conventional clock recovery circuit used as a high speed synchronous BTR, and FIG. 7 shows an operation time chart thereof. In the figure, reference numeral 1 denotes a clock regenerating circuit, which uses a phase change point detection signal DETD from the preceding differential detection circuit as an input signal to generate a regenerated clock phase-synchronized with the input signal.

The high speed BTR circuit 1 uses the change point detection signal DE.
TD is used as an input signal to generate a reproduction clock by synchronizing the phase with this input signal at the time of synchronization, and generate an initialization signal XBTR that is a timing pulse synchronized with this reproduction clock to reset the initial phase to the low-speed BTR circuit in the next stage. Output as.

That is, the rising edge detection circuit 11 'detects the rising edge of the phase change detection signal DETD from "L" to "H". Then, at each rising detection timing, the B clock of 2.688MHZ is divided by 8 by the clock generation circuit 12a, and two 366KHZ φCK and πCK of Φ phase and π phase, which are 180 degrees different in phase, are created.
Is switched by the selector 12b, and the master clock MCK having a large number of pulses by one pulse is generated just after the switching. The frequency of the master clock MCK is sufficiently higher than the frequency of the input signal (in this case, the received symbol frequency), and has a frequency 16 times, for example. The phase adjustment unit 13 is composed of a lead / lag detection circuit 13a and a clock mask circuit 23b, and the lead / lag detection circuit 13a outputs 16 bits at the timing of the rising edge detection signal.
Is the level of the recovered clock from the frequency division counter 14 "H"?
Monitors whether it is "L", and only when it is "L", clock mask circuit 13
One pulse of the master clock MCK immediately after clock switching is masked in b (a in FIG. 7) and phase adjustment is performed. The 16-divider counter 14 counts this master clock MCK to generate a reproduction clock from the count value,
While feeding back to the lead / lag detection circuit 13a,
The initialization signal generator 15 outputs the initialization signal XBRS, which is synchronized with the reproduction clock and has a small pulse width.
Is generated and output as a reset pulse for setting the initial phase of the low-speed BTR (not shown).

As described above, the phase of the reproduction clock is delayed or advanced by 1/16 clock in the direction of correcting the phase shift between the data change point and the reproduction clock. By repeating this, the recovered clock of the high-speed BTR circuit is the input IF.
A steady state is reached in synchronization with the data change point.

However, even with such a configuration, the synchronization time is limited to about several ms, so that it cannot be used in a system requiring a synchronization time of 1 ms or less, such as a digital car telephone base station.

[0013]

In the high-speed synchronous BTR circuit, for example, the output phase approaches the input phase at every other data change point every one cycle of the frequency division ratio n (for example, 16) of the counter. Therefore, even if the data changes every input signal period, 16 symbol periods are required for phase matching of the maximum phase deviation π, and the symbol frequency is
21 kHz (that is, even if the symbol period is 0.05 msec.
It takes 8 msec. In reality, data change does not occur every cycle, and when the reception level is low due to a burst rise, etc., the delay detection result, that is, the reliability of the data change point detection signal decreases, so a longer time is required. msec
However, there was a problem in practical use because it required a synchronous pull-in time.

The present invention was created in view of the above problems, and it is an object of the present invention to provide a clock recovery circuit which has a short synchronization pull-in time and is less susceptible to jitter.

[0015]

FIGS. 1 and 2 are principle block diagrams of a clock recovery circuit of the present invention. In order to solve the above problems, the clock recovery circuit of the first invention of the present invention is shown in FIG.
As shown in FIG. 3, N-divider counter means for dividing the master clock to generate a reproduced clock having the same frequency as the input signal.
14 and the lead / lag of the phase of the reproduction clock with respect to the input signal is determined, and the number of pulses is controlled based on the determination result so that the reproduction clock approaches the phase of the input signal by 1 / N clock cycle per reproduction clock cycle. The phase adjusting means 4 for generating the master clock and the phase difference between the input signal and the reproduction clock are detected, and when the phase difference exceeds a predetermined verification range, the phase of the reproduction clock is changed in the next reproduction clock cycle. And a reset means 5 for forcibly resetting the N frequency dividing counter so as to be synchronized with the input signal.
In addition, as shown in FIG. 2, the second invention is such that, as shown in FIG. 2, an edge detection unit 11 that detects a change point of an input signal and a two-phase clock signal of φ phase and π phase are switched at the detected change point and the frequency is changed after switching. Of the master clock MCK having a high portion, and whether the phase advance or delay between the input signal and the reproduction clock is judged, and the judgment result immediately after the switching of the pulse train of the master clock MCK is made. A phase adjusting unit 13 that controls the phase of the reproduction clock to approach the input signal depending on whether or not to prohibit one, and the reproduction clock having substantially the same frequency as the input signal is divided by counting the master clock MCK. A first frequency division counter 14 that generates, a second frequency division counter 16 that is reset at the change point of the input signal and counts the master clock, and the first and second frequency division counters at the change point of the input signal. counter It has a phase comparison unit 17 that compares the count values and, when the difference between the two count values exceeds the first set value range, outputs a reset signal to the first frequency division counter at the timing of the change point. Further, the third invention is the initialization signal for generating the initialization signal XBRS at the timing corresponding to the phase of the reproduction clock from the count value of the first frequency division counter, in addition to the second invention. The generation unit 15 is compared with the count values of the first and second frequency division counters, and if the difference between the count values is within the second set value range narrower than the first set value range, the synchronization is performed. The phase comparison unit 17 that outputs the status signal SYN and the synchronization signal S
A synchronization protection unit 18 which outputs a mask signal MSK when it is detected that YN has been continuously output a predetermined number of protection stages n times;
A mask section 19 for stopping the output of the initialization signal XBRS by the mask signal MSK is provided.

[0016]

Since the edge detector detects both the rising edge and the falling edge of the change point detection signal, the phase control information is doubled as compared with the conventional method using only the rising edge.

If the phase difference between the input signal and the reproduced clock is outside the predetermined (first) verification range, the reproduced clock forcibly matched in phase with the input signal is generated.
At the initial synchronization pull-in, a reset pulse synchronized with the input can be supplied to the low speed BTR circuit at high speed. If the high-speed BTR circuit is still in the operating state even after the synchronous pull-in, the change point slightly changes due to the jitter of the input signal and the reset pulse affected by the change is generated every time, but the change width is the second. If it is within the verification range of n times consecutively, the high-speed synchronous BTR circuit judges that the pull-in is completed stably, and masks the reset pulse to the low-speed BTR circuit so as not to output thereafter. As a result, even during the high speed synchronous BTR operation command, the operation is switched to only the low speed synchronous BTR circuit, and a stable reproduced clock that is not affected by jitter can be obtained.

[0018]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 3 is a block diagram of an embodiment of a clock recovery circuit of the present invention,
FIG. 4 is an operation time chart of FIG.

FIG. 3 shows a high-speed synchronization B using a change point detection signal whose level changes between "H" and "L" in synchronization with the symbol period output from the differential detection circuit described above with reference to FIG.
The operation is performed when the TR enable signal XHSSTB is active "L", and the reset pulse XBRS having a timing synchronized with the input signal is output to the low speed BTR section as an initialization signal.

In FIG. 3, 11 is an edge detection circuit, and 12a.
Is a clock generation circuit, 12b is a selector, 13a is a lead / lag determination circuit, 13b is a clock mask circuit, 14 and 16 are 16 frequency division counters, 15 is an initialization signal generation unit, 18 is a synchronization protection circuit, and 19a is
Is a mask generation circuit, and 19b is a mask circuit. The correspondence with FIG. 2 is that the clock generation circuit 12a and the selector 12b form the clock generation unit 12, the lead / lag determination circuit 13a, and the clock mask circuit.
The phase adjustment unit 13 is composed of 13b, and the mask unit 18 is composed of the synchronization protection circuit 18a and the mask generation circuit 18b.
The counter 14 is replaced by the 1/16 counter 16 as the first frequency division counter 14.
Corresponds to the second frequency dividing counter 16, and the phase comparison circuit 17 corresponds to the phase comparison unit 17.

The difference between the circuit of the present invention shown in FIG. 3 and the conventional clock recovery circuit described above with reference to FIG. 6 is that the edge detection circuit 11 is used instead of the rising edge detection circuit.
Since the counter 16, the phase comparison circuit 17, the synchronization protection circuit 18, the mask generation circuit 19a, and the master circuit 19b are provided and the other components and their functions are the same as those of the conventional art, the description thereof will be omitted.

In the present invention, an edge detection circuit 11 for detecting both the rising and falling timings of the input signal is provided in place of the conventional rising detection section to double the number of phase control operations and to provide a second 1/16 counter. 16 is reset by the change point detection signal and outputs the count value indicating the input phase, the phase comparator circuit 17 compares the count values of the two 1/16 counters 14 and 16, and based on the phase comparison, the reproduction clock A reset signal for forcibly synchronizing the input signal with the input signal and a synchronization state signal indicating the synchronization state are output. Then, when the synchronization state signal is output continuously for the predetermined number of protection stages n times, the synchronization protection circuit 18, the mask generation circuit 19a, and the mask circuit 19b stop the output of the initialization signal. In this way, after the synchronization pull-in, even if the high-speed BTR enable signal is active, the reset pulse is not issued to the low-speed BTR.

At the time of normal synchronization pull-in, the phase of the reproduction clock is delayed or advanced by 1/16 clock in the direction of correcting the deviation between the data change point and the reproduction phase by the same operation as the conventional circuit. High-speed BT by repeating this
The recovered clock of the R circuit reaches a steady state in synchronization with the changing point of the input IF data. The above is the normal DPLL operation.

Next, the characteristic part of the present invention will be described with reference to FIG. The second 1/16 counter of 16 is reset by the change point detection signal and counts the master clock MCK 16
It is a decimal counter. In the phase comparison circuit 17, the first verification range and the second verification range can be set from the outside, and the first 1/16 counter 16 has a count value of 0.
It is determined whether the count value of the 1/16 counter 14 is within the verification range, and a signal indicating the verification result is output. For example, it is assumed that the first setting range is set to -4 (= 12) to +3, and the second setting range is set to -2 (= 14) to +1 narrower than the first setting range. The phase comparison circuit 17 includes a frequency division counter 1
The count values of 4,16 are always input, and both count values are compared at the timing of change point detection (that is, the timing when the count value of the second 1/16 counter 16 becomes 0), and the / 16 against the count value 0 of 16 counter, the first 1/16
When the count value of counter 14 is outside the first setting range,
That is, in the case of +5 to -8, it is judged that the phase difference is equal to or more than the threshold value, and the reset pulse RST is output to the first frequency dividing counter. For example, in FIG. 7, since the count value of the first 1/16 frequency division counter 14 is 7 at the time of detection of the change point and the value is out of the first verification range, the reset pulse RST is output and
The 1/16 division counter 14 is forcibly reset at this point. This resets the first 1/16 counter 14,
It is forced to the same phase as the second 1/16 counter 16 which is synchronized with the input signal. At other times, the reset pulse is not output. (In Fig. 7b, the count value of the first 1/16 frequency divider counter is 2, which is within the first verification range, so the reset pulse RST is not output.) The first 1/16 frequency division counter 14 adjusts the phase of the reproduced clock in the direction of reducing the phase difference by 1/16 clock by the normal DPLL operation.

The reproduction clock from the first 1/16 counter 14 is differentiated by the B clock in the initialization signal generator 25, becomes an initialization signal having a narrow pulse width indicating the phase of the reproduction clock, passes through the mask circuit 19b, and is transmitted at a low speed. It is supplied to the mold BTR as an initial phase reset signal.

Further, the phase comparison circuit 17 is arranged such that when the count value of the second 1/16 counter 16 is 0, the first 1/16 counter 14
When it is determined that the count value of is within the second verification range −2 to +1, the recovered clock is in phase synchronization with the input signal even if this phase difference is not 0, and the position is affected by the jitter of the input signal. When it is judged that the phase difference only occurs, the sync state signal SYN indicating the sync pull-in state is output. The synchronization protection circuit 18 has a synchronization protection stage number n from the outside in advance.
Is set, and this synchronization status signal SYN is
When input twice, a mask generation signal is output to the mask generation circuit 19a. The mask generation circuit generates an active "L" XBRS mask signal and outputs it to the mask circuit 19b when the mask generation signal is received or when the external high-speed BTR enable signal is inactive.
Even when the high speed BTR enable signal HSSTB is enabled, the mask circuit 19b stops the output of the initialization signal XBRS to the low speed BTR by this XBRS mask signal. As a result, the low-speed type B is stable against jitter etc. at an early point
Since the reproduction clock generation operation is taken over by TR, a stable reproduction clock can be obtained thereafter.

[0027]

As described above, according to the present invention, there is an effect that the synchronization pull-in can be performed at a high speed, and a stable recovered clock can be obtained against the fluctuation of the input signal such as the jitter after the pull-in.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a clock recovery circuit of a first invention.

FIG. 2 is a principle configuration diagram of a clock recovery circuit of the second and third inventions.

FIG. 3 is a configuration diagram of an embodiment of the present invention.

FIG. 4 is an operation time chart of FIG.

FIG. 5 is a block diagram of a clock recovery unit to which the present invention is applied.

FIG. 6 is a block diagram of a conventional clock recovery circuit.

7 is an operation time chart of FIG.

[Explanation of symbols]

1 ... Clock reproduction circuit (high-speed BTR), 11 ... Edge detection unit (edge detection circuit), 12 ... Clock generation unit, 12a
... clock generation circuit, 12b ... selector, 13 ... phase adjustment unit, 13a ... advance / delay determination circuit, 13b ... clock mask circuit, 14 ... first frequency division counter, 15 ... initialization signal generation unit (
Circuit), 16 ... second frequency division counter, 17 ... phase comparison part (circuit), 18 ... synchronization protection part (circuit), 19 ... mask part, 19a ...
Mask generator, 19b ... Mask circuit, 2 ... Low-speed BTR,
3 ... Delay detection circuit, 4 ... Phase adjusting means, 5 ... Reset means

Claims (3)

[Claims] 1. N frequency division counter means (1) for dividing a master clock to generate a reproduction clock having the same frequency as an input signal.
4), the lead / lag of the phase of the reproduced clock with respect to the input signal is judged, and based on the judgment result, 1 per reproduced clock cycle
/ N clock period, the phase adjusting means (4) for generating a master clock in which the pulse number is controlled so that the reproduction clock approaches the phase of the input signal, and a phase difference between the input signal and the reproduction clock is detected to detect the phase difference. When the phase difference exceeds a predetermined verification range, reset means for forcibly resetting the N frequency dividing counter (14) so that the phase of the reproduced clock is synchronized with the input signal in the next reproduced clock cycle.
(5) A clock recovery circuit comprising: 2. An edge detection unit for detecting a change point of an input signal.
(11), a clock generation unit (12) that switches the two-phase clock signals of φ phase and π phase at the detected change point and generates a master clock MCK having a high frequency portion after switching, and an input signal The phase of the reproduced clock is judged to be closer to the input signal by judging whether the phase is advanced or delayed with respect to the reproduced clock and whether or not one of the pulse trains of the master clock MCK immediately after switching is prohibited according to the judgment result. Phase adjustment unit
(13), a first frequency dividing counter (14) that divides the master clock MCK to generate a reproduction clock having the same frequency as the input signal, and is reset at the change point of the input signal, The second frequency division counter (16) for counting the master clock, and the first and second frequency division counters (14, 16) at the change point of the input signal.
16) Compare the count values, and if the difference between the two count values exceeds the first verification range, the first frequency division counter (1
4) A clock generation circuit having a phase comparator (17) which outputs a reset signal at the timing of the change point. 3. An initialization signal generation section (15) for generating an initialization signal XBRS at a timing corresponding to the phase of the reproduction clock from the count value of the first frequency division counter (14), , The count values of the second frequency division counter (14, 16) are compared, and if the difference between the two count values is within the second verification value range narrower than the first verification range, the synchronization status signal SYN is set to A phase comparison unit (17) for outputting, a synchronization protection unit (18) for outputting a mask signal MSK when it is detected that the synchronization status signal (17) has been output continuously for a predetermined number of protection stages n times, 3. The clock recovery circuit according to claim 2, further comprising a mask section (19) for stopping the output of the initialization signal XBRS by the mask signal MSK.