CN108011620A - Quick clock restoring circuit based on FPGA - Google Patents

Quick clock restoring circuit based on FPGA Download PDF

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Publication number
CN108011620A
CN108011620A CN201610931405.6A CN201610931405A CN108011620A CN 108011620 A CN108011620 A CN 108011620A CN 201610931405 A CN201610931405 A CN 201610931405A CN 108011620 A CN108011620 A CN 108011620A
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clock
clock signal
phase
input data
signal
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CN201610931405.6A
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CN108011620B (en
Inventor
楚存达
王玉章
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Shenzhen Yanxiang Smart Technology Co ltd
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EVOC Intelligent Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The present invention provides a kind of quick clock restoring circuit based on FPGA.The quick clock restoring circuit based on FPGA produces multiple reference clock signals identical from input data frequency, phase is different, determine the phase relation of input data and the feedback clock signal, and quantify input data and the feedback clock signal phase difference size, according to the selection output of the phase relation and phase difference size of input data and feedback clock signal all the way with the immediate reference clock signal of input data phase as recovered clock signal.It is synchronous with input data that the present invention can be rapidly completed clock signal, and clock recovery process produces less burr.

Description

Quick clock restoring circuit based on FPGA
Technical field
The present invention relates to clock recovery techniques field, more particularly to a kind of quick clock restoring circuit based on FPGA.
Background technology
With the continuous development of serial communication technology, the serial data amount in network constantly increases, but data are being transmitted During the shake of clock inevitably occurs, these are shaken has brought deviation to data transfer, it is therefore necessary to when carrying out The recovery of clock, is subsequently used in when resetting of data.With the continuous development of integrated circuit, FPGA (Field are utilized Programmable Gate Array, field programmable gate array) realize that clock recovery can be to avoid using extra hardware electricity Road, reduces circuit area, improves integrated level, while can also greatly shorten the design cycle, saves design cost.
In the implementation of the present invention, inventor has found at least to have the following technical problems in the prior art：
The existing clock recovery circuitry recovered clock signal based on FPGA needs ceaselessly to switch clock, makes final output All the way with the most similar clock of input data phase as recovered clock, therefore the clock recovery required time is longer, and because needing Repeatedly to switch the clock signal of output, clock signal is produced more burr.
The content of the invention
Quick clock restoring circuit provided by the invention based on FPGA, can be rapidly completed clock signal and input data Synchronization, and clock recovery process produces less burr.
The present invention provides a kind of quick clock restoring circuit based on FPGA, including：
Clock generation module, for producing multiple reference clock signals identical from input data frequency, phase is different；
Phase judgment module, for receiving input data and feedback clock signal, exports two reflection input datas With the high level signal of the feedback clock signal phase relation and phase difference size, by the width granularity of the high level signal After be converted into burst pulse, the burst pulse is counted, export count value C1, C2；
Clock adjusting module, for receiving count value C1, C2 of the phase judgment module output, according to the count value The magnitude relationship of C1, C2, one clock signal of selection output from the reference clock signal of clock generation module generation, and Export high level reset signal；
Reseting module, for receiving the clock adjusting module output after the clock adjusting module is completed once to adjust Reset high level, by it is described reset high level be converted into reset burst pulse, to count value C1, C2 of the phase judgment module Resetted.
Alternatively, the clock generation module includes：
System clock circuit, for receiving the clock signal of FPGA crystal oscillators generation, clock signal is used as management all the way for output The clock input of clock circuit, all the way clock input of the clock signal as the reseting module；
Clock circuit is managed, for receiving the clock signal of the system clock circuit output, exports clock signal all the way As the input of phase-locked loop circuit, the clock signal that clock signal is inputted as the phase judgment module all the way；
Phase-locked loop circuit, for receiving the clock signal of the management clock circuit output, exports multiple and input data The reference clock signal that frequency is identical, phase is different.
Alternatively, the phase difference of two reference clock signals of arbitrary neighborhood is identical in all reference clock signals, and institute There is phase difference in reference clock signal to be up to 360 °.
Alternatively, the phase judgment module includes：
Hogge linear phase detector circuits, for receiving the input data and the feedback clock signal, export two instead Answer the input data and the high level signal of the feedback clock signal phase relation and phase difference size；
Pulse-generating circuit, for receiving described two high level signals, by the width of the high level signal respectively into Row quantifies, and is converted into burst pulse；
Pulse-scaling circuit, the burst pulse for being produced to the pulse-generating circuit count, output count value C1, C2。
Alternatively, the phase judgment module further includes：Selector circuit, in first time to the phase judgment mould During block input clock signal, the clock signal of the management clock circuit output is selected, selects the clock adjusting module afterwards The feedback clock signal of output.
Alternatively, C1 is worked as<During C2, the phase of the reference clock signal is ahead of the phase of the input data；Work as C1> During C2, the phase of the reference clock signal lags behind the phase of the input data；As C1=C2, the input data with The phase of the reference clock signal is identical.
Alternatively, when the feedback clock signal is ahead of the input data, according to the size of the value of C2-C1, institute State clock adjusting module selects output one to lag behind institute from all reference clock signals that the clock generation module produces The reference clock signal of feedback clock signal is stated, which sentences as new feedback clock signal, and as phase The input of other module；
When the feedback clock signal lags behind the input data, according to the size of the value of C1-C2, the clock tune Mould preparation block selects output one when being ahead of the feedback from all reference clock signals that the clock generation module produces The reference clock signal of clock signal, the reference clock signal is as new feedback clock signal, and as phase judgment module Input, wherein, the size of C1 and C2 differences reflects the input data and the size of the feedback clock signal phase difference.
Quick clock restoring circuit provided in an embodiment of the present invention based on FPGA, produces multiple with input data frequency phase Reference clock signal same, phase is different, determines the phase relation of input data and the feedback clock signal, and quantify Input data and the feedback clock signal phase difference size, according to input data and the phase relation and phase of feedback clock signal The selection output of potential difference size is all the way with the immediate reference clock signal of input data phase as recovered clock signal.With it is existing Technology is compared, and the present invention can not only determine the phase relation of input data and the feedback clock signal, can also draw defeated Enter the phase difference size of data and the feedback clock signal, so as to fulfill the fast quick-recovery of clock signal, and clock recovery Process produces less burr.
Brief description of the drawings
Fig. 1 is the structure diagram of quick clock restoring circuit of the one embodiment of the invention based on FPGA；
Fig. 2 is the structure diagram of one embodiment of the invention Hogge linear phase detector circuits；
Fig. 3 is the structure diagram of one embodiment of the invention pulse-generating circuit；
Fig. 4 is the electrical block diagram of one embodiment of the invention reseting module.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only Only it is part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill Personnel's all other embodiments obtained without making creative work, belong to the scope of protection of the invention.
The present invention provides a kind of quick clock restoring circuit based on FPGA, as shown in Figure 1, including：
Clock generation module 101, for producing multiple reference clock letters identical from input data frequency, phase is different Number；
Phase judgment module 102, for receiving input data and feedback clock signal, exports two reflection input numbers According to the high level signal with the feedback clock signal phase relation and phase difference size, by the width extent of the high level signal Burst pulse is converted into after change, the burst pulse is counted, exports count value C1, C2；
Clock adjusting module 103, count value C1, C2 exported for receiving the phase judgment module 102, according to described The magnitude relationship of count value C1, C2, when selection exports one from the reference clock signal of the clock generation module 101 generation Clock signal, and export high level reset signal；
Reseting module 104, for receiving the clock adjustment mould after the clock adjusting module 103 is completed once to adjust The reset high level rst_0 that block 103 exports, the reset high level is converted into resetting burst pulse rst, to the phase judgment Count value C1, C2 of module 102 is resetted.
Quick clock restoring circuit provided in an embodiment of the present invention based on FPGA, produces multiple with input data frequency phase Reference clock signal same, phase is different, determines the phase relation of input data and the feedback clock signal, and quantify Input data and the feedback clock signal phase difference size, according to input data and the phase relation and phase of feedback clock signal The selection output of potential difference size is all the way with the immediate reference clock signal of input data phase as recovered clock signal.With it is existing Technology is compared, and the present invention can not only determine the phase relation of input data and the feedback clock signal, can also draw defeated Enter the phase difference size of data and the feedback clock signal, so as to fulfill the fast quick-recovery of clock signal, and clock recovery Process produces less burr.
Alternatively, the clock generation module 101 includes：
System clock circuit be used for receive FPGA crystal oscillators generation clock signal, output all the way clock signal as management when The clock input of clock circuit, all the way clock input of the clock signal as the reseting module 104；
Clock circuit is managed, for receiving the clock signal of the system clock circuit output, exports clock signal all the way As the input of phase-locked loop circuit, the clock signal that clock signal is inputted as the phase judgment module 102 all the way；
Phase-locked loop circuit, for receiving the clock signal of the management clock circuit output, exports multiple and input data The reference clock signal that frequency is identical, phase is different.
Alternatively, the phase-locked loop circuit includes the first phase-locked loop circuit and the second phase-locked loop circuit, for producing 6 respectively The reference clock signal that road is identical from input data frequency, phase is different.
Alternatively, the phase difference of two reference clock signals of arbitrary neighborhood is identical in all reference clock signals, and institute There is phase difference in reference clock signal to be up to 360 °.
Alternatively, the phase judgment module 102 includes：
Hogge linear phase detector circuits 301, for receiving the input data and the feedback clock signal, output two It is a to react the input data and the high level signal of the feedback clock signal phase relation and phase difference size；
Pulse-generating circuit 302, for receiving described two high level signals, the width of the high level signal is distinguished Quantified, be converted into burst pulse；
Pulse-scaling circuit 303, the burst pulse for being produced to the pulse-generating circuit count, and export count value C1、C2。
Alternatively, the phase judgment module 102 further includes：
Selector circuit 304, for when first time is to 102 input clock signal of phase judgment module, selecting institute State the clock signal of management clock circuit output, the feedback clock signal for selecting the clock adjusting module 103 to export afterwards.
Alternatively, the Hogge linear phase detector circuits 301 as shown in Fig. 2, receive input data datain and it is described when The feedback clock signal recclk that clock adjustment module 103 exports, exports two high level datacq and clkcq.
Alternatively, the width of the high level clkcq is constant all the time, and is exactly equal to half of feedback clock signal refclk Clock cycle；When feedback clock signal refclk phases are ahead of input data datain, the width of high level datacq will Less than the width of high level clkcq；When feedback clock signal refclk phases lag behind input data, datacq width will be big In the width of clkcq；When refclk rising edge clocks just align the centre of datain high level, then reach lock-out state, The width of high level datacq will be equal with the width of high level clkcq at this time.
So as to by comparing the width of two high level datacq and clkcq it may determine that going out input data datain With the phase relation of feedback clock signal refclk, and the different widths of two high level datacq and clkcq are bigger, show The phase of input data datain and feedback clock signal refclk difference are bigger.
Alternatively, the pulse-generating circuit 302 produces as shown in figure 3, in the case where input clock signal dclk is certain Raw burst pulse number is directly proportional to the length of high level shuru；In the case that high level shuru length is certain, input clock Signal dclk frequencies are higher, and pulse number caused by same high level is more, the clock signal phase precision recovered at this time It is higher.
Alternatively, the frequency of the input clock signal dclk is the limiting frequency that FPGA can bear.
Alternatively, C1 is worked as<During C2, the phase of the reference clock signal is ahead of the phase of the input data；Work as C1> During C2, the phase of the reference clock signal lags behind the phase of the input data；As C1=C2, the input data with The phase of the reference clock signal is identical.
Alternatively, when the feedback clock signal is ahead of the input data, according to the size of the value of C2-C1, institute State clock adjusting module 103 selects output one stagnant from all reference clock signals that the clock generation module 101 produces After the reference clock signal of the feedback clock signal, the reference clock signal is as new feedback clock signal, and conduct The input of phase judgment module 102；
When the feedback clock signal lags behind the input data, according to the size of the value of C1-C2, the clock tune It is described that mould preparation block 103 selects output one to be ahead of from all reference clock signals that the clock generation module 101 produces The reference clock signal of feedback clock signal, the reference clock signal are used as phase judgment as new feedback clock signal The input of module 102, wherein, the size of C1 and C2 differences reflects the input data and the feedback clock signal phase difference Size.
Alternatively, may shadow since the reset high level rst_0 width of the clock adjusting module 103 output is larger The counting of next round is rung, therefore reseting module 104 will reset high level rst_0 and be converted into resetting burst pulse rst, and count value is carried out Reset.
Alternatively, the circuit structure of the reseting module 104 by high level rst_0 is resetted as shown in figure 4, be converted into resetting The input clock signal of burst pulse rst is dclk；The frequency of wherein described input clock signal dclk can bear for FPGA Limiting frequency.
The above description is merely a specific embodiment, but protection scope of the present invention is not limited thereto, any Those familiar with the art the invention discloses technical scope in, the change or replacement that can readily occur in, all should It is included within the scope of the present invention.Therefore, protection scope of the present invention should be subject to scope of the claims.

Claims (7)

  1. A kind of 1. quick clock restoring circuit based on FPGA, it is characterised in that including：
    Clock generation module, for producing multiple reference clock signals identical from input data frequency, phase is different；
    Phase judgment module, for receiving input data and feedback clock signal, exports two reflections input data and institute The high level signal of feedback clock signal phase relation and phase difference size is stated, will be turned after the width granularity of the high level signal Change burst pulse into, the burst pulse is counted, export count value C1, C2；
    Clock adjusting module, for receiving count value C1, C2 of phase judgment module output, according to the count value C1, The magnitude relationship of C2, one clock signal of selection output from the reference clock signal of clock generation module generation, and it is defeated Go out high level reset signal；
    Reseting module, for receiving answering for the clock adjusting module output after the clock adjusting module is completed once to adjust Position high level, the reset high level is converted into resetting burst pulse, count value C1, C2 of the phase judgment module is carried out Reset.
  2. 2. the quick clock restoring circuit according to claim 1 based on FPGA, it is characterised in that the clock produces mould Block includes：
    System clock circuit, for receiving the clock signal of FPGA crystal oscillators generation, clock signal is used as management clock all the way for output The clock input of circuit, all the way clock input of the clock signal as the reseting module；
    Clock circuit is managed, for receiving the clock signal of the system clock circuit output, exports clock signal conduct all the way The input of phase-locked loop circuit, the clock signal that clock signal is inputted as the phase judgment module all the way；
    Phase-locked loop circuit, for receiving the clock signal of the management clock circuit output, exports multiple and input data frequency Reference clock signal identical, phase is different.
  3. 3. the quick clock restoring circuit according to claim 2 based on FPGA, it is characterised in that all reference clock letters The phase difference of two reference clock signals of arbitrary neighborhood is identical in number, and phase difference is up in all reference clock signals 360°。
  4. 4. the quick clock restoring circuit according to claim 1 based on FPGA, it is characterised in that the phase judgment mould Block includes：
    Hogge linear phase detector circuits, for receiving the input data and the feedback clock signal, export two reaction institutes State input data and the high level signal of the feedback clock signal phase relation and phase difference size；
    Pulse-generating circuit, for receiving described two high level signals, by the width of the high level signal amount of progress respectively Change, be converted into burst pulse；
    Pulse-scaling circuit, the burst pulse for being produced to the pulse-generating circuit count, and export count value C1, C2.
  5. 5. the quick clock restoring circuit according to claim 4 based on FPGA, it is characterised in that the phase judgment mould Block further includes：
    Selector circuit, for when first time is to the phase judgment module input clock signal, selecting the management clock The clock signal of circuit output, selects the feedback clock signal of the clock adjusting module output afterwards.
  6. 6. the quick clock restoring circuit according to claim 4 based on FPGA, it is characterised in that work as C1<It is described during C2 The phase of reference clock signal is ahead of the phase of the input data；Work as C1>During C2, the phase steric retardation of the reference clock signal After the phase of the input data；As C1=C2, the input data is identical with the phase of the reference clock signal.
  7. 7. the quick clock restoring circuit according to claim 6 based on FPGA, it is characterised in that when the feedback clock When signal is ahead of the input data, according to the size of the value of C2-C1, the clock adjusting module produces mould from the clock One reference clock signal for lagging behind the feedback clock signal of selection output in all reference clock signals that block produces, should Reference clock signal is as new feedback clock signal, and as the input of phase judgment module；
    When the feedback clock signal lags behind the input data, according to the size of the value of C1-C2, the clock adjusts mould Block selects output one to be ahead of the feedback clock letter from all reference clock signals that the clock generation module produces Number reference clock signal, the reference clock signal is as new feedback clock signal, and as the input of phase judgment module, Wherein, the size of C1 and C2 differences reflects the input data and the size of the feedback clock signal phase difference.
CN201610931405.6A 2016-10-31 2016-10-31 Fast clock recovery circuit based on FPGA Active CN108011620B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021102927A1 (en) * 2019-11-29 2021-06-03 华为技术有限公司 Clock generation circuit

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972161A (en) * 1989-06-28 1990-11-20 Digital Equipment Corporation Clock recovery for serial data communications system
JPH06296184A (en) * 1993-04-08 1994-10-21 Fujitsu Ltd Clock regenerating circuit
WO1996021296A1 (en) * 1994-12-29 1996-07-11 Alcatel Standard Electrica S.A. Data recovery circuit
US6301318B1 (en) * 1998-03-30 2001-10-09 Pmc-Sierra Ltd. Pipelined phase detector for clock recovery
US20020030519A1 (en) * 2000-07-19 2002-03-14 Rejean Beaulieu Phase locked loop having DC bias circuitry
CN1808963A (en) * 2005-01-21 2006-07-26 阿尔特拉公司 Method and apparatus for multi-mode clock data recovery
CN1812268A (en) * 2005-01-28 2006-08-02 瑞昱半导体股份有限公司 Clock generating circuit and related data restoring circuit
CN101789784A (en) * 2009-12-15 2010-07-28 北京时代民芯科技有限公司 Configurable phase discriminator for time-delay locking ring
US9036764B1 (en) * 2012-12-07 2015-05-19 Rambus Inc. Clock recovery circuit

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972161A (en) * 1989-06-28 1990-11-20 Digital Equipment Corporation Clock recovery for serial data communications system
JPH06296184A (en) * 1993-04-08 1994-10-21 Fujitsu Ltd Clock regenerating circuit
WO1996021296A1 (en) * 1994-12-29 1996-07-11 Alcatel Standard Electrica S.A. Data recovery circuit
US6301318B1 (en) * 1998-03-30 2001-10-09 Pmc-Sierra Ltd. Pipelined phase detector for clock recovery
US20020030519A1 (en) * 2000-07-19 2002-03-14 Rejean Beaulieu Phase locked loop having DC bias circuitry
CN1808963A (en) * 2005-01-21 2006-07-26 阿尔特拉公司 Method and apparatus for multi-mode clock data recovery
CN1812268A (en) * 2005-01-28 2006-08-02 瑞昱半导体股份有限公司 Clock generating circuit and related data restoring circuit
CN101789784A (en) * 2009-12-15 2010-07-28 北京时代民芯科技有限公司 Configurable phase discriminator for time-delay locking ring
US9036764B1 (en) * 2012-12-07 2015-05-19 Rambus Inc. Clock recovery circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
杨宗雄: "2.5Gbps时钟数据恢复电路的设计", 《中国优秀硕士学位论文全文数据库》 *
杨宗雄: "2.5Gbps时钟数据恢复电路的设计", 《中国优秀硕士学位论文全文数据库》, 15 January 2013 (2013-01-15), pages 1 - 77 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021102927A1 (en) * 2019-11-29 2021-06-03 华为技术有限公司 Clock generation circuit

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