CN106341127B - A kind of method and apparatus that video clock restores - Google Patents
A kind of method and apparatus that video clock restores Download PDFInfo
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- CN106341127B CN106341127B CN201610822836.9A CN201610822836A CN106341127B CN 106341127 B CN106341127 B CN 106341127B CN 201610822836 A CN201610822836 A CN 201610822836A CN 106341127 B CN106341127 B CN 106341127B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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Abstract
The method and apparatus that video clock disclosed in the present application restores, the theoretic frequency of pixel clock to be restored is first calculated according to the video data in link data, thus the configuration parameter of phaselocked loop intermediate ring road frequency divider is calculated, and loop divider is configured, further according to the read-write state of doubleclocking first in, first out module, the configuration parameter of loop divider is adjusted, so that the clock of the corresponding phaselocked loop output of configuration parameter adjusted meets the requirement that doubleclocking first in, first out module is in dynamic balance state.Due to during video clock restores, the value of loop divider is only related with the theoretic frequency for the pixel clock to be restored being calculated, and the value of prescalar can be configured by any way, be not need to rely on the relevant information of transmitting terminal transmission, such as the numerical value of Mvid/Nvid.Therefore, receiving end can be compatible with all transmitting terminals, improve the compatibility of receiving end using after video clock recovery scheme disclosed in the present application.
Description
Technical field
This application involves signal transmission technology field, a kind of method restored more specifically to video clock and dress
It sets.
Background technique
In some high speed signal interface agreements such as DP, MHL V3.1&V3.2 and MIPI agreement, video data is packetized in
It is transmitted in link data by link with certain link rate, and in link does not include the pixel clock of original video, be
The quality for guaranteeing video signal playback, does not occur any loss of data and mistake, it is necessary to regenerate this picture in receiving end
Plain clock, the process for generating this pixel clock is video clock recovery process.
The related letter that the video clock for being required to send dependent on transmitting terminal in existing video clock recovery scheme restores
Breath, such as the Mvid/Nvid in DP agreement.The numerical value for relying on Mvid/Nvid, configures the prescalar and loop divide of phaselocked loop
The value of device.The video clock that the relevant information accuracy and stability that transmitting terminal is sent can all influence receiving end restores.And city
The relevant information that different transmitting terminals is sent on field has different precision and stability, so that the same receiving end is likely to
It can not or be difficult to be compatible with all transmitting terminals simultaneously.Also, there is no video in MHL V3.1&V3.2 and MIPI agreement transmission process
The relevant information of clock recovery leads to these incompatible agreements of existing video clock recovery scheme.Therefore, transmitting terminal is depended on
The video clock recovery scheme of the relevant information of transmission, reduces the compatibility of receiving end.
Summary of the invention
In view of this, the application proposes a kind of method and apparatus that video clock restores, it is intended to realize independent of transmitting terminal
The relevant information of transmission improves the purpose of the compatibility of receiving end.
To achieve the goals above, it is proposed that scheme it is as follows:
A kind of method that video clock restores, comprising:
Receive the link data that transmitting terminal is sent；
The theoretic frequency of pixel clock to be restored is calculated according to video data in the link data；
The configuration parameter of the loop divider of phaselocked loop is calculated according to the theoretic frequency of the pixel clock to be restored, with
Make the clock of the theoretic frequency of the phase-lock-ring output frequency pixel clock to be restored；
The loop divider is configured according to the configuration parameter；
Adjust the configuration parameter of the loop divider so that adjustment after loop divider the corresponding locking phase of configuration parameter
The clock of ring output meets the speed of the video data write-in doubleclocking first in, first out module and first enters elder generation from the doubleclocking
Module reads out the equal requirement of speed of the video data out.
Preferably, the theoretic frequency that pixel clock to be restored is calculated according to video data in the link data,
Include:
The periodicity of horizontal blanking signal is counted within a preset time, obtains the frequency of horizontal blanking signal；
The horizontal blanking signal frequency is multiplied with the pixel number that line synchronising signal includes, obtains the picture to be restored
The theoretic frequency of plain clock.
Preferably, the loop divider that phaselocked loop is calculated according to the theoretic frequency of the pixel clock to be restored
Configuration parameter, comprising:
By the theoretic frequency of pixel clock to be restored multiplied by the clock frequency and phaselocked loop of the voltage controlled oscillator of phaselocked loop
Multiple parameter between the frequency of the clock of output, and divided by the reference clock frequency of phaselocked loop, obtain matching for loop divider
Set parameter.
Preferably, the configuration parameter of the adjustment loop divider, comprising:
Compare the speed of video data write-in doubleclocking first in, first out module with from the doubleclocking first in, first out mould
Block reads out the size of the speed of the video data；
If the speed of the video data write-in doubleclocking first in, first out module is greater than from the doubleclocking first in, first out mould
Block reads out the speed of the video data, then increases the configuration parameter of the loop divider to improve the phaselocked loop output
Clock frequency；
If the speed of the video data write-in doubleclocking first in, first out module is less than from the doubleclocking first in, first out mould
Block reads out the speed of the video data, then reduces the configuration parameter of the loop divider to reduce the phaselocked loop output
Clock frequency.
A kind of device that video clock restores, comprising:
Receiving module, for receiving the link data of transmitting terminal transmission；
First computing module, for calculating the theory of pixel clock to be restored according to video data in the link data
Frequency；
Second computing module, for calculating the loop point of phaselocked loop according to the theoretic frequency of the pixel clock to be restored
The configuration parameter of frequency device, so that phase-lock-ring output frequency is the clock of the theoretic frequency of the pixel clock to be restored；
First frequency module, for being configured according to the configuration parameter to the loop divider；
Frequency regulation block, for adjusting the configuration parameter of the loop divider, so that loop divider after adjustment
The clock of configuration parameter corresponding phaselocked loop output meet the speed of the video data write-in doubleclocking first in, first out module with
The equal requirement of the speed for reading out the video data from the doubleclocking first in, first out module.
Preferably, first computing module, comprising:
First frequency unit obtains horizontal blanking for counting within a preset time to the periodicity of horizontal blanking signal
The frequency of signal；
First computing unit, for the horizontal blanking signal frequency to be multiplied with the pixel number that line synchronising signal includes,
Obtain the theoretic frequency of the pixel clock to be restored.
Preferably, second computing module includes:
Second computing unit, for the voltage controlled oscillator by the theoretic frequency of pixel clock to be restored multiplied by phaselocked loop
Multiple parameter between clock frequency and the frequency of the clock of phaselocked loop output, and divided by the reference clock frequency of phaselocked loop, it obtains
To the configuration parameter of loop divider.
Preferably, the frequency regulation block, comprising:
Judging unit, for the video data write-in doubleclocking first in, first out module speed with from it is described double when
Clock first in, first out module reads out the size of the speed of the video data；
The first adjustment unit, if the speed for video data write-in doubleclocking first in, first out module is greater than from described
Doubleclocking first in, first out module reads out the speed of the video data, then increases the configuration parameter of the loop divider to mention
The frequency of the clock of the high phaselocked loop output；
Second adjustment unit, if the speed for video data write-in doubleclocking first in, first out module is less than from described
Doubleclocking first in, first out module reads out the speed of the video data, then reduces the configuration parameter of the loop divider to drop
The frequency of the clock of the low phaselocked loop output.
It can be seen from the above technical scheme that the method and apparatus that video clock disclosed in the present application restores, first basis
Video data in link data calculates the theoretic frequency of pixel clock to be restored, calculates phaselocked loop intermediate ring road frequency dividing as a result,
The configuration parameter of device, and to loop divider configured to obtain the theoretic frequency that frequency is pixel clock to be restored when
Clock is adjusted the configuration parameter of loop divider further according to the read-write state of doubleclocking first in, first out module, so that adjustment
It is flat in dynamic to meet doubleclocking first in, first out module for the clock of the corresponding phaselocked loop output of the configuration parameter of loop divider afterwards
The requirement of weighing apparatus state, i.e. writing speed are equal to reading speed.And when doubleclocking first in, first out module is in read-write equilibrium state,
The clock of phaselocked loop output is the pixel clock after restoring, and is read out by this pixel clock from doubleclocking first in, first out module
Video data realizes the Distortionless of video data.
Due to during video clock restores, the value of loop divider only with the pixel to be restored that is calculated
The theoretic frequency of clock is related, and the value of prescalar can be configured by any way, be not need to rely on transmitting terminal
The video clock of transmission restores the relevant information needed, such as the numerical value of Mvid/Nvid.Therefore, receiving end is public using the application
After the video clock recovery scheme opened, do not influenced by the relevant information accuracy and stability that transmitting terminal is sent, it is possible to
The compatible relevant information sent has the transmitting terminal of different precision and stability, and the transmission not comprising relevant information
End, allows same receiving end to be compatible with all transmitting terminals, improves the compatibility of receiving end.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of flow chart for the method that video clock restores disclosed in the present embodiment；
Fig. 2 is the flow chart for the method that another kind video clock disclosed in the present embodiment restores；
Fig. 3 is the flow chart for the method that another kind video clock disclosed in the present embodiment restores；
Fig. 4 is a kind of schematic diagram for the device that video clock restores disclosed in the present embodiment；
Fig. 5 is the schematic diagram of the first computing module disclosed in the present embodiment；
Fig. 6 is the schematic diagram of frequency regulation block disclosed in the present embodiment.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
Now to this application involves noun explain, in order to the understanding to application scheme:
Phaselocked loop (Phase Locked Loop): phaselocked loop is the feedback system that output phase is compared with input phase
System, most basic function first is that clock frequency double frequency function.Its basic structure is by phase discriminator (PD, Phase Detector)
Or phase frequency detector (PFD, Phase Frequency Detector), loop filter (LF, Loop Filter), voltage-controlled vibration
It swings device (VCO, Voltage Controlled Oscillator) and loop divider (Loop Divider) is constituted.
Delta-Sigma decimal frequency-multiplication phase-locked loop (Delta Sigma Fractional N PLL): in basic phaselocked loop
Loop divider (Loop Divider) is changed to by program divider (Programmable Divider) on the basis of structure
It realizes, and is controlled by digital Delta-Sigma controller, the final phaselocked loop for realizing mixed decimal frequency multiplication.
VCO: the oscillator of output frequency can be changed by changing input voltage in voltage controlled oscillator.
Doubleclocking first in, first out module (Double Clock First In First Out, FIFO): write clock and reading
Take clock can be with different First Input First Output.
The present embodiment discloses a kind of method that video clock restores, shown in Figure 1, this method comprises:
Step S11: the link data that transmitting terminal is sent is received；
The link data that transmitting terminal is sent is serial link data, therefore, carries out clock and data recovery and by serial number
According to being converted into parallel clock and data.
Step S12: the theoretic frequency of pixel clock to be restored is calculated according to video data in link data；
The pixel number that video data in link data includes horizontal blanking signal and line synchronising signal includes.Row disappears
The product for the pixel number that the frequency and line synchronising signal of hidden signal include is the theoretic frequency of pixel clock to be restored.It needs
To illustrate that the pixel number that the frequency and line synchronising signal of horizontal blanking signal include is determined by transmitting terminal, and receiving end
Line synchronising signal be according to receiving end restore pixel clock it is self-built.
Step S13: according to the theoretic frequency for the pixel clock to be restored being calculated, the loop divide of phaselocked loop is calculated
The configuration parameter of device, so that phase-lock-ring output frequency is the clock of the theoretic frequency of pixel clock to be restored；
The configuration parameter of the loop divider of the frequency and phaselocked loop of the clock of phaselocked loop output is in a linear relationship, control ring
The configuration parameter of road frequency divider can determine the frequency of the clock of phaselocked loop output.Obtaining the reason of pixel clock to be restored
After frequency, when calculating the clock for the theoretic frequency that phase-lock-ring output frequency is pixel clock to be restored, loop divider pair
The configuration parameter answered, the i.e. value of loop divider.And the value of prescalar can be configured by any way, such as directly
Configure the numerical value of any fixation.
Step S14: loop divider is configured according to the loop divider configuration parameter being calculated；
Step S15: the configuration parameter of adjustment loop frequency divider, so that the configuration parameter of loop divider is corresponding after adjustment
The clock of phaselocked loop output meets the speed and video data write-in pair that video data is read out from doubleclocking first in, first out module
The equal requirement of the speed of clock first in, first out module.
Doubleclocking first in, first out module is written by link clock in video data, video data write-in doubleclocking first enters elder generation
The speed of module out, the frequency direct proportionality with link clock；And first entered by the clock that phaselocked loop exports from doubleclocking
First go out module and read out video data, the speed of video data is read out from doubleclocking first in, first out module, it is defeated with phaselocked loop
The frequency direct proportionality of clock out.According to matching for the read-write state adjustment loop frequency divider of doubleclocking first in, first out module
Parameter is set, and then realizes the adjustment of the frequency of the clock exported to phaselocked loop, the i.e. adjustment to the frequency of pixel clock.Doubleclocking
The effect of first in, first out module is to guarantee that data will not malfunction in cross clock domain conversion process.In doubleclocking first in, first out
When module is in read-write equilibrium state, the data in conversion process would not malfunction.And it is in doubleclocking first in, first out module
When reading and writing equilibrium state, the clock of phaselocked loop output, the as pixel clock after recovery are first from doubleclocking by this pixel clock
Enter first to go out module and read out video data, realizes the Distortionless of video data.
Video clock restoration methods disclosed in the present application, the value of loop divider only with the picture to be restored that is calculated
The theoretic frequency of plain clock is related, and the value of prescalar can be configured by any way, is not need to rely on transmitting terminal
The video clock of transmission restores the relevant information needed, such as the numerical value of Mvid/Nvid.Therefore, receiving end is public using the application
After the video clock restoration methods opened, do not influenced by the relevant information accuracy and stability that transmitting terminal is sent, it is possible to
The compatible relevant information sent has the transmitting terminal of different precision and stability, and the transmission not comprising relevant information
End, allows same receiving end to be compatible with all transmitting terminals, improves the compatibility of receiving end.
The present embodiment discloses the method that another video clock restores, shown in Figure 2, wherein step S21, S24,
S25, S26 are consistent with step S11, S13, S14, S15 respectively, and details are not described herein.Step S22 and step S23 is step S12's
Refinement, specific as described below:
Step S22: within a preset time counting the periodicity of horizontal blanking signal, calculates the frequency of horizontal blanking signal
Rate；
Utilize the system clock or other clocks that receiving end frequency is fixed, timing regular hour T, in the preset time T
The interior periodicity by horizontal blanking signal (Hblank) carries out counting C, obtains the frequency f of horizontal blanking signal (Hblank)Hblank
=C/T.
Step S23: the horizontal blanking signal frequency f that will be calculatedHblankThe pixel number H for including with line synchronising signaltotal
It is multiplied, obtains the theoretic frequency f of pixel clock to be restoredpixel=fHblank*Htotal。
It calculates the video clock that the clock utilized in the frequency procedure of horizontal blanking signal and transmitting terminal are sent and restores needs
Relevant information (Mvid/Nvid) is unrelated, this ensure that the recovery process of receiving end video clock needs not rely on transmitting terminal hair
Video clock is sent to restore the relevant information (Mvid/Nvid) needed.Therefore, receiving end is extensive using video clock disclosed in the present application
After compound method, all transmitting terminals can be compatible with, improve the compatibility of receiving end.
The present embodiment discloses the method that another video clock restores, shown in Figure 3, wherein step S31, S32,
S34, S35 are consistent with step S11, S12, S14, S15 respectively, and details are not described herein.Step S33 is the refinement of step S13, specifically
It is as described below:
Step S33: by the theoretic frequency f of pixel clock to be restoredpixelWith the clock frequency and locking phase of VCO in phaselocked loop
Multiple parameter N between the frequency of the clock of ring output is multiplied, and by multiplied result divided by the reference clock frequency f of phaselocked loopr,
Obtain the configuration parameter q of loop divider.
Wherein, the theoretic frequency f of pixel clock to be restoredpixelIt is obtained for step S12, the clock of VCO in phaselocked loop
Frequency fvcoWith the frequency f of the clock of phaselocked loop outputpixelBetween multiple parameter N determined by frequency dividing circuit in phaselocked loop, N=
fvco/fpixel, reference clock frequency frIt is determined by the reference clock that phaselocked loop is arranged.Therefore, after the circuit of phaselocked loop determines,
Only need to be calculated the theoretic frequency f of pixel clock to be restoredpixel, the configuration parameter q of loop divider can be calculated
=fHblank*Htotal*N/fr.The value of loop divider match and is postponed, the clock of phaselocked loop output, as theoretic frequency
fpixelPixel clock.
Specifically, the reference clock of phaselocked loop is set as crystal oscillator clock.Relative to using link clock as reference clock, incite somebody to action
The reference clock that crystal oscillator clock is set as phaselocked loop has better clock performance, and the jitter performance of transmitting terminal will not influence to extensive
Multiple pixel clock.Also, when selecting the biggish crystal oscillator clock of frequency, as select the crystal oscillator clock of 27MHz as phaselocked loop
When reference clock, the loop bandwidth of phaselocked loop can choose 1MHz or so, i.e., higher bandwidth, not only accelerate phaselocked loop tracking
Speed, simultaneously as the value of Mvid/Nvid is not utilized, so also not needing the prescalar and loop point of larger area
Frequency device, therefore the area of phaselocked loop is substantially reduced, and then can be easy to integrate in the chip, reduce production cost.
Specifically, the configuration parameter process of adjustment loop frequency divider, comprising: compare video data write-in doubleclocking and first enter elder generation
The size of the speed of module and the speed that video data is read out from doubleclocking first in, first out module out, if video data write-in is double
The speed of clock first in, first out module is greater than the speed that video data is read out from doubleclocking first in, first out module, then increases loop
The configuration parameter of frequency divider with improve phaselocked loop output clock frequency, if video data be written doubleclocking first in, first out module
Speed be less than and read out the speed of video data from doubleclocking first in, first out module, then reduce the configuration parameter of loop divider
To reduce the frequency of the clock of phaselocked loop output.The corresponding phaselocked loop output of the configuration parameter of loop divider after adjustment
Clock makes the speed of video data write-in doubleclocking first in, first out module and reads out video from doubleclocking first in, first out module
Until the speed of data is equal.
It should also be noted that, for the various method embodiments described above, for simple description, therefore, it is stated as a systems
The combination of actions of column, but those skilled in the art should understand that, the application is not limited by the described action sequence, because
For according to the application, some steps may be performed in other sequences or simultaneously.
The present embodiment discloses a kind of device that video clock restores, shown in Figure 4, comprising:
Receiving module 101, for receiving the link data of transmitting terminal transmission；
First computing module 102, for calculating the theory of pixel clock to be restored according to video data in link data
Frequency；
Second computing module 103, for calculating the loop point of phaselocked loop according to the theoretic frequency of pixel clock to be restored
The configuration parameter of frequency device, so that phase-lock-ring output frequency is the clock of the theoretic frequency of pixel clock to be restored；
First frequency module 104, for being configured according to the configuration parameter being calculated to loop divider, and then
To the clock for the theoretic frequency that frequency is pixel clock to be restored；
Frequency regulation block 105, for the configuration parameter of adjustment loop frequency divider, so that loop divider is matched after adjustment
Set parameter corresponding phaselocked loop output clock meet the speed of video data write-in doubleclocking first in, first out module with from it is double when
Clock first in, first out module reads out the equal requirement of speed of video data.
The first computing module 102, shown in Figure 5 disclosed in the present embodiment, comprising:
First frequency unit 1021 is gone for counting within a preset time to the periodicity of horizontal blanking signal
The frequency of blanking signal；
First computing unit 1022, for horizontal blanking signal frequency to be multiplied with the pixel number that line synchronising signal includes,
Obtain the theoretic frequency of pixel clock to be restored.
Second computing module 103 disclosed in the present embodiment, comprising:
Second computing unit, for the voltage controlled oscillator by the theoretic frequency of pixel clock to be restored multiplied by phaselocked loop
Multiple parameter between clock frequency and the frequency of the clock of phaselocked loop output, and divided by the reference clock frequency of phaselocked loop, it obtains
To the configuration parameter of loop divider.
Frequency regulation block 105 disclosed in the present embodiment, it is shown in Figure 6, comprising:
Judging unit 1051, for compare video data write-in doubleclocking first in, first out module speed with from doubleclocking elder generation
Enter first to go out the size that module reads out the speed of video data；
The first adjustment unit 1052, if for video data write-in doubleclocking first in, first out module speed be greater than from it is double when
Clock first in, first out module reads out the speed of video data, then increases the configuration parameter of loop divider to improve phaselocked loop output
Clock frequency；
Second adjustment unit 1053, if for video data write-in doubleclocking first in, first out module speed be less than from it is double when
Clock first in, first out module reads out the speed of the video data, then reduces the configuration parameter of loop divider to reduce phaselocked loop
The frequency of the clock of output.
For device embodiment, since it essentially corresponds to embodiment of the method, so related place is referring to method reality
Apply the part explanation of example.The apparatus embodiments described above are merely exemplary, wherein described be used as separation unit
The unit of explanation may or may not be physically separated, and component shown as a unit can be or can also be with
It is not physical unit.Some or all of the modules therein can be selected to realize this embodiment scheme according to the actual needs
Purpose.Those of ordinary skill in the art can understand and implement without creative efforts.
Herein, relational terms such as first and second and the like be used merely to by an entity or operation with it is another
One entity or operation distinguish, and without necessarily requiring or implying between these entities or operation, there are any this reality
Relationship or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to the packet of nonexcludability
Contain, so that the process, method, article or equipment for including a series of elements not only includes those elements, but also including
Other elements that are not explicitly listed, or further include for elements inherent to such a process, method, article, or device.
In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including the element
Process, method, article or equipment in there is also other identical elements.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of method that video clock restores characterized by comprising
Receive the link data that transmitting terminal is sent；
The theoretic frequency of pixel clock to be restored is calculated according to video data in the link data；
The configuration parameter of the loop divider of phaselocked loop is calculated according to the theoretic frequency of the pixel clock to be restored, so that lock
Phase ring output frequency is the clock of the theoretic frequency of the pixel clock to be restored, and the reference clock of the phaselocked loop is crystal oscillator
Clock；
The loop divider is configured according to the configuration parameter；
The configuration parameter of the loop divider is adjusted, so that the corresponding phaselocked loop of configuration parameter of loop divider is defeated after adjustment
Clock out meet the speed of video data write-in doubleclocking first in, first out module with from the doubleclocking first in, first out mould
Block reads out the equal requirement of speed of the video data.
2. the method according to claim 1, wherein it is described according in the link data video data calculate to
The theoretic frequency of the pixel clock of recovery, comprising:
The periodicity of horizontal blanking signal is counted within a preset time, obtains the frequency of horizontal blanking signal；
The horizontal blanking signal frequency is multiplied with the pixel number that line synchronising signal includes, when obtaining the pixel to be restored
The theoretic frequency of clock.
3. the method according to claim 1, wherein the theoretical frequency according to the pixel clock to be restored
Rate calculates the configuration parameter of the loop divider of phaselocked loop, comprising:
The theoretic frequency of pixel clock to be restored is exported multiplied by the clock frequency and phaselocked loop of the voltage controlled oscillator of phaselocked loop
Clock frequency between multiple parameter obtain the configuration ginseng of loop divider and divided by the reference clock frequency of phaselocked loop
Number.
4. the method according to claim 1, wherein the configuration parameter of the adjustment loop divider, packet
It includes:
The speed for comparing the video data write-in doubleclocking first in, first out module is read with from the doubleclocking first in, first out module
Take out the size of the speed of the video data；
It is read if the speed of the video data write-in doubleclocking first in, first out module is greater than from the doubleclocking first in, first out module
Take out the speed of the video data, then increase the configuration parameter of the loop divider with improve phaselocked loop output when
The frequency of clock；
It is read if the speed of the video data write-in doubleclocking first in, first out module is less than from the doubleclocking first in, first out module
Take out the speed of the video data, then reduce the configuration parameter of the loop divider with reduce phaselocked loop output when
The frequency of clock.
5. the device that a kind of video clock restores characterized by comprising
Receiving module, for receiving the link data of transmitting terminal transmission；
First computing module, for calculating the theoretical frequency of pixel clock to be restored according to video data in the link data
Rate；
Second computing module, for calculating the loop divider of phaselocked loop according to the theoretic frequency of the pixel clock to be restored
Configuration parameter so that phase-lock-ring output frequency be the pixel clock to be restored theoretic frequency clock, the locking phase
The reference clock of ring is crystal oscillator clock；
First frequency module, for being configured according to the configuration parameter to the loop divider；
Frequency regulation block, for adjusting the configuration parameter of the loop divider so that adjustment after loop divider configuration
The clock of parameter corresponding phaselocked loop output meet the speed of the video data write-in doubleclocking first in, first out module with from institute
State the equal requirement of speed that doubleclocking first in, first out module reads out the video data.
6. device according to claim 5, which is characterized in that first computing module, comprising:
First frequency unit obtains horizontal blanking signal for counting within a preset time to the periodicity of horizontal blanking signal
Frequency；
First computing unit is obtained for the horizontal blanking signal frequency to be multiplied with the pixel number that line synchronising signal includes
The theoretic frequency of the pixel clock to be restored.
7. device according to claim 5, which is characterized in that second computing module includes:
Second computing unit, for the clock by the theoretic frequency of pixel clock to be restored multiplied by the voltage controlled oscillator of phaselocked loop
Multiple parameter between frequency and the frequency of the clock of phaselocked loop output, and divided by the reference clock frequency of phaselocked loop, obtain ring
The configuration parameter of road frequency divider.
8. device according to claim 5, which is characterized in that the frequency regulation block, comprising:
Judging unit, for video data write-in doubleclocking first in, first out module speed with it is first from the doubleclocking
Enter first to go out the size that module reads out the speed of the video data；
The first adjustment unit, if for the video data write-in doubleclocking first in, first out module speed be greater than from it is described double when
Clock first in, first out module reads out the speed of the video data, then increases the configuration parameter of the loop divider to improve
State the frequency of the clock of phaselocked loop output；
Second adjustment unit, if for the video data write-in doubleclocking first in, first out module speed be less than from it is described double when
Clock first in, first out module reads out the speed of the video data, then reduces the configuration parameter of the loop divider to reduce
State the frequency of the clock of phaselocked loop output.
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| CN111669635B (en) * | 2020-06-15 | 2022-04-29 | 武汉精立电子技术有限公司 | Clock transmission and recovery method and device based on video interface |
| CN112486447B (en) * | 2020-12-01 | 2022-06-07 | 佛吉亚歌乐电子(丰城)有限公司 | DPI clock configuration method, system, terminal and computer storage medium |
| CN115883493B (en) * | 2022-10-31 | 2024-07-09 | 中国船舶集团有限公司第七二三研究所 | Asynchronous data time sequence recovery method based on dynamic adjustment |
| CN115426438B (en) * | 2022-11-03 | 2023-01-10 | 基石酷联微电子技术（北京）有限公司 | DP video signal time sequence recovery device and working method thereof |
| CN116318516B (en) * | 2023-05-25 | 2023-08-15 | 芯动微电子科技(珠海)有限公司 | DP protocol-based dynamic accurate realization method and device for regenerated stream clock |
| CN117349219A (en) * | 2023-11-02 | 2024-01-05 | 硅谷数模(上海)半导体有限公司 | Timing adjustment method, apparatus, computer-readable storage medium, and electronic device |
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| CN102223198B (en) * | 2011-06-17 | 2016-12-21 | 中兴通讯股份有限公司 | One realizes clock recovery method and device |
| US9014313B2 (en) * | 2012-02-07 | 2015-04-21 | Lsi Corporation | Error signature analysis for data and clock recovery in a communication system |
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