KR101526025B1 - Frequency synchronization - Google Patents

Abstract

To synchronizing the frequency between a local signal from a local oscillator and a reference clock signal from a remote oscillator. The reference counter increments its counter for every pulse in the reference clock signal. The value of the reference counter is compared to a configurable reference value. Every time a match occurs between the reference counter value and the reference value, a hit signal is generated and the reference counter value is reinitialized. At the same time, the feedback counter increases for every pulse from the local signal. When a hit signal is generated, the value of the feedback counter is compared with a configurable feedback value (by subtraction) to produce a difference value. The difference value is then converted to a frequency adjustment signal to be used to increase or decrease the frequency of the local oscillator. The hit signal also reinitializes the feedback counter.

Description

{FREQUENCY SYNCHRONIZATION}

The present invention relates to digital electronic devices. More particularly, the present invention relates to a method and system for frequency synchronization of one oscillator producing one clock signal with another oscillator producing another clock signal.

BACKGROUND OF THE INVENTION [0002] Advances in digital electronic devices and communications have generated a multitude of digital devices to consumers. Digital music players and cellular telephones are two outcomes of this evolution. In some of these devices, the clock signal driving digital electronic device components may need to be synchronized. By way of example, in order to ensure that device A operates smoothly with device B, their clock signals may need to be frequency synchronized with each other.

Clock synchronization may be possible using a phase locked loop (PLL), but this approach requires complex signal processing and is not suitable for low power applications. Also, the phase locked loop is not necessarily able to adjust the variation state. If one of the clock signals is tracking drift from the expected frequency, the inexpensive PLL may not be tuned. PLLs also require more frequency tracking between the two signals, and more than needed for some applications that do not necessarily require phase tracking.

Therefore, there is a need for frequency stabilized looping that is suitable for use with digital electronic devices that do not require complex signal processing and are easy to implement. It would also be desirable if such a solution was also suitable for use in synchronizing the clock signal over the wireless link. Preferably, the solution will be able to adjust the frequency of the VCO (voltage controlled oscillator).

The present invention provides a system and method for digital frequency locked looping that synchronizes the frequency between a local clock signal from a local oscillator and a reference clock signal from a remote oscillator.

According to one embodiment of the invention, a system is provided for synchronizing a first frequency of a local clock signal with a second frequency of a reference clock signal. The reference counter block includes an N divide circuit that divides the number of received pulses of the reference clock signal by a value N equal to a predetermined reference value and generates a hit signal if the number of received pulses is a predetermined reference value. The feedback counter block receives the local clock signal and the hit signal, counts pulses of the local clock signal between consecutively received hit signals, and counts a feedback count having a value corresponding to a count of pulses of the local clock after the last hit signal And a resettable counter circuit for generating a signal. The adder circuit receives the feedback count signal and the predetermined feedback value and generates a count error signal therefrom that represents the difference between the value of the feedback count signal and the predetermined feedback value. The controller block includes circuitry for receiving the count error signal and the hit signal and generating a frequency adjustment signal based on the count error signal, wherein the controller block is triggered by receipt of the heat signal, / RTI > is used to synchronize the first frequency by increasing or decreasing the first frequency.

The frequency adjustment signal is preferably generated by adjusting the frequency adjustment signal by the count error signal whenever a hit signal is received. The N-divider circuit receives the reference clock signal, increases the reference counter value upon receipt of each pulse of the reference clock signal, generates a hit signal if the reference counter value equals the predetermined reference value, Re-initialize the counter value. The resettable counter circuit is capable of receiving a local clock signal and a hit signal, increasing the feedback counter value upon receipt of each pulse of the local clock signal, and outputting a feedback count signal, Is the number of pulses of the local clock signal. Preferably, the predetermined reference value and the predetermined feedback value are related and are integers. The reference clock signal is derived from the rate of reception of the packet from the remote transmitter, and the packet may be transmitted in a wireless manner by the transmitter.

Preferably, the system further comprises a metastable hardening circuit for receiving the heat signal and outputting a modified heat signal received by the controller block and a feedback counter block instead of a heat signal. The front-end circuit cures the received heat signal and the back-end circuit performs the negative edge detection function. The modified hit signal allows the intersection between the clock regions of the reference and local clock signals.

According to another embodiment of the present invention, a method for frequency synchronization between a reference clock signal having a first frequency and a local clock signal having a second frequency is provided. A reference clock signal is received and increases the value of the first counter for all received pulses of the reference clock signal. If the value of the first counter is compared with the predetermined reference value and the value of the first counter is equal to the predetermined reference value, a hit signal is generated and the value of the first counter is reinitialized. Simultaneously with previous steps, a local clock signal is received and the value of the second counter increases for every pulse received of the local clock signal. When a hit signal is generated, the value of the second counter is received, the value of the second counter is compared with the predetermined feedback value, and a frequency adjustment signal is generated based on the comparison. The frequency adjustment signal is used for synchronization to increase or decrease the second frequency. The second counter is reset when a hit signal is generated.

According to another embodiment of the present invention, there is also provided a method of synchronizing a first frequency of a local clock signal with a second frequency of a reference clock signal, the method comprising: comparing a number of received pulses of a reference clock signal with a predetermined reference value Dividing by the same value N and generating a hit signal if the number of received pulses is the predetermined reference value. A local clock signal and a hit signal are received, and a pulse of the local clock signal is counted between consecutively received hit signals. A feedback count signal having a value corresponding to the count of pulses of the local clock after the last hit signal is generated. A feedback count signal and a predetermined feedback value are received and a count error signal is generated that represents the difference between the value of the feedback count signal and the predetermined feedback value. Upon generation of the heat signal, the heat signal and the count error signal are received, and the frequency adjustment signal is generated based on the count error signal. The frequency adjustment signal is used to synchronize the first frequency by increasing or decreasing the first frequency.

The invention will be better understood by consideration of the detailed description with reference to the following figures.

1 is a block diagram of a receiver-transmitter system in which an embodiment of the present invention may be used.

2 is a block diagram of one embodiment of the present invention.

3 is a block diagram of a possible design of a reference counter block that may be used in an embodiment of the present invention.

Figure 4 illustrates a possible configuration of a feedback counter block that may be used with an embodiment of the present invention.

Figure 5 illustrates a possible configuration of a controller block that may be used with embodiments of the present invention.

Figure 6 shows another embodiment of the present invention.

Figure 7 is a block diagram of a possible configuration of a curing block that may be used with the embodiment of Figure 6;

Referring to Figure 1, a receiver-transmitter is shown in which an embodiment of the present invention may be used. The system 10 has a multimedia data source 20, a transmitter 30, a receiver 40 and a multimedia destination 50. The data source may be any device that can be used to reproduce or create a personal digital music player (commonly referred to as an MP3 player), a CD player, or a multimedia (e.g., audio or video) data signal. The transmitter 30 receives the multimedia data signal and transmits the data to the receiver 40 in fixed packets at regular intervals. Transmission may be performed via the wireless link 45. The receiver 40 then reconstructs the multimedia data from the packet and sends a signal to the destination 50. In the drawing, the destination 50 is shown as a headphone, but other destinations (e.g., stereo or other devices) for multimedia data may be used.

In some implementations of the above receiver-transmitter system, it is necessary to frequency-synchronize the clock signal of the data source 20 and the transmitter 30. Some implementations may require that the frequency of the clock signal for receiver 40 and transmitter 30 be synchronized. By allowing transmitter 30 to transmit a uniformly spaced packet to a receiver 40 at a constant rate related to the clock signal of the transmitter (even if there is no data to transmit), the clock signals of receiver 40 and transmitter 30 are frequency- A wireless link may be used. The receiver 40 may then use the rate of reception of the packet to ascertain the clock signal frequency of the transmitter.

To synchronize the frequency between the data source 20 and the transmitter 30, the transmitter receives the clock signal of the data source 20 via a hard wired connection and synchronizes the frequency with this clock signal. Once the frequency is synchronized, the transmitter 30 can frequency-synchronize with the receiver 40.

It should be noted that the term " frequency synchronized "herein means synchronizing the frequencies of two signals. Thus, the expression for frequency synchronization of signals A and B means to ensure that if signal A has frequency A1, signal B has frequency A2, and the relationship between A1 and A2 is the intended integer It is rain. Ideally, frequency synchronization may also require tracking the reference frequency and adjusting the local clock frequency to account for changes in the reference frequency. Frequency synchronization does not require phase synchronization. Thus, if the signals A and B are frequency synchronized to the frequencies A1 and A2, these signals may be out of phase with each other.

Referring to Figure 2, a block diagram of one embodiment of the present invention is shown. 2 shows a block diagram of a frequency synchronization system 100 in accordance with an aspect of the present invention.

In the system 100, the reference counter block 110 receives the reference clock signal 120 and the reference value Nr 130. A hit signal 140 is generated by the reference counter whenever the number of clock pulses in the reference clock signal 120 equals the number of reference values 130. Thus, a hit signal is generated whenever the counted clock pulse (the number of clock pulses that have elapsed since the last hit signal) equals the reference value 130. The hit signal reinitializes the reference counter whenever a hit signal is generated.

The feedback signal 150 is received by the controller block 160 as a reset signal and the hit signal 140 is received. The feedback counter block 150 receives the local clock signal 165 and the start value 175 as an input from the local oscillator 170. The feedback counter block 150 counts the number of pulses in the local clock during the occurrence of the hit signal 140.

The feedback counter block 150 outputs the feedback count signal 180 as the number of local clock signal pulses after the last hit signal. This feedback count signal 180 is then received by the adder 185. The adder 185 subtracts the feedback value Nf from the feedback count signal 180 to generate the count error signal 190.

A count error signal 190 is received by the controller block 160. The controller block 160 generates a frequency adjustment signal 195 that adjusts the frequency of the local oscillator 170 using the count error signal 190. Based on the frequency adjustment signal 195, the frequency of the local oscillator increases or decreases to synchronize the frequency of the local oscillator with the frequency of the reference clock signal 120.

Referring to FIG. 3, a sample circuit that may be used in the reference counter block 110 is shown. The block diagram of Figure 3 shows an N-divide circuit. Other types and configurations of N divide circuits may be used in place of the circuit of FIG.

The circuit of FIG. 3 includes a multiplexer 200, a register 210, a comparator 220, and an adder 230. The output of the comparator 220 is the hit signal 140, which is the output of the reference counter block 110. This hit signal 140 is also a selector input to the multiplexer 200. The count output 240 of the register 210 is received by both the adder 230 and the comparator 220. The comparator 220 also receives the reference value 130 as an input. The output 250 of the multiplexer 200 is received as one of the inputs of the register. Register 210 is clocked by reference clock signal 120. The multiplexer 200 receives as an input the output 260 of the adder 230 and a constant value 270 (in the illustrated embodiment, this value is 1). The adder 230 receives the constant value 280 as input and the count output 240 of the register. As will be appreciated by those skilled in the art, another configuration for this N-divide block is to set (i.e., initialize) the reference counter value to a predetermined reference value and decrease upon receipt of each pulse of the reference clock signal, A hit signal will be generated when this reference counter value is zero. In this embodiment, each generation of the hit signal will reinitialize the reference counter value to a predetermined reference value. In this embodiment, a hit signal is generated whenever the number of pulses of the reference clock signal that has elapsed since the last hit signal is equal to the predetermined reference value.

The circuit operates by outputting a high value on the hit signal 140 whenever the value of the count output 240 equals the reference value 130. When this occurs, the output of the multiplexer 200 is considered to be a constant value 270 (again, in one embodiment, its value is 1). This constant value is written to the register every time the count signal 240 is equal to the reference value 130. [ The value of the count signal 240 is incremented by the adder 230. This increment value is output as an output 260 by the adder 230 and is stored in the register in the next clock period by being selected in the multiplexer by the resulting row value of the hit signal 140. [

As a result, the circuit effectively counts the clock pulse of the reference clock signal, and the hit signal is generated and the count is reinitialized each time the number of clock pulses reaches the value (Nr).

Referring to FIG. 4, a sample circuit for feedback counter block 150 is shown. The feedback counter 150 is essentially a resettable counter. The circuit of FIG. 4 is provided only as an example of a resettable counter. Other resettable counter circuits may be used.

The resettable counter circuit 300 includes a multiplexer 310, a register 320, and an adder 330. The output of the register 320 is the feedback count 180 while the input of the register is the local oscillator clock signal 165 and the output 340 of the multiplexer 310. The multiplexer 310 has three inputs where the hit signal 140 is the selector signal while the start value 175 and the count output 350 of the adder 330 provide a selection for the multiplexer 310 . The adder 330 increases the feedback count 180 by a constant value 360, which in the embodiment of FIG. 4 has a constant value of one.

As will be appreciated by those skilled in the art, another configuration for the resettable counter circuit block is to set (i.e., initialize) the feedback counter value to a predetermined feedback value upon receipt of the hit signal, and to decrease the feedback counter value upon receipt of the local clock signal And outputs a feedback count signal. In this embodiment, a count error signal is derived directly from the feedback count signal, whereby upon receipt of the hit signal, the count error signal is a count of the number of pulses of the local clock signal that has occurred between the receipt of the hit signal and the predetermined feedback value It's a car.

The circuit 300 counts the pulses of the local oscillator clock signal 165 and outputs this feedback count 180. When the hit signal 140 is received, the counter is reset to the start value, which is selected as 1 in Fig. Reset to zero or any other value can be used by using this starting value on the start signal line.

Referring to FIG. 5, a circuit 400 that may be used in the controller block 150 is shown. The circuit 400 receives the count error signal 190 from the adder 185. As described above, the value of the count error signal 190 is the difference between the feedback count value 180 and the feedback value 187. [ In circuit 400, the register 410 is clocked by the hit signal 140. The register 410 receives as input the output 195 of the adder 420 receiving the count error signal 190. The adder 420 also receives the output of the register 410. The output 195 of the adder 420 is the frequency adjustment signal 195 of FIG. Therefore, the circuit 400 adds all the values in the register 410 to the count error signal value each time a hit signal is generated, and the result is the input to the register. Since the count error signal is the difference between the feedback value 187 and the feedback count value 180, the frequency feedback adjustment signal 195 is a cumulative tracking of the difference between the local oscillator frequency and the intended integer multiple of the frequency of the reference clock signal. In one embodiment, if the local oscillator frequency is lower than an intended multiple of the frequency of the reference clock signal, the feedback adjustment signal will be proportional to the difference of the two frequencies. Thus, the feedback adjustment signal will cause the local oscillator to increase the frequency by an amount associated with the value of the feedback adjustment signal. Similarly, if the local oscillator frequency is higher than an intended multiple of the frequency of the reference clock signal, the feedback adjustment signal will cause the local oscillator to lower the frequency.

Referring now to Fig. 6, another possible configuration of system 100 is shown. The system 100A of FIG. 6 is similar to the system 100 of FIG. 2, except that a metastable hardening block 500 is added to the system 100 of FIG. The hardening block 500 receives the heat signal 140 and outputs the modified heat signal 140A. The modified hit signal 140A is a clock and reset signal received by the controller block 160 and the feedback counter block 150, respectively. The metastability hardening block 500 causes the heat signal to cross from one clock region (reference clock) to another clock region (i.e., the local oscillator clock). The metastable hardening block 500 provides an improvement over the base system, but is not required.

Referring to FIG. 7, a block diagram of a possible hardening block 500 is shown. As can be seen, the hit signal 140 is received by one of the three cascaded D flip-flops 520A, 520B, 520C. The D flip-flop 520A receives the hit signal 140 and its output is received by the D flip-flop 520B. Similarly, D flip-flop 520B has an output received by D flip-flop 520C. However, the negative of the output of D flip-flop 520B is also received by AND gate 530 along with the output of D flip-flop 420C. The output of AND gate 530 is a modified hit signal 140A.

The first two flip-flops 520A and 520B provide metastable curing of the signal while the remainder of the circuit performs a negative edge detection function.

It should be noted that the three flip-flops 520A, 520B, 520C are all clocked by the local clock signal 165. It should also be appreciated that other designs may be used in hardening block 500.

It is clear that the determination of the value for the reference hit value (Nr) and the feedback value (Nf) determines when the hit signal is generated and when the frequency of the local clock signal increases or decreases. Ideally, the values for Nr and Nf are related and are integers. Since the reference clock is assumed to be a relatively constant pulse train, Tr can be defined as the nominal time interval between reference clock pulses. Similarly, Tx can be defined as the nominal time interval of the local clock signal. The main relationship between Nf and Nr is as follows.

Thus, it is assumed that the nominal frequency of the reference clock as well as the nominal frequency of the local clock are known. The system only causes the local clock to be frequency synchronized to the reference clock so that the frequency of the local clock also changes accordingly if the frequency of the reference clock moves or changes slightly.

In embodiments where the system synchronizes the local clock frequency with a wired or attached device (e.g., the reference clock is provided by the audio source coupled to the system), particularly when the nominal local clock frequency is known, a value for Nr and Nf The decision is simple. In one implementation, the nominal local clock frequency is 22.5792 MHZ. In such an embodiment, Nf = 1000000 and Nr is given in the following table for the specific value of the reference clock frequency.

As described above, the system may be used to synchronize the clock signal over a wireless connection. Obviously, the receiver 40 will attempt to synchronize the local clock frequency with the clock frequency of the transmitter 30 (see FIG. 1). In such an implementation, the transmitter 30 will deliver a fixed stream of evenly spaced packets of the receiver 40. The rate at which the fixed packet is received at the receiver 40 may be used as a reference clock for the case of a system installed on the receiver 40. [

Again, assuming that the fixed packet reception rate is related to the remote clock frequency, it is clear that the fixed packet reception rate is associated with the desired value of Nr and Nf. The reciprocal of the reception rate is the time interval during which each packet is received. As such, the time interval can be defined as Tr. If the nominal local clock frequency is known and the nominal fixed packet reception rate is known, the ratio of Nf to Nr can be obtained by using the following equation:

It should also be noted that ideally, the interval over which the packet is received is an integer multiple of the local clock frequency, since a nonnegative multiplication can result in a small degree of drift to the circuit.

It should be noted that the terms "signal " and" value "are used interchangeably herein because all values are expressed using digital signals and all signals can be interpreted as having integer values. Also, the signal and value are single bit or multi bit. Using the principles presented above, one of ordinary skill in the art will know which signal and which value is a single bit or a multi-bit, depending on the implementation.

While several illustrative embodiments of the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made to the apparatus to thereby attain certain advantages of the invention without departing from the true scope thereof.

Those skilled in the art of the present invention can now understand other structures and embodiments or variations, all of which are intended to be within the scope of the present invention as defined in the following claims.

Claims (19)

A system for synchronizing a first frequency of a local clock signal with a second frequency of a reference clock signal, (a) dividing the number of received pulses of the reference clock signal by a value N equal to a predetermined reference value, and if the number of received pulses is the predetermined reference value, generating a hit signal, A reference counter block including a divide-by-N circuitry, (b) receiving the local clock signal and the hit signal, counting pulses of the local clock signal between consecutively received hit signals, and counting a value corresponding to a count of pulses of the local clock signal after the last hit signal A feedback counter circuit comprising a resettable counter circuit configured to generate a feedback count signal, (c) an adder circuit for receiving the feedback count signal and the predetermined feedback value and for generating a count error signal indicative of the difference between the value of the feedback count signal and the predetermined feedback value therefrom; (d) a controller block comprising circuitry for receiving the count error signal and the hit signal and for generating a frequency adjustment signal based on the count error signal, the controller block being triggered by receipt of the hit signal, Wherein the frequency adjustment signal is used to synchronize the first frequency by increasing or decreasing the first frequency Frequency synchronization system. The method according to claim 1, The controller block generates the frequency adjustment signal each time a hit signal is received and adjusts the frequency adjustment signal by the count error signal Frequency synchronization system. The method according to claim 1, Wherein the N divider circuit receives the reference clock signal and increases the reference counter value upon receipt of each pulse of the reference clock signal, If the reference counter value is equal to a predetermined reference value, the hit signal is generated, and the hit signal reinitializes the reference counter value Frequency synchronization system. The method of claim 3, Wherein the resettable counter circuit receives the local clock signal and the hit signal, the feedback counter value increases upon receipt of each pulse of the local clock signal, a feedback count signal is output, Wherein the feedback count signal is a number of pulses of the local clock signal between receipt of the hit signal Frequency synchronization system. 3. The method of claim 2, Wherein the predetermined reference value is associated with the predetermined feedback value Frequency synchronization system. 6. The method of claim 5, Wherein the predetermined reference value is related to the predetermined feedback value by the following equation,

Nf is the predetermined feedback value, Nr is the predetermined reference value, Tr is a time interval between pulses of the reference clock signal, Tx is the time period between the pulses of the local clock signal Frequency synchronization system. The method according to claim 6, Wherein the predetermined reference value and the predetermined feedback value are integers Frequency synchronization system. The method according to claim 1, The reference clock signal is derived from the rate of reception of a packet from a remote transmitter Frequency synchronization system. 9. The method of claim 8, The packet is transmitted in a wireless manner by the transmitter Frequency synchronization system. The method according to claim 1, A back-end circuit configured to receive the hit signal and to harden the received hit signal and a back-end circuit configured to perform a negative edge detection function, wherein the feedback counter block and the back- Outputting a modified hit signal for reception by the controller block such that the modified hit signal provides a metastable hardening citcuitry that allows the crossing between the reference clock signal and the clock regions of the local clock signal. More included Frequency synchronization system. A method for frequency synchronization between a reference clock signal having a first frequency and a local clock signal having a second frequency, (a) receiving the reference clock signal; (b) increasing the value of the first counter for all received pulses of the reference clock signal; (c) comparing the value of the first counter with a predetermined reference value; (d) if the value of the first counter is equal to the predetermined reference value, generating a hit signal and re-initializing the value of the first counter; And a step (e) receiving the local clock signal; (f) increasing a value of a second counter for all received pulses of the local clock signal; When a hit signal is generated, (g) receiving the value of the second counter; (h) performing a comparison of the value of the second counter and a predetermined feedback value, (i) generating a frequency adjustment signal based on the comparison, Thereby, the frequency adjustment signal is used for synchronization to increase or decrease the second frequency, and when the hit signal is generated, the second counter is reset Frequency synchronization method. 12. The method of claim 11, Wherein the comparison of the value of the second counter and the predetermined feedback value is performed by subtracting the predetermined feedback value from the value of the second counter to generate a difference Frequency synchronization method. 13. The method of claim 12, Wherein the frequency adjustment signal is based on the difference Frequency synchronization method. 12. The method of claim 11, Wherein the predetermined reference value and the predetermined feedback value are integers, Frequency synchronization method. 15. The method of claim 14, Wherein the predetermined reference value is related to the predetermined feedback value by the following equation,

Nf is the predetermined feedback value, Nr is the predetermined reference value, Tr is the nominal time interval between the pulses of the reference clock signal, Tx is the nominal time period between the pulses of the local clock signal Frequency synchronization method. CLAIMS 1. A method for synchronizing a first frequency of a local clock signal with a second frequency of a reference clock signal, (a) dividing the number of received pulses of the reference clock signal by a value N equal to a predetermined reference value and generating a hit signal if the number of received pulses is the predetermined reference value; (b) receiving the local clock signal and the hit signal, counting pulses of the local clock signal between consecutively received hit signals, and counting a value corresponding to a count of pulses of the local clock signal after the last hit signal Generating a feedback count signal having a first frequency, (c) receiving the feedback count signal and a predetermined feedback value, generating a count error signal indicative of a difference between the value of the feedback count signal and the predetermined feedback value, (d) receiving the hit signal and the count error signal upon generation of the hit signal, and generating a frequency adjustment signal based on the count error signal, the frequency adjustment signal increasing the first frequency Or used to synchronize said first frequency by < RTI ID = 0.0 > Frequency synchronization method. 17. The method of claim 16, Wherein the division of the received pulse of the reference clock signal is performed by increasing a reference counter value upon receipt of each pulse of the reference clock signal and if the reference counter value equals the predetermined reference value, , Whereby the hit signal re-initializes the reference counter value Frequency synchronization method. 18. The method of claim 17, Counting pulses of the local clock signal between successively received hit signals is performed by increasing the feedback counter value upon receipt of each pulse of the local clock signal Frequency synchronization method. 19. The method of claim 18, Wherein the predetermined reference value is related to the predetermined feedback value by the following equation,

Nf is the predetermined feedback value, Nr is the predetermined reference value, Tr is a time interval between pulses of the reference clock signal, Tx is the time period between the pulses of the local clock signal Frequency synchronization method.

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