CN102223198B - One realizes clock recovery method and device - Google Patents
One realizes clock recovery method and device Download PDFInfo
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- CN102223198B CN102223198B CN201110164332.XA CN201110164332A CN102223198B CN 102223198 B CN102223198 B CN 102223198B CN 201110164332 A CN201110164332 A CN 201110164332A CN 102223198 B CN102223198 B CN 102223198B
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- 101100518559 Homo sapiens OTUB1 gene Proteins 0.000 description 13
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
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Abstract
The present invention provides a kind of method and device realizing clock recovery, and the method includes: during the asynchronous demapping of service layer's data goes out client's layer data, obtains the adjustment information of the described service layer every frame of data；The fractional frequency division factor that the byte number taken by total bytes and the client layer data of the described service layer every frame of data determines is adjusted according to described adjustment information；After carrying out fractional frequency division according to described fractional frequency division factor pair service layer clock, as the reference clock of phaselocked loop, recover client layer clock through described phaselocked loop.The ability of clock transparent transmission and cascade can be improved by the present invention.
Description
Technical field
The present invention relates to optical transport network technology field, particularly relate to (the speed flexibly of oduflex in OTN (optical transfer network) business
Rate light data cell) method and device of clock recovery of mapping/demapping system.
Background technology
(such as PDH (Plesiochronous Digital Hierarchy, plesiochronous digital in digital transmission system
Series), SDH (Synchronous Digital Hierarchy, Synchronous Digital Hierarchy), OTN), it is often necessary in demapping system
The end of system recovers the synchronised clock of customer data.It is said that in general, presently, there are two kinds of sides recovering the clock of customer data
Case:
The first scheme is exactly classical phaselocked loop (PLL), as it is shown in figure 1, such as when STM-64 (Synchronous Transport Module level-N
64), during business is mapped into OTU2 business, then the clock of OTU2 services clock exactly, the clock of STM-64 business is exactly client layer
Clock, it is found that the application of this classical phaselocked loop is suitable only for the clock recovery in the case of synchronization map, is i.e. reflecting
During penetrating without JC (adjustment control byte) or Cm (ITU-T G.709 defined in GMP (general mapping code) mapping mode
The units that middle customer data occupies in service layer) adjust, i.e. client clock and service clock are homologies.
First scheme is exactly to come by the degree of depth of FIFO (First Input First Output, push-up storage)
Produce UP pulse signal and DOWN pulse signal, control VCO (voltage controlled oscillator), as shown in Figure 2:
The breach homogenization that the clock of demapping data is mainly enabled by the function of breach Leveling Block, makes data relative
Uniformly, it is ensured that the FIFO depth during FIFO controls VCO logic below is the most steady.FIFO controls VCO logic and is mainly basis
The degree of depth of FIFO adjusts output UP pulse signal and the dutycycle of DOWN pulse signal, thus adjust outside VCO output time
Clock frequency rate, it is ensured that on the client traffic frequency-tracking of VCO to the business data flow of demapping, this scheme can be used in asynchronous reflecting
Penetrate/demapping system, but, owing to FIFO controls the response of VCO relatively slowly, whole loop is the tracking in frequency.
Along with the increase of cascade progression, phase error can constantly be accumulated, and the quality of PLL output clock can ultimately result in out worse and worse
Existing error code, i.e. cascade ability and clock transparent transmission ability are very limited.
The defect of two schemes:
Scheme one uses PFD (phase discriminator), and therefore the tracking ability of phaselocked loop is strong, not only follows the tracks of in frequency, also
Following the tracks of in phase place, therefore clock cascade ability is strong.But this programme requires that client clock and service clock are homologies, the most only
Only being useful in the system of synchronization map/demapping, therefore range is limited.
Scheme two be with the degree of depth of FIFO produce UP pulse signal, DOWN pulse signal instead of PFD, although this side
Case can be applicable in asynchronous mapping/demapping system, can recover clock information from data code flow, but institute as discussed above
Stating, owing to FIFO controls the response of VCO relatively slowly, whole loop is the tracking in frequency.Increasing along with cascade progression
Adding, phase error can constantly be accumulated, and the quality of PLL output clock can ultimately result in and error code occur worse and worse, i.e. cascades ability
It is very limited.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of method and device realizing clock recovery, saturating to improve clock
Pass and the ability of cascade.
In order to solve above-mentioned technical problem, the invention provides a kind of method realizing clock recovery, including:
During the asynchronous demapping of service layer's data goes out client's layer data, obtain the tune of the described service layer every frame of data
Whole information；
Adjust according to described adjustment information and to be taken by the total bytes of the described service layer every frame of data and client layer data
The fractional frequency division factor that byte number determines；
After carrying out fractional frequency division according to described fractional frequency division factor pair service layer clock, as the reference clock of phaselocked loop,
Client layer clock is recovered through described phaselocked loop.
Further, said method also has following feature: described fractional frequency division factor R is represented by following formula:
R=(Y0+ Δ Y1)/X*N,
Wherein, the nominal byte number that during Y0 is every frame, client layer data take；X is total word of the described service layer every frame of data
Joint number, N is a constant；
According to the adjustment of described adjustment information, Δ Y1 is equal to+2 ,+1 ,-1 ,-2 or 0.
Further, said method also has a following feature:
The described fractional frequency division factor adjusts always according to the full indication signal of sky of memorizer, described memorizer for storage from
The client layer data that described service layer data demapping goes out, described fractional frequency division factor R is expressed as:
R=(Y0+ Δ Y1+ Δ Y2)/X*N,
Wherein, if the full indication signal of described sky indicates described memorizer by full, then Δ Y2 is equal to+1；
If the full indication signal of described sky indicates described memorizer by sky, then Δ Y2 is equal to-1；
If the full indication signal instruction of described sky is normal, then Δ Y2 is equal to 0.
Further, said method also has a following feature: described according to described fractional frequency division factor pair service layer clock
Carry out fractional frequency division particularly as follows: take advantage of service layer's clock in the described fractional frequency division factor.
In order to solve the problems referred to above, present invention also offers a kind of device realizing clock recovery, including:
Asynchronous De-mapping module, for during demapping goes out client's layer data from service layer's data, obtains institute
Stating the adjustment information of the every frame of service layer's data, output is to phase demodulation clock generation module；
Described phase demodulation clock generation module, for adjusting total by the described service layer every frame of data according to described adjustment information
The fractional frequency division factor that the byte number that byte number and client layer data take determines, according to described fractional frequency division factor pair service layer
Clock carries out fractional frequency division, and the reference clock as phaselocked loop exports to described phaselocked loop；
Described phaselocked loop, for recovering client layer clock according to described reference clock.
Further, said apparatus also has a following feature:
Described fractional frequency division factor R is represented by following formula:
R=(Y0+ Δ Y1)/X*N,
Wherein, the nominal byte number that during Y0 is every frame, client layer data take；X is total word of the described service layer every frame of data
Joint number, N is a constant；According to the adjustment of described adjustment control byte, Δ Y1 is equal to+2 ,+1 ,-1 ,-2 or 0.
Further, said apparatus also has following feature: described device also includes:
Asynchronous buffer logic module, for storing the client that described asynchronous De-mapping module goes out from service layer's data demapping
Layer data, exports full for the sky of storage indication signal to described phase demodulation clock generation module；
Described phase demodulation clock generation module, is additionally operable to adjust the described fractional frequency division factor according to the full indication signal of described sky
R, described fractional frequency division factor R is expressed as:
R=(Y0+ Δ Y1+ Δ Y2)/X*N,
Wherein, if the full indication signal of described sky indicates described asynchronous buffer logic module by full, then Δ Y2 is equal to+1；If institute
Stating empty full indication signal indicates described asynchronous buffer logic module by sky, then Δ Y2 is equal to-1；If the full indication signal of described sky refers to
Show normal, then Δ Y2 is equal to 0.
Further, said apparatus also has following feature: described asynchronous buffer logic module is push-up storage.
Further, said apparatus also has a following feature:
Described asynchronous De-mapping module, is additionally operable to during from service layer's data, demapping goes out client's layer data,
The nominal byte number that total bytes and the client layer data of the described service layer every frame of data take is notified that described phase demodulation clock produces
Raw module.
Further, said apparatus also has a following feature:
Described phase demodulation clock generation module, is additionally operable to be previously stored with total bytes and the visitor of the described service layer every frame of data
The nominal byte number that family layer data takies.
To sum up, the present invention provides a kind of method and device realizing clock recovery, utilizes phase discriminator cascade strong excellent of ability
Point, phaselocked loop can be applied in asynchronous mapping/demapping system so that clock transparent transmission and cascade ability are greatly improved.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of classical phaselocked loop；
Fig. 2 is the schematic diagram of a clock recovery system of prior art；
Fig. 3 is the schematic diagram of the clock recovery device of the embodiment of the present invention；
Fig. 4 is the flow chart of the method realizing clock recovery of the present invention；
Fig. 5 is the schematic diagram of the OTU1 frame structure of the embodiment of the present invention；
Fig. 6 is the flow chart of the method realizing clock recovery of the embodiment of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to the present invention
Embodiment be described in detail.It should be noted that in the case of not conflicting, in embodiment in the application and embodiment
Feature can mutual combination in any.
As it is shown on figure 3, the clock recovery device of the embodiment of the present invention mainly includes 4 parts: asynchronous De-mapping module, different
Step cache logic module, phase demodulation clock generation module and phaselocked loop, wherein,
Asynchronous De-mapping module: identical with traditional De-mapping module, goes out client layer in demapping from service layer's data
Data, the adjustment information obtaining service layer's every frame of data exports to phase demodulation clock generation module；
In AMP (asynchronous mapping code) pattern, described adjustment information is JC (adjustment control byte), in GMP pattern,
Described adjustment information is Cm information.In the present embodiment as a example by AMP pattern, asynchronous De-mapping module can be by JC and frame originating point information
Synchronization is sent, it is provided that to phase demodulation clock generation module.
Phase demodulation clock generation module: for adjusting the total bytes by the described service layer every frame of data and client layer according to JC
The fractional frequency division factor that the byte number that data take determines, carries out decimal according to described fractional frequency division factor pair service layer clock and divides
Frequently, the reference clock as phaselocked loop exports to described phaselocked loop；
Wherein, frame originating point information is used for reminding this renewal adjustment information of phase demodulation clock generation module, phase demodulation clock generation module
The JC provided according to asynchronous De-mapping module, can know how many words during customer data takies whole frame on earth in each frame
Joint.
Wherein, client during phase demodulation clock generation module can be previously stored with the total bytes of service layer's Frame and every frame
The information of the nominal byte number that data take.Can also be asynchronous De-mapping module during demapping service layer data,
The information of the nominal byte number taken by customer data in the total bytes of service layer's Frame and every frame notifies to phase demodulation clock
Generation module.
Assuming that servicing clock is f1, the total bytes in service layer's data frame structure is X, can calculate at frame according to JC
In structure, the byte number of customer data, is designated as Y, then clock frequency f2=f1*Y/X of customer data, and wherein, X is a constant, Y
Then dynamically adjust according to the JC value of every frame.
Note Y0 is the nominal byte number that in every frame, customer data takies, then Y=Y0 ± Δ Y1 ± Δ Y2.
Wherein, when Δ Y1 produces according to the value of the JC of every frame, when this frame does negative justification when, JC=1, then Δ Y1 etc.
In+1, when this frame does positive 1 adjustment when, then JC=3, then Δ Y1 is equal to-1, when this frame does positive 2 adjustment when, then JC=
2, Δ Y1 are equal to-2；When without adjusting when, JC=0, Δ Y1=0.
If Δ Y1 produces according to the value of the Cm of every frame, carry out coding according to Cm value and calculate, Δ Y1 can equal to+2 ,+
1,0 ,-1 ,-2 etc..
Wherein, Δ Y2 is the amount of a standby fine setting, produces according to the full indication signal of the sky of asynchronous buffer logic module, if
Empty full indication signal indicates described asynchronous buffer logic module by full, then Δ Y2 is equal to+1；If the full indication signal instruction of described sky
Asynchronous buffer logic module is by sky, then Δ Y2 is equal to-1；If the full indication signal instruction of described sky is normal, then Δ Y2 is equal to 0.Typically
For, Δ Y2=0.
According to the principle of phaselocked loop, the reference clock frequency to be kept with feedback clock inputing to phase discriminator is consistent.In order to
Reducing shake as far as possible, promote the quality of clock, the generation of feedback clock can be in the way of using integral frequency divisioil, and note Frequency Dividing Factor is
M, the output clock frequency of note VCO is fvco, then according to phaselocked loop phase-demodulating principle, obtain formula (1):
Fvco/M=f2/N (1)
Due to fvco=f2, then N=M.
According to analysis above, the relation of f2 and f1 is:
F2=f1*Y/X (2)
Y=Y0+ Δ Y1+ Δ Y2 (3)
Obtained by formula 1,2,3:
Fvco/M=f1* (Y0+ Δ Y1+ Δ Y2)/X*N (4)
Knowing according to formula 4, the core circuit of phase demodulation clock generation module carries out integral frequency divisioil, frequency dividing ratio to fvco exactly
For M, service layer clock f1 being carried out fractional frequency division, fractional frequency division factor R is Y/X*N, and wherein X, N, M are constants, Y then basis
JC or the CM overhead byte of asynchronous De-mapping module and the full indication signal of the sky of asynchronous buffer logic module produce, and every frame moves
State fine setting fractional frequency division factor R, reaches to follow the tracks of the purpose of demapping data clock rate.
Asynchronous buffer logic module: a relatively large asynchronous FIFO, be used for storing described asynchronous De-mapping module from
The client layer data that service layer's data demapping goes out, it is ensured that can tolerate that the data breach that asynchronous demapping produces is unlikely to cause
Cache overflow, exports full for the sky of storage indication signal to described phase demodulation clock generation module.
In theory, due to this FIFO read-write both sides clock frequency be macroscopically synchronized, therefore FIFO will not have time,
Full phenomenon.But in practical operation, it is contemplated that the clock breach factor impact of read-write clock and the locking time of phaselocked loop
Factor, reversely to produce Δ Y2 when detecting when FIFO is the most empty or soon expires, be finely adjusted the fractional frequency division factor, it is ensured that
FIFO will not overflow.Generally speaking Δ Y2 is 0, and Δ Y2 is used merely to deal with special circumstances, increases the robustness of system design.
Phaselocked loop can be common phaselocked loop, by PFD (classical phase discriminator), LPF (low pass filter) and VCO (pressure
Controlled oscillator) constitute, for recovering client layer clock according to described reference clock.
Fig. 4 is the flow chart of a kind of method realizing clock recovery of the embodiment of the present invention, as shown in Figure 4, the present embodiment
Method include below step:
S10, during the asynchronous demapping of service layer's data goes out client's layer data, obtain the tune of the service layer every frame of data
Whole information；
S20, according to described adjustment information adjust accounted for by total bytes and the client layer data of the described service layer every frame of data
The fractional frequency division factor that determines of byte number；
S30, carry out fractional frequency division according to described fractional frequency division factor pair service layer clock after, during as the reference of phaselocked loop
Clock, recovers client layer clock through described phaselocked loop.
Use the solution of the present invention and device, compared with the prior art, overcome use FIFO depth and control VCO and (voltage-controlled shake
Swing device) clock scheme cause clock cascade limited ability shortcoming, make phaselocked loop i.e. can apply to synchronization map simultaneously
System can also be applied to asynchronous mapping system, improves the clock transparent transmission of asynchronous mapping system and the ability of cascade simultaneously.
Below as a example by asynchronous demapping STM-16 of OTU1, the implementation of the present invention is described.
In the present embodiment, the speed of STM-16 business be the speed of 2488.32kbit/s, OTU1 business be 255/238 ×
2488320kbit/s.STM-16 business asynchronous mapping enters the frame structure of OTU1 as shown in Figure 5.Wherein STM-16 data are mapped into
17-3824 row in OTU1 frame structure, NJO be negative justification byte, PJO be that positive justification byte, JC are for adjusting control byte.
Implementing procedure is as shown in Figure 6 in detail, including below step:
Step 101: asynchronous De-mapping module is from OTU1 business, and according to the instruction of JC, NJO, PJO, demapping goes out STM16
Business Stream, export the frame head of OTU1 and the JC indication signal of every frame simultaneously.
Step 102: the clock frequency of writing of asynchronous buffer logic module write side is 166.63MHZ, and write enable signal is by different
Step De-mapping module provides, and the clock reading side is VCXO clock, i.e. 155.52MHZ clock, simultaneously by full for the sky of FIFO signal
It is supplied to phase demodulation clock generation module.
Step 103: to VCO feedback clock carry out integral frequency divisioil, OTU1 clock is carried out fractional frequency division, fractional frequency division because of
Daughter root completely indicates every frame dynamically to adjust according to the sky of JC instruction and caching FIFO；
Specifically, frame head and the JC of every frame that phase demodulation clock generation module provides according to asynchronous De-mapping module indicate, can
To know in each frame OTU1, STM-16 data take how many bytes on earth, so that it is determined that ginseng in formula (1), (2), (3), (4)
The concrete numerical value of number, as follows:
Fvcxo=155.52MHZ (owing to the speed that clock frequency is 2488.32MHZ, 2.488G of STM-16 is the highest,
Reality hardware circuit uses the frequency of its 16 frequency dividing, i.e. the benchmark frequency of SDH in realizing, after obtaining this frequency, can use again
Serdes (parallel series and staticizer) or doubler obtain STM-16 frequency)
(speed of 2.66G is the highest, realizes at reality hardware circuit for f1=255/238 × 2488320/16=166.63MHZ
Time uses the frequency of its 16 frequency dividing, i.e. the reference clock frequency of OTU1, after obtaining this frequency, can again with Serdes or again
Frequently device obtains STM-16 frequency).
X=4*4080, is the byte number of the every frame of OTU1.
Y0=3808*4, i.e. STM-16 are mapped into every frame nominal byte number of OTU1.
, i.e. there are 1 positive justification byte and 1 negative justification byte in Δ Y1=± 1 or 0 due to each OTU1 frame.Work as negative justification
When (JC=1, NJO are data, and PJO is data), Δ Y1=+1；When positive justification when, (now JC=3, NJO are for filling
Byte, PJO is byte of padding), Δ Y1=-1；When without adjusting when, (now JC=0, NJO are byte of padding, and PJO is number
According to), the every frame of Δ Y1=0, Δ Y1 updates once.
Δ Y2 completely determines according to the sky of asynchronous buffer FIFO, when FIFO by sky when, show that read rate is faster than writing speed,
So Δ Y2=-1, when FIFO will expire when, shows that read rate is less than writing speed, and Δ Y2=+1, at the waterline of FIFO
When rational position, then the every frame of Δ Y2=0, Δ Y2 updates once.
The value of M, N to consider the bandwidth of low pass filter and the device property of VCO so that phaselocked loop
Can be optimal, take M=N=8 in this example, certain M, N can also take other value, be not limited to this.
After determining parameter, carry out M integral frequency divisioil and fractional frequency division, produce reference clock and feedback clock is supplied to
The PFD of phaselocked loop.
Step 104:PFD carries out phase demodulation to input reference clock and feedback clock, produces UP pulse signal and DOWN pulse
Signal is supplied to LPF, recovers client layer clock eventually through VCO, reads FIFO.
One of ordinary skill in the art will appreciate that all or part of step in said method can be instructed by program
Related hardware completes, and described program can be stored in computer-readable recording medium, such as read only memory, disk or CD
Deng.Alternatively, all or part of step of above-described embodiment can also use one or more integrated circuit to realize.Accordingly
Ground, each module/unit in above-described embodiment can realize to use the form of hardware, it would however also be possible to employ the shape of software function module
Formula realizes.The present invention is not restricted to the combination of the hardware and software of any particular form.
These are only the preferred embodiments of the present invention, certainly, the present invention also can have other various embodiments, without departing substantially from this
In the case of spirit and essence thereof, those of ordinary skill in the art are when making various corresponding change according to the present invention
And deformation, but these change accordingly and deform the protection domain that all should belong to appended claims of the invention.
Claims (10)
1. the method realizing clock recovery, including:
During the asynchronous demapping of service layer's data goes out client's layer data, obtain the adjustment letter of the described service layer every frame of data
Breath；
The byte taken by total bytes and the client layer data of the described service layer every frame of data is adjusted according to described adjustment information
The fractional frequency division factor that number determines；
After carrying out fractional frequency division according to described fractional frequency division factor pair service layer clock, the service layer's clock after fractional frequency division is made
For the reference clock of phaselocked loop, recover client layer clock through described phaselocked loop.
2. the method for claim 1, it is characterised in that: described fractional frequency division factor R is represented by following formula:
R=(Y0+ Δ Y1)/X*N,
Wherein, the nominal byte number that during Y0 is every frame, client layer data take；X is the total byte of the described service layer every frame of data
Number, N is a constant；
According to the adjustment of described adjustment information, Δ Y1 is equal to+2 ,+1 ,-1 ,-2 or 0.
3. method as claimed in claim 2, it is characterised in that:
The described fractional frequency division factor adjusts always according to the full indication signal of sky of memorizer, and described memorizer is for storing from described
The client layer data that service layer's data demapping goes out, described fractional frequency division factor R is expressed as:
R=(Y0+ Δ Y1+ Δ Y2)/X*N,
Wherein, if the full indication signal of described sky indicates described memorizer by full, then Δ Y2 is equal to+1；
If the full indication signal of described sky indicates described memorizer by sky, then Δ Y2 is equal to-1；
If the full indication signal instruction of described sky is normal, then Δ Y2 is equal to 0.
4. as claimed in claim 2 or claim 3 method, it is characterised in that: described according to described fractional frequency division factor pair service layer time
Clock carry out fractional frequency division particularly as follows:
Service layer's clock is taken advantage of in the described fractional frequency division factor.
5. realize a device for clock recovery, including:
Asynchronous De-mapping module, for during demapping goes out client's layer data from service layer's data, obtains described clothes
The adjustment information of the business every frame of layer data, output is to phase demodulation clock generation module；
Described phase demodulation clock generation module, for adjusting by the total byte of the described service layer every frame of data according to described adjustment information
The fractional frequency division factor that number and the byte numbers that take of client layer data determine, according to described fractional frequency division factor pair service layer clock
Carry out fractional frequency division, the service layer's clock after fractional frequency division is exported to described phaselocked loop as the reference clock of phaselocked loop；
Described phaselocked loop, for recovering client layer clock according to described reference clock.
6. device as claimed in claim 5, it is characterised in that:
Described fractional frequency division factor R is represented by following formula:
R=(Y0+ Δ Y1)/X*N,
Wherein, the nominal byte number that during Y0 is every frame, client layer data take；X is the total byte of the described service layer every frame of data
Number, N is a constant；According to the adjustment of described adjustment control byte, Δ Y1 is equal to+2 ,+1 ,-1 ,-2 or 0.
7. device as claimed in claim 6, it is characterised in that: described device also includes:
Asynchronous buffer logic module, for storing client's number of plies that described asynchronous De-mapping module goes out from service layer's data demapping
According to, full for the sky of storage indication signal is exported to described phase demodulation clock generation module；
Described phase demodulation clock generation module, is additionally operable to adjust described fractional frequency division factor R, institute according to the full indication signal of described sky
State fractional frequency division factor R to be expressed as:
R=(Y0+ Δ Y1+ Δ Y2)/X*N,
Wherein, if the full indication signal of described sky indicates described asynchronous buffer logic module by full, then Δ Y2 is equal to+1；If described sky
Full indication signal indicates described asynchronous buffer logic module by sky, then Δ Y2 is equal to-1；If the full indication signal of described sky is just indicating
Often, then Δ Y2 is equal to 0.
8. device as claimed in claim 7, it is characterised in that:
Described asynchronous buffer logic module is push-up storage.
9. the device as described in any one of claim 6-8, it is characterised in that:
Described asynchronous De-mapping module, is additionally operable to during from service layer's data, demapping goes out client's layer data, by institute
State the total bytes of the every frame of service layer's data and nominal byte number that client layer data take notifies that described phase demodulation clock produces mould
Block.
10. the device as described in any one of claim 6-8, it is characterised in that:
Described phase demodulation clock generation module, is additionally operable to be previously stored with total bytes and the client layer of the described service layer every frame of data
The nominal byte number that data take.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110164332.XA CN102223198B (en) | 2011-06-17 | 2011-06-17 | One realizes clock recovery method and device |
| PCT/CN2012/076950 WO2012171475A1 (en) | 2011-06-17 | 2012-06-14 | Method and device for realizing clock recovery |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110164332.XA CN102223198B (en) | 2011-06-17 | 2011-06-17 | One realizes clock recovery method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102223198A CN102223198A (en) | 2011-10-19 |
| CN102223198B true CN102223198B (en) | 2016-12-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110164332.XA Expired - Fee Related CN102223198B (en) | 2011-06-17 | 2011-06-17 | One realizes clock recovery method and device |
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| WO (1) | WO2012171475A1 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102223198B (en) * | 2011-06-17 | 2016-12-21 | 中兴通讯股份有限公司 | One realizes clock recovery method and device |
| CN102523064B (en) * | 2011-11-16 | 2014-06-18 | 武汉日电光通信工业有限公司 | Clock frequency dividing circuit and method based on lookup table |
| CN102859927B (en) * | 2012-05-10 | 2015-03-11 | 华为技术有限公司 | Data and clock recovery module and data and clock recovery method |
| CN103731223B (en) * | 2012-10-16 | 2016-09-28 | 中兴通讯股份有限公司 | A kind of clock recovery method and device |
| CN105515749B (en) * | 2014-10-17 | 2019-12-03 | 中兴通讯股份有限公司 | A kind of method and system for realizing clock transparent transmission during asynchronous mapping |
| CN106341127B (en) * | 2016-09-13 | 2019-04-05 | 龙迅半导体（合肥）股份有限公司 | A kind of method and apparatus that video clock restores |
| CN106341128B (en) * | 2016-09-13 | 2019-04-05 | 龙迅半导体（合肥）股份有限公司 | A kind of method and apparatus of restored audio clock |
| CN112583507B (en) * | 2019-09-29 | 2022-05-10 | 华为技术有限公司 | State control method, data sending method and terminal |
| CN111641892B (en) * | 2020-05-21 | 2022-01-21 | 成都信息工程大学 | High-precision service clock mapping and recovering method in OTN |
| CN111697967B (en) * | 2020-06-29 | 2023-04-18 | 电子科技大学 | Self-adaptive digital clock taming system |
| CN116599621B (en) * | 2023-07-18 | 2023-09-19 | 杭州初灵信息技术股份有限公司 | Method, equipment and device for recovering clock based on cross board transfer and regeneration |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7106224B2 (en) * | 2002-08-14 | 2006-09-12 | Standard Microsystems Corporation | Communication system and method for sample rate converting data onto or from a network using a high speed frequency comparison technique |
| CN1286290C (en) * | 2003-07-11 | 2006-11-22 | 中兴通讯股份有限公司 | An apparatus and method for restoring E3/T3 branch signal from synchronous digital transmission hierarchy |
| CN1848717B (en) * | 2005-04-15 | 2011-04-06 | 华为技术有限公司 | Method for obtaining asynchronous de-mapping clock and circuit |
| US7912381B2 (en) * | 2006-06-02 | 2011-03-22 | Standard Microsystems Corporation | Transmission network having an optical receiver that utilizes dual power pins and a single status pin to lower power consumption, lower manufacturing cost, and increase transmission efficiency |
| CN1946017A (en) * | 2006-10-09 | 2007-04-11 | 华为技术有限公司 | Method and system for clock synchronizing of transmission end and receiving end in package switching network |
| CN1968063B (en) * | 2006-10-26 | 2010-10-27 | 华为技术有限公司 | Clock recovery method and apparatus |
| CN101964688B (en) * | 2009-07-21 | 2015-05-20 | 中兴通讯股份有限公司 | Method and system for recovering data clock |
| CN101707506B (en) * | 2009-11-06 | 2013-05-08 | 中兴通讯股份有限公司 | Business clock transparent transmission method and system in optical transport network |
| CN102223198B (en) * | 2011-06-17 | 2016-12-21 | 中兴通讯股份有限公司 | One realizes clock recovery method and device |
-
2011
- 2011-06-17 CN CN201110164332.XA patent/CN102223198B/en not_active Expired - Fee Related
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2012
- 2012-06-14 WO PCT/CN2012/076950 patent/WO2012171475A1/en active Application Filing
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| Publication number | Publication date |
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| CN102223198A (en) | 2011-10-19 |
| WO2012171475A1 (en) | 2012-12-20 |
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