CN106341128B - A kind of method and apparatus of restored audio clock - Google Patents
A kind of method and apparatus of restored audio clock Download PDFInfo
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- CN106341128B CN106341128B CN201610822840.5A CN201610822840A CN106341128B CN 106341128 B CN106341128 B CN 106341128B CN 201610822840 A CN201610822840 A CN 201610822840A CN 106341128 B CN106341128 B CN 106341128B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
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Abstract
The method and apparatus of restored audio clock disclosed in the present application, first calculate the sample rate of link data sound intermediate frequency data, thus the configuration parameter of phaselocked loop intermediate ring road frequency divider is calculated, and loop divider is configured to obtain the clock for the theoretic frequency that frequency is audio clock to be restored, further according to the read-write state of doubleclocking first in, first out module, the configuration parameter of loop divider is adjusted, so that the clock of the corresponding phaselocked loop output of configuration parameter adjusted meets the requirement that doubleclocking first in, first out module is in dynamic balance state.Due to during restored audio clock, the value of loop divider is only related with the sample rate of audio clock, and the value of prescalar can be configured by any way, is not need to rely on the relevant information of transmitting terminal transmission, such as the numerical value of N and CTS or Maud and Naud.Therefore, receiving end can be compatible with all transmitting terminals, improve the compatibility of receiving end using after restored audio clock scheme disclosed in the present application.
Description
Technical field
This application involves signal transmission technology fields, more specifically to the method and dress of a kind of restored audio clock
It sets.
Background technique
In some high speed signal interface agreements such as HDMI, MHL and DP agreement, audio data is packetized in link data
It is transmitted by link transmission, and by certain link rate, and in link does not include original audio sampling clock, in order to
The quality for guaranteeing audio signal playback, does not occur any loss of data and mistake, it is necessary to regenerate this sampling in receiving end
Clock, the process for generating this sampling clock is restored audio clock process.
The relevant information sent dependent on transmitting terminal is required in existing restored audio clock scheme, as HDMI, MHL are assisted
N and CTS in view, Maud and Naud in DP agreement.Receiving end utilizes the numerical value of N and CTS or Maud and Naud, configuration lock
The prescalar of phase ring and the value of loop divider.The relevant information accuracy and stability that transmitting terminal is sent can all influence
The restored audio clock of receiving end.And the relevant information that different transmitting terminal is sent in the market has different precision and stabilization
Property, so that the same receiving end is likely to or be difficult to be compatible with all transmitting terminals simultaneously.Therefore, it is sent dependent on transmitting terminal
Relevant information restored audio clock scheme, reduce the compatibility of receiving end.
Summary of the invention
In view of this, the method and apparatus that the application proposes a kind of restored audio clock, are intended to realize independent of transmitting terminal
The relevant information of transmission improves the purpose of the compatibility of receiving end.
To achieve the goals above, it is proposed that scheme it is as follows:
A kind of method of restored audio clock, comprising:
Receive the link data that transmitting terminal is sent；
Calculate the sample rate of the link data sound intermediate frequency data；
According to the sample rate calculate phaselocked loop loop divider configuration parameter so that phase-lock-ring output frequency be to
The clock of the theoretic frequency of the audio clock of recovery；
The loop divider is configured according to the configuration parameter；
Adjust the configuration parameter of the loop divider so that adjustment after loop divider the corresponding locking phase of configuration parameter
The clock of ring output meets the speed of the audio data write-in doubleclocking first in, first out module and first enters elder generation from the doubleclocking
Out module read out the audio data speed it is equal.
Preferably, the sample rate for calculating the link data sound intermediate frequency data, comprising:
The link data is parsed to obtain audio, video data and link clock；
Packets of audio data crawl is carried out to the audio, video data within a preset time；
The sample rate of audio data is calculated according to the packets of audio data number grabbed in the preset time.
Preferably, the configuration parameter of the loop divider that phaselocked loop is calculated according to the sample rate, comprising:
The theoretic frequency of audio clock to be restored is calculated according to the sample rate；
In conjunction with the theoretic frequency, clock frequency and the clock of phaselocked loop output of the voltage controlled oscillator of phaselocked loop
The reference clock frequency of multiple parameter and the phaselocked loop between frequency, is calculated the configuration of the loop divider
Parameter.
Preferably, the configuration parameter of the adjustment loop divider, comprising:
Compare the speed of audio data write-in doubleclocking first in, first out module with from the doubleclocking first in, first out mould
Block reads out the size of the speed of the audio data；
If the speed of the audio data write-in doubleclocking first in, first out module is greater than from the doubleclocking first in, first out mould
Block reads out the speed of the audio data, then increases the configuration parameter of the loop divider to improve the phaselocked loop output
Clock frequency；
If the speed of the audio data write-in doubleclocking first in, first out module is less than from the doubleclocking first in, first out mould
Block reads out the speed of the audio data, then reduces the configuration parameter of the loop divider to reduce the phaselocked loop output
Clock frequency.
A kind of device of restored audio clock, comprising:
Receiving module, for receiving the link data of transmitting terminal transmission；
First computing module, for calculating the sample rate of the link data sound intermediate frequency data；
Second computing module, the configuration parameter of the loop divider for calculating phaselocked loop according to the sample rate, so that
Phase-lock-ring output frequency is the clock of the theoretic frequency of audio clock to be restored；
First frequency module, for being configured according to the configuration parameter to the loop divider；
Frequency regulation block, for adjusting the configuration parameter of the loop divider, so that loop divider after adjustment
The clock of configuration parameter corresponding phaselocked loop output meet the speed of the audio data write-in doubleclocking first in, first out module with
The speed for reading out the audio data from the doubleclocking first in, first out module is equal.
Preferably, first computing module, comprising:
Resolution unit obtains audio, video data and the link clock for being parsed to the link data；
Data packet picking unit, for carrying out packets of audio data crawl to the audio, video data within a preset time；
First computing unit, for audio number to be calculated according to the packets of audio data number grabbed in the preset time
According to sample rate.
Preferably, second computing module includes:
Second computing unit, for calculating the theoretic frequency of audio clock to be restored according to the sample rate；
Third computing unit, for the voltage controlled oscillator in conjunction with the theoretic frequency, phaselocked loop clock frequency with it is described
The reference clock frequency of multiple parameter and the phaselocked loop between the frequency of the clock of phaselocked loop output, is calculated institute
State the configuration parameter of loop divider.
Preferably, the frequency regulation block, comprising:
Judging unit, for the audio data write-in doubleclocking first in, first out module speed with from it is described double when
Clock first in, first out module reads out the size of the speed of the audio data；
The first adjustment unit, if the speed for audio data write-in doubleclocking first in, first out module is greater than from described
Doubleclocking first in, first out module reads out the speed of the audio data, then increases the configuration parameter of the loop divider to mention
The frequency of the clock of the high phaselocked loop output；
Second adjustment unit, if the speed for audio data write-in doubleclocking first in, first out module is less than from described
Doubleclocking first in, first out module reads out the speed of the audio data, then reduces the configuration parameter of the loop divider to drop
The frequency of the clock of the low phaselocked loop output.
It can be seen from the above technical scheme that the method and apparatus of restored audio clock disclosed in the present application, first calculate
The sample rate of link data sound intermediate frequency data calculates the configuration parameter of phaselocked loop intermediate ring road frequency divider as a result, and to loop divide
Device is configured to obtain the clock for the theoretic frequency that frequency is audio clock to be restored, further according to doubleclocking first in, first out module
Read-write state, the configuration parameter of loop divider is adjusted, so that the configuration parameter of loop divider is corresponding after adjustment
Phaselocked loop output clock meet the requirement that doubleclocking first in, first out module is in dynamic balance state, i.e. writing speed is equal to
Reading speed.And when doubleclocking first in, first out module is in read-write equilibrium state, the clock of phaselocked loop output is after restoring
Audio clock, audio data is read out from doubleclocking first in, first out module by this audio clock, realizes the nothing of audio data
Damage is restored.
Since during restored audio clock, the value of loop divider is only related with the sample rate of audio data,
And the value of prescalar can be configured by any way, the restored audio clock for being not need to rely on transmitting terminal transmission needs
The relevant information wanted, such as the numerical value of N and CTS or Maud and Naud.Therefore, when receiving end uses audio disclosed in the present application
It after clock recovery scheme, is not influenced by the relevant information accuracy and stability that transmitting terminal is sent, it is possible to compatible transmission
Relevant information has the transmitting terminal of different precision and stability, and same receiving end is allowed to be compatible with all transmitting terminals,
Improve the compatibility of receiving end.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of flow chart of the method for restored audio clock disclosed in the present embodiment；
Fig. 2 is the flow chart of the method for another kind restored audio clock disclosed in the present embodiment；
Fig. 3 is the flow chart of the method for another kind restored audio clock disclosed in the present embodiment；
Fig. 4 is a kind of schematic diagram of the device of restored audio clock disclosed in the present embodiment；
Fig. 5 is the schematic diagram of the first computing module disclosed in the present embodiment；
Fig. 6 is the schematic diagram of the second computing module disclosed in the present embodiment；
Fig. 7 is the schematic diagram of frequency regulation block disclosed in the present embodiment.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
Now to this application involves noun explain, in order to the understanding to application scheme:
Phaselocked loop (Phase Locked Loop): phaselocked loop is the feedback system that output phase is compared with input phase
System, most basic function first is that clock frequency double frequency function.Its basic structure is by phase discriminator (PD, Phase Detector)
Or phase frequency detector (PFD, Phase Frequency Detector), loop filter (LF, Loop Filter), voltage-controlled vibration
It swings device (VCO, Voltage Controlled Oscillator) and loop divider (Loop Divider) is constituted.
Delta-Sigma decimal frequency-multiplication phase-locked loop (Delta Sigma Fractional N PLL): in basic phaselocked loop
Loop divider (Loop Divider) is changed to by program divider (Programmable Divider) on the basis of structure
It realizes, and is controlled by digital Delta-Sigma controller, the final phaselocked loop for realizing mixed decimal frequency multiplication.
VCO: the oscillator of output frequency can be changed by changing input voltage in voltage controlled oscillator.
Doubleclocking first in, first out module (Double Clock First In First Out, FIFO): write clock and reading
Take clock can be with different First Input First Output.
A kind of method that the present embodiment discloses restored audio clock, it is shown in Figure 1, this method comprises:
Step S11: the link data that transmitting terminal is sent is received；
The link data that transmitting terminal is sent is serial link data, therefore, carries out clock and data recovery and by serial number
According to being converted into parallel clock and data.
Step S12: the sample rate of link data sound intermediate frequency data is calculated；
Packets of audio data in link data is grabbed, the sample rate of link data sound intermediate frequency data is calculated.
Step S13: according to the sample rate for the audio data being calculated, the configuration ginseng of the loop divider of phaselocked loop is calculated
Number, so that phase-lock-ring output frequency is the clock of the theoretic frequency of audio clock to be restored；
According to the sample rate f of audio datasObtain the theoretic frequency of audio clock to be restored, such as f128fs=128*fs。
The configuration parameter of the loop divider of the frequency and phaselocked loop of the clock of phaselocked loop output is in a linear relationship, control loop frequency divider
Configuration parameter, that is, can determine phaselocked loop output clock frequency.Obtaining the theoretic frequency of audio clock to be restored
f128fs=128*fsAfterwards, the theoretic frequency f that phase-lock-ring output frequency is audio clock to be restored is calculated128fs=128*fsWhen
Zhong Shi, the corresponding configuration parameter of loop divider, the i.e. value of loop divider.And the value of prescalar can be by any
Mode configures, such as directly configures the numerical value of any fixation.
Step S14: loop divider is configured according to the loop divider configuration parameter being calculated；
Step S15: the configuration parameter of adjustment loop frequency divider, so that the configuration parameter of loop divider is corresponding after adjustment
The clock of phaselocked loop output meets the speed and audio data write-in pair that audio data is read out from doubleclocking first in, first out module
The equal requirement of the speed of clock first in, first out module.
Doubleclocking first in, first out module is written by link clock in audio data, audio data write-in doubleclocking first enters elder generation
The speed of module out, the frequency direct proportionality with link clock；And first entered by the clock that phaselocked loop exports from doubleclocking
First go out module and read out audio data, the speed of audio data is read out from doubleclocking first in, first out module, it is defeated with phaselocked loop
The frequency direct proportionality of clock out.According to matching for the read-write state adjustment loop frequency divider of doubleclocking first in, first out module
Parameter is set, and then realizes the adjustment of the frequency of the clock exported to phaselocked loop.The effect of doubleclocking first in, first out module be in order to
Guarantee that data will not malfunction in cross clock domain conversion process.When doubleclocking first in, first out module is in read-write equilibrium state,
Data in conversion process would not malfunction.And when doubleclocking first in, first out module is in read-write equilibrium state, phaselocked loop is defeated
Clock out, the audio clock after as restoring, reads out audio number from doubleclocking first in, first out module by this audio clock
According to realizing the Distortionless of audio data.
Restored audio clock method disclosed in the present application, the value of loop divider only have with the sample rate of audio data
It closes, the value of prescalar can be configured by any way, be not need to rely on the restored audio clock of transmitting terminal transmission
The relevant information needed, such as the numerical value of N and CTS or Maud and Naud.Therefore, receiving end uses audio disclosed in the present application
After clock recovery method, do not influenced by the relevant information accuracy and stability that transmitting terminal is sent, it is possible to compatible to send
Relevant information have the transmitting terminal of different precision and stability, allow same receiving end to be compatible with all transmissions
End, improves the compatibility of receiving end.
The method that the present embodiment discloses another restored audio clock, it is shown in Figure 2, wherein step S21, S25,
S26, S27 are consistent with step S11, S13, S14, S15 respectively, and details are not described herein.Step S22, step S23 and step S24 are
The refinement of step S12, specific as described below:
Step S22: link data is parsed to obtain audio, video data and link clock；
Step S23: packets of audio data crawl is carried out to audio, video data in preset time T；
Utilize the system clock or other clocks that receiving end frequency is fixed, timing regular hour T, in the preset time T
It is interior by the way that the packets of audio data in audio, video data is parsed and is grabbed.Calculate the clock and hair utilized during sample rate
The information that sending end is sent is unrelated, this ensure that the recovery process of receiving end audio clock, which needs not rely on transmitting terminal, sends audio
The relevant information that clock recovery needs.Therefore, receiving end can be compatible with using after restored audio clock method disclosed in the present application
All transmitting terminals improve the compatibility of receiving end.
Step S24: the sample rate of audio data is calculated according to the packets of audio data number G grabbed in preset time T
fs=G/T.
The method that the present embodiment discloses another restored audio clock, it is shown in Figure 3, wherein step S31, S32,
S35, S36 are consistent with step S11, S12, S14, S15 respectively, and details are not described herein.Step S33 and step S34 is step S13's
Refinement, specific as described below:
Step S33: according to sample rate fsCalculate the theoretic frequency of audio clock to be restored；
Step S34: in conjunction with the clock frequency and phaselocked loop of VCO in the theoretic frequency of audio clock to be restored, phaselocked loop
The reference clock frequency of multiple parameter and phaselocked loop between the frequency of the clock of output, is calculated loop divider
Configuration parameter.
According to the sample rate f of audio datas, calculate the theoretic frequency of audio clock to be restored, such as f128fs=128*
fs.And then obtain the clock frequency f of VCO in phaselocked loopvcoWith the reference clock frequency f of phaselocked looprBetween proportionality factor q=
fvco/fr=128*fs*N/fr, i.e. the configuration parameter of loop divider, wherein N is the clock frequency and locking phase of VCO in phaselocked loop
Multiple parameter N=f between the frequency of the clock of ring outputvco/f128fs, it is known quantity.The value of loop divider is matched
It postpones, the clock of phaselocked loop output is theoretic frequency f128fsAudio clock.
Specifically, the reference clock of phaselocked loop is crystal oscillator clock.Relative to using link clock as reference clock, by crystal oscillator
Clock has better clock performance as the reference clock of phaselocked loop, and the jitter performance of transmitting terminal will not influence sound to be restored
Frequency clock.Also, when selecting the biggish crystal oscillator clock of frequency, when such as selecting reference of the crystal oscillator clock of 27MHz as phaselocked loop
Zhong Shi, the loop bandwidth of phaselocked loop can choose 1MHz or so, i.e., higher bandwidth not only accelerates phaselocked loop tracking velocity,
Simultaneously as N and CTS is not utilized, alternatively, the value of Maud and Naud, so not needing the prescalar of larger area yet
And loop divider, therefore the area of phaselocked loop being substantially reduced, and then can be easy to integrate in the chip, reduction is produced into
This.
Specifically, the configuration parameter process of adjustment loop frequency divider, comprising: comparing audio data write-in doubleclocking first enters elder generation
The size of the speed of module and the speed that audio data is read out from doubleclocking first in, first out module out, if audio data write-in is double
The speed of clock first in, first out module is greater than the speed that audio data is read out from doubleclocking first in, first out module, then increases loop
The configuration parameter of frequency divider with improve phaselocked loop output clock frequency, if audio data be written doubleclocking first in, first out module
Speed be less than and read out the speed of audio data from doubleclocking first in, first out module, then reduce the configuration parameter of loop divider
To reduce the frequency of the clock of phaselocked loop output.The corresponding phaselocked loop output of the configuration parameter of loop divider after adjustment
The frequency of clock reads the speed of audio data write-in doubleclocking first in, first out module with from doubleclocking first in, first out module
Until the speed of audio data is equal out.
It should also be noted that, for the various method embodiments described above, for simple description, therefore, it is stated as a systems
The combination of actions of column, but those skilled in the art should understand that, the application is not limited by the described action sequence, because
For according to the application, some steps may be performed in other sequences or simultaneously.
The present embodiment discloses a kind of device of restored audio clock, shown in Figure 4, comprising:
Receiving module 101, for receiving the link data of transmitting terminal transmission；
First computing module 102, for calculating the sample rate of the link data sound intermediate frequency data；
Second computing module 103 calculates the loop point of phaselocked loop for the sample rate according to the audio data being calculated
The configuration parameter of frequency device, so that the frequency of the clock of phaselocked loop output is the theoretic frequency of audio clock to be restored；
First frequency module 104, for according to the configuration parameter of loop divider being calculated to loop divider into
Row configuration obtains the clock for the theoretic frequency that frequency is audio clock to be restored；
Frequency regulation block 105, for the configuration parameter of adjustment loop frequency divider, so that loop divider is matched after adjustment
The clock for setting the corresponding phaselocked loop output of parameter meets the speed and sound that audio data is read out from doubleclocking first in, first out module
The frequency requirement equal according to the speed of write-in doubleclocking first in, first out module.
The first computing module 102, shown in Figure 5 disclosed in the present embodiment, comprising:
Resolution unit 1021 obtains audio, video data and link clock for being parsed to link data；
Data packet picking unit 1022, for carrying out packets of audio data crawl to audio, video data within a preset time；
First computing unit 1023, for audio number to be calculated according to the packets of audio data number grabbed in preset time
According to sample rate.
The second computing module 103, shown in Figure 6 disclosed in the present embodiment, comprising:
Second computing unit 1031, when for calculating audio to be restored according to the sample rate for the audio data being calculated
The theoretic frequency of clock；
Third computing unit 1032, for combining the theoretic frequency of audio clock to be restored, in phaselocked loop VCO clock
The reference clock frequency of multiple parameter and phaselocked loop between frequency and the frequency of the clock of phaselocked loop output, is calculated
The configuration parameter of loop divider.
Frequency regulation block 105 disclosed in the present embodiment, it is shown in Figure 7, comprising:
Judging unit 1051, for comparing audio data write-in doubleclocking first in, first out module speed with from doubleclocking elder generation
Enter first to go out the size that module reads out the speed of audio data；
The first adjustment unit 1052, if for audio data write-in doubleclocking first in, first out module speed be greater than from it is double when
Clock first in, first out module reads out the speed of audio data, then increases the configuration parameter of loop divider to improve phaselocked loop output
Clock frequency；
Second adjustment unit 1053, if for audio data write-in doubleclocking first in, first out module speed be less than from it is double when
Clock first in, first out module reads out the speed of audio data, then reduces the configuration parameter of loop divider to reduce phaselocked loop output
Clock frequency.
For device embodiment, since it essentially corresponds to embodiment of the method, so related place is referring to method reality
Apply the part explanation of example.The apparatus embodiments described above are merely exemplary, wherein described be used as separation unit
The unit of explanation may or may not be physically separated, and component shown as a unit can be or can also be with
It is not physical unit.Some or all of the modules therein can be selected to realize this embodiment scheme according to the actual needs
Purpose.Those of ordinary skill in the art can understand and implement without creative efforts.
Herein, relational terms such as first and second and the like be used merely to by an entity or operation with it is another
One entity or operation distinguish, and without necessarily requiring or implying between these entities or operation, there are any this reality
Relationship or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to the packet of nonexcludability
Contain, so that the process, method, article or equipment for including a series of elements not only includes those elements, but also including
Other elements that are not explicitly listed, or further include for elements inherent to such a process, method, article, or device.
In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that including the element
Process, method, article or equipment in there is also other identical elements.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (8)
1. a kind of method of restored audio clock characterized by comprising
Receive the link data that transmitting terminal is sent；
Calculate the sample rate of the link data sound intermediate frequency data；
The configuration parameter of the loop divider of phaselocked loop is calculated according to the sample rate, so that phase-lock-ring output frequency is to be restored
Audio clock theoretic frequency clock, the reference clock of the phaselocked loop is crystal oscillator clock；
The loop divider is configured according to the configuration parameter；
The configuration parameter of the loop divider is adjusted, so that the corresponding phaselocked loop of configuration parameter of loop divider is defeated after adjustment
Clock out meet the speed of audio data write-in doubleclocking first in, first out module with from the doubleclocking first in, first out mould
The speed that block reads out the audio data is equal.
2. the method according to claim 1, wherein the sampling for calculating the link data sound intermediate frequency data
Rate, comprising:
The link data is parsed to obtain audio, video data and link clock；
Packets of audio data crawl is carried out to the audio, video data within a preset time；
The sample rate of audio data is calculated according to the packets of audio data number grabbed in the preset time.
3. the method according to claim 1, wherein the loop point for calculating phaselocked loop according to the sample rate
The configuration parameter of frequency device, comprising:
The theoretic frequency of audio clock to be restored is calculated according to the sample rate；
In conjunction with the frequency for the clock that the theoretic frequency, the clock frequency of the voltage controlled oscillator of phaselocked loop and the phaselocked loop export
Between multiple parameter and the phaselocked loop reference clock frequency, the configuration parameter of the loop divider is calculated.
4. the method according to claim 1, wherein the configuration parameter of the adjustment loop divider, packet
It includes:
The speed for comparing the audio data write-in doubleclocking first in, first out module is read with from the doubleclocking first in, first out module
Take out the size of the speed of the audio data；
It is read if the speed of the audio data write-in doubleclocking first in, first out module is greater than from the doubleclocking first in, first out module
Take out the speed of the audio data, then increase the configuration parameter of the loop divider with improve phaselocked loop output when
The frequency of clock；
It is read if the speed of the audio data write-in doubleclocking first in, first out module is less than from the doubleclocking first in, first out module
Take out the speed of the audio data, then reduce the configuration parameter of the loop divider with reduce phaselocked loop output when
The frequency of clock.
5. a kind of device of restored audio clock characterized by comprising
Receiving module, for receiving the link data of transmitting terminal transmission；
First computing module, for calculating the sample rate of the link data sound intermediate frequency data；
Second computing module, the configuration parameter of the loop divider for calculating phaselocked loop according to the sample rate, so that locking phase
Ring output frequency is the clock of the theoretic frequency of audio clock to be restored, and the reference clock of the phaselocked loop is crystal oscillator clock；
First frequency module, for being configured according to the configuration parameter to the loop divider；
Frequency regulation block, for adjusting the configuration parameter of the loop divider so that adjustment after loop divider configuration
The clock of parameter corresponding phaselocked loop output meet the speed of the audio data write-in doubleclocking first in, first out module with from institute
State doubleclocking first in, first out module read out the audio data speed it is equal.
6. device according to claim 5, which is characterized in that first computing module, comprising:
Resolution unit obtains audio, video data and the link clock for being parsed to the link data；
Data packet picking unit, for carrying out packets of audio data crawl to the audio, video data within a preset time；
First computing unit, for audio data to be calculated according to the packets of audio data number grabbed in the preset time
Sample rate.
7. device according to claim 5, which is characterized in that second computing module includes:
Second computing unit, for calculating the theoretic frequency of audio clock to be restored according to the sample rate；
Third computing unit, clock frequency and the locking phase for the voltage controlled oscillator in conjunction with the theoretic frequency, phaselocked loop
The reference clock frequency of multiple parameter and the phaselocked loop between the frequency of the clock of ring output, is calculated the ring
The configuration parameter of road frequency divider.
8. device according to claim 5, which is characterized in that the frequency regulation block, comprising:
Judging unit, for audio data write-in doubleclocking first in, first out module speed with it is first from the doubleclocking
Enter first to go out the size that module reads out the speed of the audio data；
The first adjustment unit, if for the audio data write-in doubleclocking first in, first out module speed be greater than from it is described double when
Clock first in, first out module reads out the speed of the audio data, then increases the configuration parameter of the loop divider to improve
State the frequency of the clock of phaselocked loop output；
Second adjustment unit, if for the audio data write-in doubleclocking first in, first out module speed be less than from it is described double when
Clock first in, first out module reads out the speed of the audio data, then reduces the configuration parameter of the loop divider to reduce
State the frequency of the clock of phaselocked loop output.
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| CN112116915A (en) * | 2019-06-19 | 2020-12-22 | 北京中版超级立体信息科技有限公司 | Digital audio signal decoder based on FPGA and decoding method |
| TWI841985B (en) * | 2022-06-20 | 2024-05-11 | 瑞昱半導體股份有限公司 | Electronic device and method for transmitting video data and audio data |
| CN115883493B (en) * | 2022-10-31 | 2024-07-09 | 中国船舶集团有限公司第七二三研究所 | Asynchronous data time sequence recovery method based on dynamic adjustment |
| CN116032453A (en) * | 2022-12-31 | 2023-04-28 | 青岛信芯微电子科技股份有限公司 | Audio clock recovery method, receiving terminal and device |
| CN116318516B (en) * | 2023-05-25 | 2023-08-15 | 芯动微电子科技(珠海)有限公司 | DP protocol-based dynamic accurate realization method and device for regenerated stream clock |
| CN116743158B (en) * | 2023-08-15 | 2023-11-07 | 慷智集成电路(上海)有限公司 | Method for extracting frequency phase of input signal and digital signal transmission system |
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