CN108055036B - Loop bandwidth adjusting method and device of clock data recovery circuit - Google Patents
Loop bandwidth adjusting method and device of clock data recovery circuit Download PDFInfo
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Abstract
The invention discloses a loop bandwidth adjusting method and a loop bandwidth adjusting device of a clock data recovery circuit. Wherein, the method comprises the following steps: generating an auxiliary clock of a sampling clock of the clock data recovery circuit, wherein the sampling clock is a clock for sampling data received by the clock data recovery circuit; according to the generated auxiliary clock, carrying out noise distribution statistics on the received data to obtain a noise statistical result; and adjusting the loop bandwidth of the clock data recovery circuit according to the obtained noise statistical result. The invention solves the technical problem of large adjustment workload caused by the fact that the loop bandwidth of the clock recovery circuit can not be adjusted independently.
Description
Technical Field
The invention relates to the technical field of data communication, in particular to a loop bandwidth adjusting method and device of a clock data recovery circuit.
Background
With the rapid development of science and technology, people's demands for information speed, information types and information capacity are increasing day by day, and the information transmission quantity and the information exchange quantity are increasing day by day. The optical fiber communication system becomes the main body of the information highway due to the advantages of large capacity, energy conservation, long transmission distance and the like. When transmitting data signals at high speed, the data stream is distorted and jittered by various external factors, such as noise, temperature variation, etc., during the transmission process to the receiving end through the transmission medium, so that the jitter accumulated during the transmission process needs to be eliminated at the receiving end by using a clock and data recovery circuit. The clock data recovery circuit has the main functions of recovering a clock signal from input non-return-to-zero random data and recovering data information by using the recovered clock signal and a transmitted data signal. The clock data recovery circuit is the main body of the optical fiber communication system, the performance of the clock data recovery circuit restricts the working performance of the whole optical fiber communication system, and the clock data recovery circuit is the main bottleneck for improving the speed of the optical fiber communication system.
In the related field, the binary phase-detecting clock data recovery circuit in high-speed serial data communication is widely applied, but the loop bandwidth of the binary phase-detecting clock data recovery circuit is easily affected by the noise of input data due to the nonlinearity of the binary phase detector, so that the working performance of the clock data recovery circuit is affected. In the related art, common solutions include, but are not limited to: 1. manually adjusting the gain of the loop filter and changing the bandwidth of the loop; 2. and the loop bandwidth is obtained through board-level chip testing, so that the adjustment of the loop bandwidth in the chip is guided. However, both methods have certain defects, and the method 1 is blind and cannot be automatically adjusted when the application environment is changed, and the method 2 has large test workload when being applied in a large scale.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a method and a device for adjusting loop bandwidth of a clock data recovery circuit, which at least solve the technical problem of large adjustment workload caused by the fact that the loop bandwidth of the clock recovery circuit cannot be adjusted independently.
According to an aspect of an embodiment of the present invention, there is provided a loop bandwidth adjusting method of a clock data recovery circuit, including: generating an auxiliary clock of a sampling clock of the clock data recovery circuit, wherein the sampling clock is a clock for sampling data received by the clock data recovery circuit; according to the generated auxiliary clock, carrying out noise distribution statistics on the received data to obtain a noise statistical result; and adjusting the loop bandwidth of the clock data recovery circuit according to the obtained noise statistical result.
Optionally, the generating the auxiliary clock of the sampling clock of the clock data recovery circuit includes: selecting a phase difference between the sampling clock and the auxiliary clock to be generated; and generating the auxiliary clock according to the selected phase difference and the sampling clock.
Optionally, performing noise distribution statistics on the received data according to the generated auxiliary clock, and obtaining a noise statistical result includes: acquiring data sampled according to the auxiliary clock; and counting the condition that the data sampled according to the auxiliary clock is abnormal data according to the phase relation between the auxiliary clock and the sampling clock to obtain the noise statistical result.
Optionally, the counting the data sampled by the auxiliary clock as abnormal data according to the phase relationship between the auxiliary clock and the sampling clock, and obtaining the noise statistical result includes: under the condition that the phase relation between the auxiliary clock and the sampling clock is that the phase of the auxiliary clock lags relative to the sampling clock, determining data sampled by the auxiliary clock and having a phase lead relative to the data received by the clock data recovery circuit as abnormal data, and counting the determined abnormal data to obtain the noise statistical result; and/or determining data sampled by the auxiliary clock and having a lagging phase relative to the data received by the clock data recovery circuit as the abnormal data under the condition that the phase relationship between the auxiliary clock and the sampling clock is that the phase of the auxiliary clock is ahead relative to the phase of the sampling clock, and counting the determined abnormal data to obtain the noise statistical result.
Optionally, adjusting the loop bandwidth of the clock data recovery circuit according to the obtained noise statistical result includes: determining the noise of the received data according to the obtained noise statistical result; determining a gain adjustment amount for adjusting a gain of a low-pass filter of the clock data recovery circuit according to the determined noise; and adjusting the loop bandwidth of the clock data recovery circuit by adopting the determined gain adjustment amount to adjust the gain of the low-pass filter.
According to another aspect of the embodiments of the present invention, there is also provided a loop bandwidth adjusting apparatus of a clock data recovery circuit, including: a generating module, configured to generate an auxiliary clock of a sampling clock of the clock data recovery circuit, where the sampling clock is a clock for sampling data received by the clock data recovery circuit; the statistic module is used for carrying out noise distribution statistics on the received data according to the generated auxiliary clock to obtain a noise statistic result; and the adjusting module is used for adjusting the loop bandwidth of the clock data recovery circuit according to the obtained noise statistical result.
Optionally, the generating module includes: a selection unit for selecting a phase difference between the sampling clock and the auxiliary clock to be generated; and the generating unit is used for generating the auxiliary clock according to the selected phase difference and the sampling clock.
Optionally, the statistical module includes: the acquisition unit is used for acquiring data sampled according to the auxiliary clock; and the statistical unit is used for carrying out statistics on the condition that the data sampled according to the auxiliary clock is abnormal data according to the phase relation between the auxiliary clock and the sampling clock so as to obtain the noise statistical result.
Optionally, the statistical unit includes: a first statistical subunit, configured to determine, when a phase relationship between the auxiliary clock and the sampling clock is that the auxiliary clock is delayed with respect to a phase of the sampling clock, data sampled by the auxiliary clock and having a phase advanced with respect to data received by the clock data recovery circuit as the abnormal data, perform statistics on the determined abnormal data, and obtain the noise statistical result; and/or the second statistical subunit is configured to, when the phase relationship between the auxiliary clock and the sampling clock is that the auxiliary clock is in phase advance with respect to the sampling clock, determine, as the abnormal data, data sampled by the auxiliary clock and having a phase lag with respect to data received by the clock data recovery circuit, perform statistics on the determined abnormal data, and obtain the noise statistical result.
Optionally, the adjusting module includes: the first determining unit is used for determining the noise of the received data according to the obtained noise statistical result; a second determining unit configured to determine a gain adjustment amount for adjusting a gain of a low-pass filter of the clock data recovery circuit according to the determined magnitude of the noise; and the adjusting unit is used for adjusting the loop bandwidth of the clock data recovery circuit by adopting the determined gain adjusting amount to adjust the gain of the low-pass filter.
According to another aspect of the embodiments of the present invention, there is provided a communication apparatus applied to the loop bandwidth adjusting method of the clock data recovery circuit described in any one of the above.
In the embodiment of the invention, the self-adaptive adjustment mode is adopted, the gain of the filter of the clock recovery circuit is self-adaptively adjusted through noise distribution statistics, and the loop bandwidth of the clock recovery circuit is further adjusted, so that the purpose that the loop bandwidth of the clock recovery circuit can be automatically changed along with the application environment is achieved, the technical effect of improving the noise tolerance of clock data is realized, and the technical problem of large adjustment workload caused by the fact that the loop bandwidth of the clock recovery circuit cannot be automatically adjusted is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a flow diagram of a method of loop bandwidth adjustment for a clock data recovery circuit according to an embodiment of the invention;
fig. 2 is a schematic diagram of a binary phase-discriminated clock data recovery circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of BBCDR loop bandwidth versus data noise according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an auxiliary clock generation circuit for a loop bandwidth adjustment method of a clock data recovery circuit according to an embodiment of the present invention;
fig. 5 is a basic principle of a binary phase detector of a clock data recovery circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a statistical distribution of noise in a clock data recovery circuit according to an embodiment of the present invention;
FIG. 7 is a block diagram of a loop bandwidth adjusting apparatus of a clock data recovery circuit according to an embodiment of the present invention;
fig. 8 is a block diagram of a loop bandwidth adjusting means generating block 72 of the clock data recovery circuit according to the embodiment of the present invention;
FIG. 9 is a block diagram of a loop bandwidth adjusting means statistics module 74 of the clock data recovery circuit according to an embodiment of the present invention;
FIG. 10 is a block diagram of a statistical unit 94 of the loop bandwidth adjusting means adjusting block 76 of the clock data recovery circuit according to an embodiment of the present invention;
FIG. 11 is a block diagram of the loop bandwidth adjusting means adjusting block 76 of the clock data recovery circuit according to an embodiment of the present invention;
FIG. 12 is a block diagram of an optimization system for a loop bandwidth adjustment system for a clock data recovery circuit constructed in accordance with an embodiment of the invention;
figure 13 is a schematic representation of the BBCDR loop bandwidth versus data noise relationship implemented in accordance with an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In accordance with an embodiment of the present invention, there is provided a method embodiment for loop bandwidth adjustment of a clock data recovery circuit, it is noted that the steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions and that, although a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than that presented herein.
Fig. 1 is a flowchart of a loop bandwidth adjusting method of a clock data recovery circuit according to an embodiment of the present invention, as shown in fig. 1, the method includes the following steps:
step S102, generating an auxiliary clock of a sampling clock of the clock data recovery circuit, wherein the sampling clock is a clock for sampling data received by the clock data recovery circuit;
step S104, according to the generated auxiliary clock, carrying out noise distribution statistics on the received data to obtain a noise statistical result;
and step S106, adjusting the loop bandwidth of the clock data recovery circuit according to the obtained noise statistical result.
Through the steps, the self-adaptive adjustment mode can be adopted, the gain of the filter of the clock recovery circuit is self-adaptively adjusted through noise distribution statistics, and then the loop bandwidth of the clock recovery circuit is adjusted, so that the purpose that the loop bandwidth of the clock recovery circuit can be automatically changed along with the application environment is achieved, the technical effect of improving the noise tolerance of clock data is achieved, and the technical problem of large adjustment workload caused by the fact that the loop bandwidth of the clock recovery circuit cannot be automatically adjusted is solved. Meanwhile, the embodiment of the invention can stop the self-adaptive adjustment after the bandwidth adjustment is finished once so as to save the power consumption.
In the field of data communication, a clock data recovery circuit is widely applied to a high-speed serial data communication circuit, and the performance of the clock data recovery circuit directly influences the error rate of received data. In the embodiment of the present invention, a binary phase-detecting clock data recovery circuit is taken as an example, the circuit is mainly applied to high-speed serial data communication, and fig. 2 is a schematic diagram of a binary phase-detecting clock data recovery circuit according to the embodiment of the present invention.
The non-linearity of the binary phase detector causes the loop bandwidth of the circuit to be affected by input data noise as shown by the open loop transfer function of the binary clock data recovery circuit as follows:
wherein the content of the first and second substances,
in order to flip the scale of the input data,
for the standard deviation of the noise of the input data,
proportional gain, τ, for clock data recovery circuitsNIntegrating the path time constant, T, for a clock data recovery circuitupLoop update period, N, for clock data recovery circuitdIs the loop delay time period of the clock data recovery circuit, and t(s) is the loop transfer function of the clock data recovery circuit.
Wherein
Is the standard deviation of the input data noise, the magnitude of which directly determines the loop bandwidth. The performance of the clock data recovery circuit is determined by three indexes of circuit jitter generation, jitter transmission and jitter tolerance, and the indexes are determined by the loop bandwidth of the clock data recovery circuit. Fig. 3 is a schematic diagram showing a relationship between a loop bandwidth and Data noise of a binary phase-detecting Clock Data Recovery circuit (BBCDR) according to an embodiment of the present invention, where as shown in fig. 3, the larger the noise amplitude is, the smaller the loop bandwidth of the Clock Data Recovery circuit is, and the larger the loop bandwidth of the Clock Data Recovery circuit is otherwise.
According to the embodiment of the invention, the gain of the low-pass filter in the clock data recovery circuit is adjusted according to the noise obtained by the statistical result by acquiring and counting the time sequence noise distribution of the input data, so that the purpose of adjusting the loop bandwidth of the clock data recovery circuit is achieved. And then the clock data recovery circuit realizes the phase locking of the input data and the sampling clock generated by the voltage-controlled oscillator so as to achieve the purpose of correctly sampling the input data at the receiving end.
Preferably, the auxiliary clock generating the sampling clock of the clock data recovery circuit includes: selecting a phase difference between a sampling clock and an auxiliary clock to be generated; an auxiliary clock is generated based on the selected phase difference and the sampling clock.
Fig. 4 is a schematic diagram of an auxiliary clock generation circuit of a loop bandwidth adjustment method of a clock data recovery circuit according to an embodiment of the present invention, which is implemented by a delay locked loop, a phase interpolator, a delay gate circuit, and the like.
Preferably, the performing noise distribution statistics on the received data according to the generated auxiliary clock, and obtaining a noise statistic result includes: acquiring data sampled according to an auxiliary clock; and according to the phase relation between the auxiliary clock and the sampling clock, counting the abnormal data sampled according to the auxiliary clock to obtain a noise statistical result.
Due to the influence relationship between the circuit loop bandwidth change and the input data noise, the embodiment of the invention realizes the bandwidth adjustment of the clock data recovery circuit by acquiring the data noise distribution. In the circuit adjusting process, after the sampling clock and the input data are locked in phase, when the input data is low in noise, namely the input data is relatively clean, and when the auxiliary clock phase is on the left side of the sampling clock, namely the auxiliary clock phase lags behind the data phase, the circuit cannot send an abnormal signal. When the input data is noisy, the probability that the circuit where the auxiliary clock sampling is located sends an abnormal signal becomes high because the input data is affected by the noise. By adjusting the phase selection control of the auxiliary phase generation circuit, the noise distribution statistics of the input data under different phase deviations can be realized, so that the noise of the input data is obtained. The filter gain of the clock data recovery circuit is adjusted through noise distribution statistics, and the purpose of loop bandwidth adjustment is achieved.
Preferably, the statistics on the abnormal data sampled according to the auxiliary clock according to the phase relationship between the auxiliary clock and the sampling clock, and the obtaining of the noise statistical result includes: under the condition that the phase relation between the auxiliary clock and the sampling clock is that the phase of the auxiliary clock lags relative to the sampling clock, determining data sampled according to the auxiliary clock and having a phase lead relative to the data received by the clock data recovery circuit as abnormal data, and counting the determined abnormal data to obtain a noise statistical result; and/or determining data sampled by the auxiliary clock and lagging in phase relative to the data received by the clock data recovery circuit as abnormal data under the condition that the phase relationship between the auxiliary clock and the sampling clock is that the phase of the auxiliary clock is ahead relative to the phase of the sampling clock, and counting the determined abnormal data to obtain a noise statistical result.
Fig. 5 is a basic principle of a binary phase detector of a clock data recovery circuit according to an embodiment of the present invention, as shown in fig. 5, when a falling edge of a sampling clock lags a data flip edge, the binary phase detector sends out a clock phase right shift signal, as shown in (1) in fig. 5; when the falling edge of the sampling clock leads the data flip edge, the binary phase discriminator sends out a clock phase left shift signal, as shown in (2) in fig. 5; when the falling edge of the sampling clock is aligned with the data turning edge, the clock data recovery circuit is locked, and the binary phase discriminator sends out clock phase left shift or right shift determined by input data noise and loop bandwidth.
Fig. 6 is a schematic diagram illustrating a statistical principle of noise distribution of the clock data recovery circuit according to the embodiment of the present invention. As shown in fig. 6, after the sampling clock is phase locked to the input data, the falling edge of the sampling clock is aligned with the inverting edge of the input data. The auxiliary clock in the figure is a leading or lagging phase clock of the sampling clock, the phase offset from the sampling clock being implemented by the auxiliary clock generating circuit. As shown in (1) of fig. 6, when the input data is low in noise, that is, the input data is relatively clean, and when the auxiliary clock phase is on the left side of the sampling clock, that is, the auxiliary clock phase lags behind the data phase, the binary phase detector controlled by the auxiliary clock always outputs a phase lag signal, but does not output a phase lead signal; when the auxiliary clock phase is to the right of the sampling clock, i.e., the auxiliary clock phase leads the data phase, the binary phase detector controlled by the auxiliary clock always outputs a phase lead signal, but does not output a phase lag signal. The counter counts only the issued exception signal, i.e. the phase lead signal when the auxiliary clock phase is to the left of the sampling clock and the phase lag phase when the auxiliary clock phase is to the right of the sampling clock.
Preferably, adjusting the loop bandwidth of the clock data recovery circuit according to the obtained noise statistics comprises: determining the noise of the received data according to the obtained noise statistical result; determining a gain adjustment amount for adjusting the gain of a low-pass filter of the clock data recovery circuit according to the determined noise; the loop bandwidth of the clock data recovery circuit is adjusted by adjusting the gain of the low-pass filter by the determined gain adjustment amount.
The embodiment of the invention realizes bandwidth adjustment by acquiring data noise distribution and adjusting the gain of a loop filter in a clock data recovery circuit. As shown in (2) in fig. 6, the input data is noisy, and even if the auxiliary clock leads or lags the sampling clock, the inversion edge of the input data is greatly deviated due to the influence of noise, so that the probability that the phase detector sampling by the auxiliary clock generates an abnormal signal becomes high. By adjusting the phase selection control of the auxiliary clock generation circuit, noise distribution statistics can be performed on input data under different phase deviations, so that the noise of the input data is obtained. The filter gain of the clock data recovery circuit is adjusted through noise distribution statistics, and the purpose of loop bandwidth adjustment is achieved.
According to another aspect of the embodiments of the present invention, there is further provided a loop bandwidth adjusting device of a clock data recovery circuit, fig. 7 is a block diagram of a loop bandwidth adjusting device of a clock data recovery circuit according to an embodiment of the present invention, and as shown in fig. 7, the loop bandwidth adjusting device of a clock data recovery circuit includes: a generation module 72, a statistics module 74, and an adjustment module 76. The loop bandwidth adjusting means of the clock data recovery circuit is explained in detail below.
A generating module 72, configured to generate an auxiliary clock of a sampling clock of the clock data recovery circuit, where the sampling clock is a clock for sampling data received by the clock data recovery circuit;
a statistic module 74, connected to the generating module 72, for performing noise distribution statistics on the received data according to the generated auxiliary clock to obtain a noise statistic result;
and an adjusting module 76, connected to the statistical module 74, for adjusting the loop bandwidth of the clock data recovery circuit according to the obtained noise statistics.
Fig. 8 is a block diagram of a loop bandwidth adjusting apparatus generating module 72 of the clock data recovery circuit according to the embodiment of the present invention, and as shown in fig. 8, the generating module 72 includes: the selection unit 82 and the generation unit 84 will be described below with reference to the generation module 72.
A selection unit 82 for selecting a phase difference between the sampling clock and the auxiliary clock to be generated;
and a generating unit 84, connected to the selecting unit 82, for generating an auxiliary clock according to the selected phase difference and the sampling clock.
Fig. 9 is a block diagram of a loop bandwidth adjusting apparatus statistic module 74 of the clock data recovery circuit according to the embodiment of the present invention, and as shown in fig. 9, the statistic module 74 includes: an acquisition unit 92 and a statistics unit 94, which statistics module 74 is explained below.
An obtaining unit 92 configured to obtain data sampled according to the auxiliary clock;
and a statistical unit 94, connected to the obtaining unit 92, for performing statistics on the abnormal data sampled according to the auxiliary clock according to the phase relationship between the auxiliary clock and the sampling clock, so as to obtain a noise statistical result.
Fig. 10 is a block diagram of a statistical unit 94 of the loop bandwidth adjusting device adjusting module 76 of the clock data recovery circuit according to the embodiment of the present invention, and as shown in fig. 10, the statistical unit 94 includes: the first statistics subunit 102 and/or the second statistics subunit 104, the statistics unit 94 is described below.
The first statistical subunit 102 is configured to, when the phase relationship between the auxiliary clock and the sampling clock is that the auxiliary clock is lagging with respect to the sampling clock, determine that data sampled according to the auxiliary clock is abnormal data with respect to data received by the clock data recovery circuit, perform statistics on the determined abnormal data, and obtain a noise statistical result; and/or the presence of a gas in the gas,
and a second statistical subunit 104, configured to determine, when the phase relationship between the auxiliary clock and the sampling clock is that the auxiliary clock is in phase advance with respect to the sampling clock, that data sampled by the auxiliary clock and having a phase lag with respect to data received by the clock data recovery circuit is abnormal data, perform statistics on the determined abnormal data, and obtain a noise statistical result.
Fig. 11 is a block diagram of a structure of a loop bandwidth adjusting means adjusting module 76 of the clock data recovery circuit according to the embodiment of the present invention, and as shown in fig. 11, the adjusting module 76 includes: a first determination unit 112, a second determination unit 114 and an adjustment unit 116, which adjustment module 76 is explained below.
A first determining unit 112, configured to determine a noise level of the received data according to the obtained noise statistic result;
a second determining unit 114, connected to the first determining unit 112, for determining a gain adjustment amount for adjusting the gain of the low-pass filter of the clock data recovery circuit according to the determined noise level;
and an adjusting unit 116, connected to the second determining unit 114, for adjusting the loop bandwidth of the clock data recovery circuit by adjusting the gain of the low-pass filter with the determined gain adjustment amount.
In an embodiment of the present invention, there is further provided a communication device, which is applied to the loop bandwidth adjusting method of the clock data recovery circuit described in any one of the above.
Fig. 12 is a diagram of an optimized system for a loop bandwidth adjusting system of a clock data recovery circuit according to an embodiment of the present invention, and as shown in fig. 12, the loop bandwidth adjusting system of the clock data recovery circuit includes: an amplifier or equalizer module 120, a clock data recovery circuit module 130, an auxiliary clock generation circuit module 140 (which functions as the generation module 72 described above), and a noise distribution statistics module 150. Wherein the clock data recovery circuit module 130 includes: a first binary phase detector 132 (functioning as the obtaining unit 92), a low-pass filter 134 (functioning as the second determining unit 114), a voltage-controlled oscillator or phase interpolator 136; the noise distribution statistical module 150 includes: a second binary phase detector 152 (functionally identical to the obtaining unit 92 described above), a counter 154 (functionally identical to the statistical unit 94 described above), and a noise distribution statistical unit 156 (functionally identical to the first determining unit 112 described above). A loop bandwidth adjusting system of the clock data recovery circuit is explained below.
And an amplifier or equalizer module 120 connected to the receive port for amplifying and compensating the received data. The module may include one or more stages of amplifier circuits, one or more stages of equalizer circuits, a combination of amplifier and equalizer circuits, or may not include the module in some applications.
And a clock data recovery circuit module 130, connected to the amplifier or equalizer module 120, for achieving phase locking between the input data and the sampling clock generated by the vco, so as to achieve the purpose of correctly sampling the input data at the receiving end. Wherein: the first binary phase discriminator 132 mainly utilizes the tracking and capturing functions of the phase-locked loop, and generates an error voltage control signal related to the phase difference and the frequency difference of the received data by comparing the phase and the frequency of the sampling clock and the received data; a low pass filter 134, connected to the first binary phase detector 132, and implemented by using an analog filter, a digital filter, or a combination of the two, for reducing input noise to the vco or the phase interpolator and stabilizing the frequency of the vco or the phase interpolator; a voltage controlled oscillator or phase interpolator 136, coupled to the low pass filter 134 and having its output as input to the auxiliary clock generation circuit block 140 and the first binary phase detector 132, may be replaced by an analog or digital phase interpolator for generating a circuit sampling clock, which is compared to the input data to generate a control voltage controlled oscillation frequency and phase.
An auxiliary clock generation circuit block 140 is coupled to the voltage controlled oscillator or phase interpolator 136 and the second binary phase detector 152 for generating an auxiliary clock. The input of the auxiliary clock generation circuit is the sampling clock generated by the voltage controlled oscillator or phase interpolator 136 and the output is the input of the second binary phase detector 152.
The noise distribution statistical module 150 is connected to the receiving port and the clock data recovery circuit module 130, and configured to perform noise distribution statistics on the input data under different phase deviations through changes of the auxiliary clock, to obtain noise of the input data, and then adjust the gain of the low-pass filter of the clock data recovery circuit module through the noise distribution statistics, so as to achieve the purpose of adjusting the loop bandwidth. Wherein: a second binary phase detector 152 for generating an error voltage control signal related to a phase difference and a frequency difference of the received data by comparing phases and frequencies of the auxiliary clock and the received data; a counter 154 connected to the second binary phase detector 152 for counting abnormal signals sent by the second binary phase detector 152, that is, counting phase-leading signals when the auxiliary clock phase is on the left side of the sampling clock, and counting phase-lagging signals when the auxiliary clock phase is on the right side of the sampling clock; and a noise distribution statistical unit 156 connected to the counter 154 and the low-pass filter 134, for performing noise distribution statistics on the input data under different phase deviations of the auxiliary clock and the sampling clock, so as to obtain the noise level of the input data.
As shown in fig. 12, the clock data recovery circuit module 120 achieves phase locking between the input data and the sampling clock generated by the voltage controlled oscillator, so as to achieve the purpose of correctly sampling the input data at the receiving end. The noise distribution statistical module realizes the acquisition and statistics of the time sequence noise distribution of the input data, and adjusts the gain of the low-pass filter in the clock data recovery circuit according to the noise obtained by changing the statistical result, thereby achieving the purpose of adjusting the loop bandwidth of the clock data recovery circuit. Fig. 13 is a schematic diagram of the relationship between the BBCDR loop bandwidth and the data noise implemented by the embodiment of the present invention. As shown in fig. 13, the effect after adaptive adjustment of the loop bandwidth is greatly improved compared with that of fig. 3.
By utilizing the embodiment of the invention, the noise distribution of the input data can be obtained, and the purpose of self-adaptive adjustment of the loop bandwidth is achieved. Meanwhile, the noise tolerance of clock data can be improved, and the self-adaptive adjusting module is closed after one-time bandwidth adjustment is finished so as to save power consumption.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (7)
1. A method for adjusting loop bandwidth of a clock data recovery circuit, comprising:
generating an auxiliary clock of a sampling clock of the clock data recovery circuit, wherein the sampling clock is a clock for sampling data received by the clock data recovery circuit;
according to the generated auxiliary clock, carrying out noise distribution statistics on the received data to obtain a noise statistical result;
adjusting the loop bandwidth of the clock data recovery circuit according to the obtained noise statistical result;
wherein, according to the generated auxiliary clock, performing noise distribution statistics on the received data, and obtaining a noise statistical result includes: acquiring data sampled according to the auxiliary clock; according to the phase relation between the auxiliary clock and the sampling clock, counting the condition that the data sampled according to the auxiliary clock is abnormal data to obtain the noise statistical result;
wherein, according to the phase relation between the auxiliary clock and the sampling clock, counting the data sampled according to the auxiliary clock as abnormal data, and obtaining the noise statistical result comprises: under the condition that the phase relation between the auxiliary clock and the sampling clock is that the phase of the auxiliary clock lags relative to the sampling clock, determining data sampled by the auxiliary clock and having a phase lead relative to the data received by the clock data recovery circuit as abnormal data, and counting the determined abnormal data to obtain the noise statistical result; and/or determining data sampled by the auxiliary clock and having a lagging phase relative to the data received by the clock data recovery circuit as the abnormal data under the condition that the phase relationship between the auxiliary clock and the sampling clock is that the phase of the auxiliary clock is ahead relative to the phase of the sampling clock, and counting the determined abnormal data to obtain the noise statistical result.
2. The method of claim 1, wherein generating the auxiliary clock of the sampling clock of the clock data recovery circuit comprises:
selecting a phase difference between the sampling clock and the auxiliary clock to be generated;
and generating the auxiliary clock according to the selected phase difference and the sampling clock.
3. The method of claim 1 or 2, wherein adjusting the loop bandwidth of the clock data recovery circuit in accordance with the obtained noise statistics comprises:
determining the noise of the received data according to the obtained noise statistical result;
determining a gain adjustment amount for adjusting a gain of a low-pass filter of the clock data recovery circuit according to the determined noise;
and adjusting the loop bandwidth of the clock data recovery circuit by adopting the determined gain adjustment amount to adjust the gain of the low-pass filter.
4. A loop bandwidth adjusting apparatus of a clock data recovery circuit, comprising:
a generating module, configured to generate an auxiliary clock of a sampling clock of the clock data recovery circuit, where the sampling clock is a clock for sampling data received by the clock data recovery circuit;
the statistic module is used for carrying out noise distribution statistics on the received data according to the generated auxiliary clock to obtain a noise statistic result;
the adjusting module is used for adjusting the loop bandwidth of the clock data recovery circuit according to the obtained noise statistical result;
wherein the statistics module comprises: the acquisition unit is used for acquiring data sampled according to the auxiliary clock; the statistical unit is used for carrying out statistics on the condition that the data sampled according to the auxiliary clock is abnormal data according to the phase relation between the auxiliary clock and the sampling clock so as to obtain the noise statistical result;
the statistical unit includes: a first statistical subunit, configured to determine, when a phase relationship between the auxiliary clock and the sampling clock is that the auxiliary clock is delayed with respect to a phase of the sampling clock, data sampled by the auxiliary clock and having a phase advanced with respect to data received by the clock data recovery circuit as the abnormal data, perform statistics on the determined abnormal data, and obtain the noise statistical result; and/or the second statistical subunit is configured to, when the phase relationship between the auxiliary clock and the sampling clock is that the auxiliary clock is in phase advance with respect to the sampling clock, determine, as the abnormal data, data sampled by the auxiliary clock and having a phase lag with respect to data received by the clock data recovery circuit, perform statistics on the determined abnormal data, and obtain the noise statistical result.
5. The apparatus of claim 4, wherein the generating module comprises:
a selection unit for selecting a phase difference between the sampling clock and the auxiliary clock to be generated;
and the generating unit is used for generating the auxiliary clock according to the selected phase difference and the sampling clock.
6. The apparatus of claim 4 or 5, wherein the adjustment module comprises:
the first determining unit is used for determining the noise of the received data according to the obtained noise statistical result;
a second determining unit configured to determine a gain adjustment amount for adjusting a gain of a low-pass filter of the clock data recovery circuit according to the determined magnitude of the noise;
and the adjusting unit is used for adjusting the loop bandwidth of the clock data recovery circuit by adopting the determined gain adjusting amount to adjust the gain of the low-pass filter.
7. A communication apparatus characterized in that the communication apparatus applies the loop bandwidth adjusting method of the clock data recovery circuit according to any one of claims 1 to 3.
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| CN112688701B (en) * | 2020-12-22 | 2022-05-31 | 北京奕斯伟计算技术有限公司 | Receiver circuit and receiver circuit control method |
| CN118018010A (en) * | 2024-04-08 | 2024-05-10 | 芯动微电子科技(武汉)有限公司 | Method and device for judging working stability of data clock recovery circuit |
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