CN112688701B - Receiver circuit and receiver circuit control method - Google Patents
Receiver circuit and receiver circuit control method Download PDFInfo
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- CN112688701B CN112688701B CN202011527021.0A CN202011527021A CN112688701B CN 112688701 B CN112688701 B CN 112688701B CN 202011527021 A CN202011527021 A CN 202011527021A CN 112688701 B CN112688701 B CN 112688701B
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- signal
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- frequency locking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/18—Input circuits, e.g. for coupling to an antenna or a transmission line
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
- H04L41/08—Configuration management of networks or network elements
- H04L41/0896—Bandwidth or capacity management, i.e. automatically increasing or decreasing capacities
Abstract
The invention provides a receiver circuit and a receiver circuit control method. The invention detects the input data through the detection circuit to obtain the data rate detection result, and automatically adjusts the bandwidth of the receiver according to the data rate detection result, thereby avoiding using chip pins or information packets of a time schedule controller to control the bandwidth of the receiver and realizing the optimization of the performance of the display driving chip.
Description
Technical Field
The present invention relates to the field of receiver devices, and in particular, to a receiver circuit and a receiver circuit control method.
Background
To support multiple types of application products, more and more display interface protocols cover a wide range of data rates. Receivers supporting a wide range of data rates need to support these display interface protocols. For power efficiency, the receiver needs to set different bandwidths according to the data rates of different input data, wherein the larger the required bandwidth, the larger the consumed current. In the receiver, an Analog Front-End (AFE) amplifies small signals from a channel into large signals to a Clock & Data Recovery (CDR). In general, there are two common ways to control the bandwidth of a receiver. One is through a chip PIN (PIN) control. The other is controlled by a way that a Timing Controller (TCON) sends a display driving chip information packet (Package). However, the PIN control method consumes additional chip PINs, and the Package control method is limited by TCON, which makes it difficult to optimize the performance of the display driver chip.
Disclosure of Invention
The invention provides a receiver circuit and a receiver circuit control method, which aim to solve the problem that the performance of a display driving chip is difficult to optimize due to the fact that a chip pin or a message packet of a time schedule controller is used for controlling the bandwidth of a receiver.
According to a first aspect of the invention, there is provided a receiver circuit comprising: an analog front end to output a first signal; the clock data recovery circuit is connected with the analog front end and is used for locking the frequency of the first signal and outputting a frequency locking signal; the detection circuit is respectively connected with the analog front end and the clock recovery circuit, and is used for carrying out data rate detection according to the frequency locking signal and outputting a bandwidth signal, a bias signal and a completion signal according to a data rate detection result; the bandwidth signal is used for adjusting the bandwidth of the clock data recovery circuit, the bias signal is used for adjusting the bandwidth of the analog front end, and the completion signal is used for controlling the clock data recovery circuit to lock the phase of the first signal.
In some embodiments, the detection circuit comprises: the first trigger is used for outputting a second signal according to a power supply voltage signal, the first signal and a frequency locking signal; the first logic gate outputs a third signal according to the second signal and an inverted signal; a timing circuit that outputs a fourth signal according to the third signal; a second flip-flop outputting the completion signal according to the power supply voltage signal, the fourth signal, and the frequency locking signal; an inverter outputting the inverted signal according to the completion signal; a second logic gate outputting a clock count signal according to the first signal, the second signal, and the inverted signal; and the counter outputs a count value according to the clock count signal and the frequency locking signal, and the count value is used for looking up a table to obtain the parameters of the bandwidth signal and the offset signal.
In some embodiments, the timing circuit comprises: the input end of the driving circuit is connected with the third signal; one end of the capacitor is connected with the output end of the driving circuit, and the other end of the capacitor is connected with a grounding signal; one end of the voltage source is connected with the grounding signal; and a first input end of the comparator is connected with the other end of the voltage source, and a second input end of the comparator is connected with the output end of the driving circuit.
In some embodiments, the driving circuit includes: one end of the current source is connected with the power supply voltage signal; the source stage of the first switch tube and the drain stage of the second switch tube are the output ends, the drain stage of the first switch tube is connected with the other end of the current source, and the source stage of the second switch tube is connected with a grounding signal.
In some embodiments, the first switch tube is a PMOS tube, and the second switch tube is an NMOS tube.
In some embodiments, when the third signal is at a first level, the first switch tube is turned on, the second switch tube is turned off, and the capacitor starts to charge; when the third signal is at a second level, the first switch tube is turned off, the second switch tube is turned on, and the capacitor starts to discharge.
In some embodiments, when the frequency locking signal is at a first level, the counter outputs a first count value, and the first count value is used for acquiring a bandwidth gear of the bandwidth signal; when the frequency locking signal is at the second level, the counter starts counting and outputs a counting value.
According to a second aspect of the present invention, there is provided a receiver circuit control method comprising: receiving a frequency locking signal output by a clock data recovery circuit; carrying out data rate detection according to the frequency locking signal; and outputting a bandwidth signal, an offset signal and a completion signal according to a data rate detection result, wherein the bandwidth signal is used for adjusting the bandwidth of the clock data recovery circuit, the offset signal is used for adjusting the bandwidth of the analog front end, and the completion signal is used for controlling the clock data recovery circuit to lock the phase of the first signal.
In some embodiments, the method further comprises: when the completion signal is at a second level, the circuit path of the detection circuit is cut off.
Compared with the prior art, the invention has the beneficial effects that: the input data is detected through the detection circuit to obtain a data rate detection result, and the bandwidth of the receiver is automatically adjusted according to the data rate detection result, so that the bandwidth of the receiver is prevented from being controlled by chip pins or an information packet of a time schedule controller, and the performance optimization of the display driving chip is realized.
Drawings
Fig. 1 is a schematic structural diagram of a receiver circuit according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a detection circuit according to an embodiment of the present invention.
Fig. 3 is a timing diagram of a receiver circuit according to an embodiment of the invention.
Fig. 4 is a flowchart illustrating steps of a method for controlling a receiver circuit according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides a receiver circuit, which includes an analog front end 11, a clock data recovery circuit 12, and a detection circuit 13.
The analog front end 11 is configured to output a first signal.
The clock data recovery circuit 12 is connected to the analog front end 11. The clock data recovery circuit 12 is configured to lock the frequency of the first signal and output a frequency locked signal.
The detection circuit 13 is connected to the analog front end 11 and the clock recovery circuit 12, respectively. The detection circuit 13 is configured to perform data rate detection according to the frequency locking signal, and output a bandwidth signal, an offset signal, and a completion signal according to a result of the data rate detection. The bandwidth signal is used to adjust the bandwidth of the clock data recovery circuit 12, the bias signal is used to adjust the bandwidth of the analog front end 11, and the completion signal is used to control the clock data recovery circuit 12 to lock the phase of the first signal. Resetting the detection circuit when the frequency locking signal is at a first level (low level); when the frequency locking signal is at a second level (high level), the detection circuit performs data rate detection.
Referring to fig. 2, an embodiment of the invention provides a detection circuit, including: a first flip-flop 21, a first logic gate 22, a timing circuit 23, a second flip-flop 24, an inverter 25, a second logic gate 26, and a counter 27.
The first flip-flop 21 is configured to output a second signal according to the power supply voltage signal, the first signal, and the frequency locking signal.
The first logic gate 22 outputs a third signal according to the second signal and an inverted signal.
The timing circuit 23 outputs a fourth signal based on the third signal.
Wherein, the timing circuit 23 includes: a driver circuit 231, a capacitor 232, a voltage source 233, and a comparator 234.
The input terminal of the driving circuit 231 is connected to the third signal. The drive circuit 231 includes: a current source 2311, a first switching tube 2312 and a second switching tube 2313. One end of the current source 231 is connected to the power supply voltage signal. The gates of the first switch tube 2312 and the second switch tube 2313 are the input ends, the source of the first switch tube 2312 and the drain of the second switch tube 2313 are the output ends, the drain of the first switch tube 2312 is connected with the other end of the current source 2311, and the source of the second switch tube 2313 is connected with a ground signal.
In some embodiments, the first switch 2312 is a PMOS transistor and the second switch 2313 is an NMOS transistor.
When the third signal is at a first level, the first switch tube is turned on, the second switch tube is turned off, and the capacitor starts to charge; when the third signal is at a second level, the first switch tube is turned off, the second switch tube is turned on, and the capacitor starts to discharge.
One end of the capacitor 232 is connected to the output end of the driving circuit 231, and the other end of the capacitor 232 is connected to the ground signal.
One end of the voltage source 233 is connected to the ground signal.
A first input terminal of the comparator 234 is connected to the other terminal of the voltage source 233, and a second input terminal of the comparator 234 is connected to the output terminal of the driving circuit 231.
The second flip-flop 24 outputs the completion signal according to the power supply voltage signal, the fourth signal, and the frequency locking signal.
The inverter 25 outputs the inverted signal according to the completion signal.
The second logic gate 26 outputs a clock count signal based on the first signal, the second signal, and the inverted signal.
The counter 27 outputs a count value according to the clock count signal and the frequency locking signal, and the count value is used for table lookup to obtain parameters of the bandwidth signal CDRBW and the offset signal RXBIAS. When the frequency locking signal is at a first level, the counter outputs a first count value, and the first count value is used for acquiring a bandwidth gear of the bandwidth signal; when the frequency locking signal is at the second level, the counter starts counting and outputs a counting value FREQ. Wherein, the values of the bandwidth signal RXBIAS and the bias signal CDRBW are obtained through LUT0 and LUT1 of a look-up table (LUT) circuit to realize the functions of table 1 below.
In the embodiment of the invention, when the frequency locking signal is at the first level (low level), the enable terminal EN of the COUNTER is at the low level, and the output value of the COUNTER is the maximum broadband gear of the broadband signal obtained by looking up the table to output the offset signal. When the frequency lock signal is at the second level (high level), the counter starts counting, increments the count value by 1 every time one clock signal period elapses, and outputs the last count value.
Referring to fig. 3, the present invention provides a timing diagram of a receiver circuit.
When the frequency locking signal FLOCK is at the first level (low level), the detection circuit is reset (V)INTIs pulled to VGND) RXBIAS is pulled to the maximum bandwidth gear to ensure that the maximum data rate can work properly.
When the frequency lock signal FLOCK is at the second level (high level), the counter starts counting. At the same time, the integrating capacitor (C)INT) Is referenced to the current (I)REF) Charging, integral voltage (V)INT) And starts to grow.
Once V isINTTo a reference voltage (V)REF) When the fourth signal output from the comparator 234 changes from low to high, the detection circuit ends its operation (the completion signal DRD _ DONE is pulled high), the counter stops counting, and the last value is kept output.
The value output by the counter is determined by the input frequency, and the values of RXBIAS and CDRBW can be set according to the corresponding information table established as shown in table 1.
| fDATA | tCK | K | RXBIAS | AFE bias current ratio |
| 2.0 | 5.00 | 100 | LL | 100％ |
| 1.6 | 6.25 | 80 | LH | 80％ |
| 1.2 | 8.33 | 60 | HL | 60％ |
| 0.8 | 12.5 | 40 | HH | 40％ |
TABLE 1
As shown in fig. 4, the present invention provides a receiver circuit control method including steps S41 through S43.
In step S41, the frequency lock signal output from the clock data recovery circuit is received.
And step S42, detecting the data rate according to the frequency locking signal.
Step S43, outputting a bandwidth signal, a bias signal and a completion signal according to a data rate detection result, where the bandwidth signal is used to adjust the bandwidth of the clock data recovery circuit, the bias signal is used to adjust the bandwidth of the analog front end, and the completion signal is used to control the clock data recovery circuit to lock the phase of the first signal.
In some embodiments, when the completion signal is at a second level, a circuit path of the detection circuit is cut off to save power consumption.
Besides the control of the values of the bias signal and the bandwidth signal, the detection circuit can also control circuit parameters related to the input data rate, such as power consumption, bias current of the voltage-controlled delay oscillator, locking time of CDR and the like.
The invention detects the input data through the detection circuit to obtain the data rate detection result, and automatically adjusts the bandwidth of the receiver according to the data rate detection result, thereby avoiding using chip pins or information packets of a time schedule controller to control the bandwidth of the receiver and realizing the optimization of the performance of the display driving chip.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above detailed description is provided for a receiver circuit and a receiver circuit control method according to the embodiments of the present invention, and a specific example is applied in the present disclosure to explain the principle and the implementation of the present invention, and the description of the above embodiments is only used to help understanding the technical solution and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A receiver circuit, comprising:
an analog front end to output a first signal;
the clock data recovery circuit is connected with the analog front end and is used for locking the frequency of the first signal and outputting a frequency locking signal;
the detection circuit is respectively connected with the analog front end and the clock data recovery circuit, and is used for carrying out data rate detection according to the frequency locking signal and outputting a bandwidth signal, a bias signal and a completion signal according to a data rate detection result;
the bandwidth signal is used for adjusting the bandwidth of the clock data recovery circuit, the bias signal is used for adjusting the bandwidth of the analog front end, and the completion signal is used for controlling the clock data recovery circuit to lock the phase of the first signal.
2. The receiver circuit of claim 1, wherein the detection circuit comprises:
the first trigger is used for outputting a second signal according to a power supply voltage signal, the first signal and a frequency locking signal;
the first logic gate outputs a third signal according to the second signal and an inverted signal;
a timing circuit that outputs a fourth signal according to the third signal;
a second flip-flop outputting the completion signal according to the power supply voltage signal, the fourth signal, and the frequency locking signal;
an inverter outputting the inverted signal according to the completion signal;
a second logic gate outputting a clock count signal according to the first signal, the second signal, and the inverted signal;
and the counter outputs a count value according to the clock count signal and the frequency locking signal, and the count value is used for looking up a table to obtain the parameters of the bandwidth signal and the offset signal.
3. The receiver circuit of claim 2, wherein the timing circuit comprises:
the input end of the driving circuit is connected with the third signal;
one end of the capacitor is connected with the output end of the driving circuit, and the other end of the capacitor is connected with a grounding signal;
one end of the voltage source is connected with the grounding signal;
and a first input end of the comparator is connected with the other end of the voltage source, and a second input end of the comparator is connected with the output end of the driving circuit.
4. The receiver circuit of claim 3, wherein the drive circuit comprises:
one end of the current source is connected with the power supply voltage signal;
the source stage of the first switch tube and the drain stage of the second switch tube are the output ends, the drain stage of the first switch tube is connected with the other end of the current source, and the source stage of the second switch tube is connected with a grounding signal.
5. The receiver circuit of claim 4, wherein the first switch transistor is a PMOS transistor and the second switch transistor is an NMOS transistor.
6. The receiver circuit of claim 4, comprising:
when the third signal is at a first level, the first switch tube is turned on, the second switch tube is turned off, and the capacitor starts to charge;
when the third signal is at a second level, the first switch tube is turned off, the second switch tube is turned on, and the capacitor starts to discharge.
7. The receiver circuit of claim 2, comprising:
when the frequency locking signal is at a first level, the counter outputs a first count value, and the first count value is used for acquiring a bandwidth gear of the bandwidth signal;
when the frequency locking signal is at the second level, the counter starts counting and outputs a counting value.
8. The receiver circuit of claim 1, comprising:
resetting the detection circuit when the frequency locking signal is at a first level;
when the frequency locking signal is at the second level, the detection circuit performs data rate detection.
9. A receiver circuit control method applied to the receiver circuit according to any one of claims 1 to 8, comprising:
receiving a frequency locking signal output by a clock data recovery circuit;
carrying out data rate detection according to the frequency locking signal;
and outputting a bandwidth signal, an offset signal and a completion signal according to a data rate detection result, wherein the bandwidth signal is used for adjusting the bandwidth of the clock data recovery circuit, the offset signal is used for adjusting the bandwidth of the analog front end, and the completion signal is used for controlling the clock data recovery circuit to lock the phase of the first signal.
10. The receiver circuit control method of claim 9, wherein the method further comprises:
when the completion signal is at a second level, the circuit path of the detection circuit is cut off.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011527021.0A CN112688701B (en) | 2020-12-22 | 2020-12-22 | Receiver circuit and receiver circuit control method |
| US18/003,724 US20230231590A1 (en) | 2020-12-22 | 2021-12-01 | Receiver Circuit and Receiver Circuit Control Method |
| PCT/CN2021/134776 WO2022135086A1 (en) | 2020-12-22 | 2021-12-01 | Receiver circuit and receiver circuit control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011527021.0A CN112688701B (en) | 2020-12-22 | 2020-12-22 | Receiver circuit and receiver circuit control method |
Publications (2)
| Publication Number | Publication Date |
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| CN112688701A CN112688701A (en) | 2021-04-20 |
| CN112688701B true CN112688701B (en) | 2022-05-31 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202011527021.0A Active CN112688701B (en) | 2020-12-22 | 2020-12-22 | Receiver circuit and receiver circuit control method |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20230231590A1 (en) |
| CN (1) | CN112688701B (en) |
| WO (1) | WO2022135086A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112688701B (en) * | 2020-12-22 | 2022-05-31 | 北京奕斯伟计算技术有限公司 | Receiver circuit and receiver circuit control method |
| CN114220380B (en) * | 2022-02-22 | 2022-06-10 | 深圳通锐微电子技术有限公司 | Calibration digital circuit, source driver and display panel |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4771249A (en) * | 1987-05-26 | 1988-09-13 | Motorola, Inc. | Phase locked loop having a filter with controlled variable bandwidth |
| CA2050892A1 (en) * | 1989-06-26 | 1990-12-27 | Robert J. Schwendeman | Receiver with variable predetection bandwidth based on expected data rate |
| CN1075691C (en) * | 1994-06-10 | 2001-11-28 | Ntt移动通信网株式会社 | Receiver |
| US6285722B1 (en) * | 1997-12-05 | 2001-09-04 | Telcordia Technologies, Inc. | Method and apparatus for variable bit rate clock recovery |
| US6631144B1 (en) * | 1999-12-21 | 2003-10-07 | Intel Corporation | Multi-rate transponder system and chip set |
| US7822113B2 (en) * | 2003-12-19 | 2010-10-26 | Broadcom Corporation | Integrated decision feedback equalizer and clock and data recovery |
| US8798223B2 (en) * | 2010-12-23 | 2014-08-05 | Ashish K. Choudhury | Clock and data recovery unit without an external reference clock |
| KR101918627B1 (en) * | 2012-04-04 | 2018-11-15 | 삼성전자 주식회사 | Data receiver device and testing method thereof |
| CN103427830B (en) * | 2013-08-08 | 2016-02-03 | 南京邮电大学 | A kind of half-blindness type over-sampling clock data recovery circuit with high lock-in range |
| US9294260B2 (en) * | 2013-12-27 | 2016-03-22 | Intel Corporation | Phase adjustment circuit for clock and data recovery circuit |
| US9923564B2 (en) * | 2015-11-17 | 2018-03-20 | Mediatek Inc. | Clock data recovery apparatus and method capable of reducing more noise as well as tracking larger frequency offsets |
| US10567069B2 (en) * | 2016-04-28 | 2020-02-18 | Netgear, Inc. | Repeater bandwidth, radio configuration, and ADC clock speed adjustment |
| CN108055036B (en) * | 2017-10-31 | 2020-12-29 | 北京集创北方科技股份有限公司 | Loop bandwidth adjusting method and device of clock data recovery circuit |
| CN209390099U (en) * | 2019-03-08 | 2019-09-13 | 北京集创北方科技股份有限公司 | Detection circuit and clock data recovery circuit |
| US10728015B1 (en) * | 2019-06-06 | 2020-07-28 | Qualcomm Incorporated | Adaptive phase-locked loop bandwidth control |
| CN112688701B (en) * | 2020-12-22 | 2022-05-31 | 北京奕斯伟计算技术有限公司 | Receiver circuit and receiver circuit control method |
-
2020
- 2020-12-22 CN CN202011527021.0A patent/CN112688701B/en active Active
-
2021
- 2021-12-01 US US18/003,724 patent/US20230231590A1/en active Pending
- 2021-12-01 WO PCT/CN2021/134776 patent/WO2022135086A1/en unknown
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| Publication number | Publication date |
|---|---|
| WO2022135086A1 (en) | 2022-06-30 |
| CN112688701A (en) | 2021-04-20 |
| US20230231590A1 (en) | 2023-07-20 |
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Address after: 100176 no.2179, 2 / F, building D, 33, 99 Kechuang 14th Street, Beijing Economic and Technological Development Zone, Beijing (centralized office area) Patentee after: Beijing yisiwei Computing Technology Co.,Ltd. Patentee after: HEFEI YISIWEI INTEGRATED CIRCUIT Co.,Ltd. Address before: 100176 no.2179, 2 / F, building D, 33, 99 Kechuang 14th Street, Beijing Economic and Technological Development Zone, Beijing (centralized office area) Patentee before: Beijing yisiwei Computing Technology Co.,Ltd. Patentee before: HEFEI YISIWEI INTEGRATED CIRCUIT Co.,Ltd. |
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Address after: 100176 no.2179, 2 / F, building D, 33, 99 Kechuang 14th Street, Beijing Economic and Technological Development Zone, Beijing (centralized office area) Patentee after: Beijing yisiwei Computing Technology Co.,Ltd. Patentee after: Hefei Yisiwei Computing Technology Co.,Ltd. Address before: 100176 no.2179, 2 / F, building D, 33, 99 Kechuang 14th Street, Beijing Economic and Technological Development Zone, Beijing (centralized office area) Patentee before: Beijing yisiwei Computing Technology Co.,Ltd. Patentee before: HEFEI YISIWEI INTEGRATED CIRCUIT Co.,Ltd. |