CA2050892A1 - Receiver with variable predetection bandwidth based on expected data rate - Google Patents
Receiver with variable predetection bandwidth based on expected data rateInfo
- Publication number
- CA2050892A1 CA2050892A1 CA002050892A CA2050892A CA2050892A1 CA 2050892 A1 CA2050892 A1 CA 2050892A1 CA 002050892 A CA002050892 A CA 002050892A CA 2050892 A CA2050892 A CA 2050892A CA 2050892 A1 CA2050892 A1 CA 2050892A1
- Authority
- CA
- Canada
- Prior art keywords
- receiver
- bandwidth
- signal
- filter
- bit rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W8/00—Network data management
- H04W8/22—Processing or transfer of terminal data, e.g. status or physical capabilities
- H04W8/24—Transfer of terminal data
- H04W8/245—Transfer of terminal data from a network towards a terminal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/1638—Special circuits to enhance selectivity of receivers not otherwise provided for
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
- H04W88/02—Terminal devices
- H04W88/022—Selective call receivers
Abstract
This invention relates to selective call receivers (11), such as paging receivers, for receiving modulated data signals having a variable bit rate. A band pass filter (26), particularly an I. F.
filter, is provided having an adjustable bandwidth. The bandwidth of the filter is adjusted in accordance with a code in the received signal which indicates the bit rate.
filter, is provided having an adjustable bandwidth. The bandwidth of the filter is adjusted in accordance with a code in the received signal which indicates the bit rate.
Description
~ ~9l/00655 PCT/US90/02679 `` 2 ~ 2 ~eeeiver With Varia~l~ predetectiQn-Ban~wi~h Based on Expe~t~ a Rate sackground of the Iny~n~lQ~
This inventlon relates to selective call receivers, such as paging receivers, employing variable data rates.
Current paging receivers operate on a variety of signaling code formats that can all be detected using a 10 consistent (fixed) IF bandwidth. Examples of existing code ;`
formats and their respective bit rates in bits per second (BPS) are:
Motorola GSC: 300 BPS Address /600 BPS Message POCSAG: 512 BPS
POCSAG: 1200 BPS
NEC D2, D3: 200 BPS
NEC D9: 512 BPS
, .
It is within the performance capability of today's receivers and transmitters to achieve consistent system sensitivity at these low bit rates.
In order to achieve higher throughput of information, it is advantageous to use higher bit rates, for example 2400, 4800, and conceivably 9600 BPS. However, it would be j desirable to provide a pager which could operate on ~` -existing paging systems, e.g. at 1200 BPS and could also operate at higher bit rates to give increased capacity ror 30 future system expansion. With the higher bit rate system ~-operation there is a need to compensate for the loss in energy per bit by adding additional transmitters. These added transmitters fill in the coverage areas where the received signal is inadequate for acceptable higher bit ~5 rate operation. In this way, by adding further transmitters and increasing the bit rate, the capacity of the overall system can be increased substantially. In changing from 1200 to 4800 BPS, only an additional 6db of :.
. :.:: .: : : : , ::
.: , .. ~ : -: - ~ :
. .
WV91/0~655 2 o ~ 2 2 P~/US90~0267 signal is required to compensate for this loss whereas the throughput capacity is quadrupled. In addition, it would also be desirable to provide a paging system with the capability of paging different pagers at different bit rates, because greater range is achievable with lower bit rates. In order to achieve optimum range, for each system operation however, it is important to optimize the band width of the IF filter. The narrow bandwidth IF filter required at the lower bit rates would be unsuitable for the higher bit rates.
U. S. Patent 4,642,632 describes a paging system in which an address code is transmitted at a lower transmission rate than the message code. The receiver includes a low pass filter which Pilters the signal at the post-detection stage, immediately prior to the bit slicer.
The low pass filter has a cut-off frequency 5witchable between the reception rate for the address and the reception rate ~or the mes~age~ This .L9 don~ to maxirn.tze the paging code reception pro~babillties at both data rates.
According to the invention, there is provided a selective call receiver and system and a method of 25 operation thereof. The receiver comprises means for ~
receiving a modulated data signal having a variable bit -:
rate and including a code indicative of the bit rate; a demodulator; a bandpass filter for filtering the signal prior to demodulation in the-de~odulator, the bandpass filter having an adjustable bandwidth; and means for adjusting the bandwidth of the bandpass filter in response to the code received.
By this means, the bandwidth of the filter can be selected according to the bit rate of the receiv~d signal, as indicated by the code lncluded in the signal. In this way, a signal ha~ing a low blt rate can be filtered through a narrow bandwidth filter, thereby giving a good signal-to-09l/0~5; PCT/USgO/Q2679 noise ratio, while a higher bit rate requiring a widerbandwidth to prevent intersymbol interference can be filtered through a wider bandwidth filter.
The invention results in improved overall performance.
A preferred embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings.
Figure 1 shows a paging system having a transmitter -and a receiver, in accordance with the invention.
Figure 2 shows the format of the slgnal transmitted by the transmitter of Figure l.
Flgure 3 show9 the pre~etection ~llter o~ ~h~ receiver o F Figure 1.
Deta:lled DesoriDtlon Q~ the Tnv~n~,ion Referring to Figure 1, there is shown a paging transmitter lC and a paging receiver 11. The transmitter 10 comprises a paging system controller 15 and one or more transmitters 17. The receiver 11 comprises an RF amplifier 20, a first mixer 21, a first IF amplifier 22 and a second mixer 23. First and second oscillators 24 and 25 provide signals to the first and second mixers 21 and 23 respectively. The first: oscillator-24 is crystal controlled. A variable IF bandwidth filter is shown generally at 26, receiving an IF signal from second mixer 23 and passing the filtered signal to a demodulator 27. A
microprocessor 28 is shown, with control lines connected to the second mixer 23, the oscillators 24 and 25 and the filter 26.
In operation, the transmitter 10 transmits a signal having the format shown in Figure 2. On this figure, there . . :
.. ..
W091/00655 PCT/US90/026~1~
This inventlon relates to selective call receivers, such as paging receivers, employing variable data rates.
Current paging receivers operate on a variety of signaling code formats that can all be detected using a 10 consistent (fixed) IF bandwidth. Examples of existing code ;`
formats and their respective bit rates in bits per second (BPS) are:
Motorola GSC: 300 BPS Address /600 BPS Message POCSAG: 512 BPS
POCSAG: 1200 BPS
NEC D2, D3: 200 BPS
NEC D9: 512 BPS
, .
It is within the performance capability of today's receivers and transmitters to achieve consistent system sensitivity at these low bit rates.
In order to achieve higher throughput of information, it is advantageous to use higher bit rates, for example 2400, 4800, and conceivably 9600 BPS. However, it would be j desirable to provide a pager which could operate on ~` -existing paging systems, e.g. at 1200 BPS and could also operate at higher bit rates to give increased capacity ror 30 future system expansion. With the higher bit rate system ~-operation there is a need to compensate for the loss in energy per bit by adding additional transmitters. These added transmitters fill in the coverage areas where the received signal is inadequate for acceptable higher bit ~5 rate operation. In this way, by adding further transmitters and increasing the bit rate, the capacity of the overall system can be increased substantially. In changing from 1200 to 4800 BPS, only an additional 6db of :.
. :.:: .: : : : , ::
.: , .. ~ : -: - ~ :
. .
WV91/0~655 2 o ~ 2 2 P~/US90~0267 signal is required to compensate for this loss whereas the throughput capacity is quadrupled. In addition, it would also be desirable to provide a paging system with the capability of paging different pagers at different bit rates, because greater range is achievable with lower bit rates. In order to achieve optimum range, for each system operation however, it is important to optimize the band width of the IF filter. The narrow bandwidth IF filter required at the lower bit rates would be unsuitable for the higher bit rates.
U. S. Patent 4,642,632 describes a paging system in which an address code is transmitted at a lower transmission rate than the message code. The receiver includes a low pass filter which Pilters the signal at the post-detection stage, immediately prior to the bit slicer.
The low pass filter has a cut-off frequency 5witchable between the reception rate for the address and the reception rate ~or the mes~age~ This .L9 don~ to maxirn.tze the paging code reception pro~babillties at both data rates.
According to the invention, there is provided a selective call receiver and system and a method of 25 operation thereof. The receiver comprises means for ~
receiving a modulated data signal having a variable bit -:
rate and including a code indicative of the bit rate; a demodulator; a bandpass filter for filtering the signal prior to demodulation in the-de~odulator, the bandpass filter having an adjustable bandwidth; and means for adjusting the bandwidth of the bandpass filter in response to the code received.
By this means, the bandwidth of the filter can be selected according to the bit rate of the receiv~d signal, as indicated by the code lncluded in the signal. In this way, a signal ha~ing a low blt rate can be filtered through a narrow bandwidth filter, thereby giving a good signal-to-09l/0~5; PCT/USgO/Q2679 noise ratio, while a higher bit rate requiring a widerbandwidth to prevent intersymbol interference can be filtered through a wider bandwidth filter.
The invention results in improved overall performance.
A preferred embodiment of the invention will now be described, by way of example, with reference to the accompanying drawings.
Figure 1 shows a paging system having a transmitter -and a receiver, in accordance with the invention.
Figure 2 shows the format of the slgnal transmitted by the transmitter of Figure l.
Flgure 3 show9 the pre~etection ~llter o~ ~h~ receiver o F Figure 1.
Deta:lled DesoriDtlon Q~ the Tnv~n~,ion Referring to Figure 1, there is shown a paging transmitter lC and a paging receiver 11. The transmitter 10 comprises a paging system controller 15 and one or more transmitters 17. The receiver 11 comprises an RF amplifier 20, a first mixer 21, a first IF amplifier 22 and a second mixer 23. First and second oscillators 24 and 25 provide signals to the first and second mixers 21 and 23 respectively. The first: oscillator-24 is crystal controlled. A variable IF bandwidth filter is shown generally at 26, receiving an IF signal from second mixer 23 and passing the filtered signal to a demodulator 27. A
microprocessor 28 is shown, with control lines connected to the second mixer 23, the oscillators 24 and 25 and the filter 26.
In operation, the transmitter 10 transmits a signal having the format shown in Figure 2. On this figure, there . . :
.. ..
W091/00655 PCT/US90/026~1~
2 ~ 4 ~7 is shown line 30 which illustrates on a small scale the structure of a complete frame of page data. The frame comprises a sync portion 31 followed by page data 32. The page data portion 32 may contain addresses and data for paging receivers. Together the blocks 31 and 32 comprise a single frame of page data. At the end of this frame, another frame begins, i.e. the sequence of sync portion and frame portion repeats itself.
At the bottom of Figure 2, sync portion 31 is shown in a larger scale, from which it can be seen that portion of the frame comprises a settling signal A, bit/word sync signal B, and a frame information signal C.
Settling signal A includes at least 24 bits which provldes time ~or receiver stabilization. The 24 hits may cons~st of an alternating "1" "0" pattern. The bit/word sync signal B, may consist o~ a 32 bit predetermined pa~tern which provides for bit ~nchroni~iation and frame synchronization. The frame lnformation signal C comprises a 32 bit code word which is structured as a 31,21 BCH code word with one additional bit of parity. Thus, the frame information signal C has 21 information bits which may be made up as follows:
6 BITS -- FRAME NUMBER (00-63) .-3 BITS - FRAME SPEED (600,1200, 2400, 4800, 9600,19.2K, 38 . 4K, X) 12. BITS. -- SPARES: :
It can be seen that the frame information signal includes a signal which indicates the frame speed. This signal is comprised within three bits which are capable of indicating 8 speeds, these being 600, 1200, 2400, 4800, 9600, 19.2Y and 38.4IC, wlth capaclty for one ~urther speedi.
In the remainder of the description which follows, the case will be described where only the speeds 1200, 2400 and 4800 BPS are used.
.
~091/00655 ` PCT/U~90/02679 8 ~ 2 The system operates as follows. The transmitter puts together the sync portion of the frame in controller 15;
Depending on the volume of traffic and~or other factors, the controller 15 will determine the three bits within frame information signal which indicate the fxame speed.
The transmitter 17 transmits the sync portion 31 of the frame at a predetermined speed of 1200 bits per second.
Corresponding to the beginning of the first block of :~::
portion 32, the transmitter 17 switches to the bit rate of the frame, for example 2400 BPS, and the remainder of the frame 32 is transmitted at the higher bit rate.
The receiver 11 receives this signal, which is amplified in amplifier 20, mixed down to an IF frequency by mixer 21 and oscillator 29, ampli~ied in amplifl.~r 22, further mixed down in the frequency by mixer 23 and oscillator 25, and then filtered by Eilt~r 26. Th~
~iltered signal ~rom f:Llter 26 i9 demodulated at 1200 BPS
in demodulator 27, and the bit stream derived ~rom the signal is fed to microprocessor 28. On receipt of the frame info code word D or E, microprocessor 28 identifies the bit rate of the ~orthcoming ~rame, whereupon it adjusts the bandwidth of IF filter 26 via control line 29. In 25 response to a signal from control line 29, filter 26 ;
changes its bandwidth. In the present case, with the forthcoming frame bit rate determined as 2400 BPS, and the ;~
rate of the sync portion being 1200 BPS the filter 26 switches from the na~row bandwidth 26a to the intermediate bandwidth 26b. This is necessary because the narrow bandwidth, while giving better signal-to-noise at 1200 BPS, is too narrow for a 2900 BPS signal. One possible manner in which this change is implemented is illustrated in Figure 3.
Referring to that figure~ three ceramic ~ilters are shown 40, 41 and 42. Filter 40 has a typical bandwidth of 5.5 KHz ~ or - 10%. Filter 41 has a typical bandwidth of WO91/0~65~ 2 0 ~ ~ ~ 9 2 PCT/US90/0267~
8.25 KHz + or - 10% and filter 92 has a typical bandwidth of 11 KHz + or - 10~. A CMOS analog switch 43 is provided of the type MC14066B. The filter circuits 26 receives inputs from the second mixer 23 and provide the inputs to the filters 90,41 and 42. There is a three-bit control line 29 from the microprocessor 28 to the switch 93. The outputs of the filters 90, 41 and 42 are connected to an IF
amplifier 45, which is connected to the demodulator 27.
The filter operates as ~ollow5. On receipt of the frame speed code (1200 BPS), the microcomputer 28 provides a signal on control line 29 which operates analog switch 43 to remain connected to IF amp 45 from filter 40 for continued 1200 BPS operation. In this instance filters 41 and 42 are isolated from the IF amp 95.
If the frame 5peed i~ to be changed ~rom 1200 BPS to 4800 BPS, the microcomputer 28 rec~lves the appropriate ~rame speed code, and causes the switch 43 to dlsconnect filter 40 and connect the IF arnp ~5 to the ~ilter 42. In this instance, filters 40 and 41 are isolated from the circuit.
The demodulator 27 acts as a frequency discriminator, and the possible choices could be: at the bit rate of 1200, the high and low bit frequencies are at the carrier frequency + or -2.2KHz, at the bit rate of 2400 BPS, the frequencies are carrier + or -3.8 KHz. At 4800 BPS, the : ~requencies-are carrier ~ or -4.5 KHz.
:: 30 It should be understood that there may be numerous other ways of implementing the invention, particularly in implementing the variable bandwidth filter 26. It will also be appreciated that the filter 26, may be capable of providing two ~andwidths only, or more than three bandwidths, and for example wider bandwidths may be provided for higher bit rates such as 9600 BPS, 19.2 K and 38.4 K. It should be further appreciated that the receiver ~ O91/0065~ PCT/US90/02679 7 . : 2 ~
of the present invention may alternately be constructed ~ -with a single intermediate frequency, thereby eliminating ~:
elements 22, 23 and 25 from Figure 1. Alternately, more than two intermediate frequencies may be used.
What is claimed is:
At the bottom of Figure 2, sync portion 31 is shown in a larger scale, from which it can be seen that portion of the frame comprises a settling signal A, bit/word sync signal B, and a frame information signal C.
Settling signal A includes at least 24 bits which provldes time ~or receiver stabilization. The 24 hits may cons~st of an alternating "1" "0" pattern. The bit/word sync signal B, may consist o~ a 32 bit predetermined pa~tern which provides for bit ~nchroni~iation and frame synchronization. The frame lnformation signal C comprises a 32 bit code word which is structured as a 31,21 BCH code word with one additional bit of parity. Thus, the frame information signal C has 21 information bits which may be made up as follows:
6 BITS -- FRAME NUMBER (00-63) .-3 BITS - FRAME SPEED (600,1200, 2400, 4800, 9600,19.2K, 38 . 4K, X) 12. BITS. -- SPARES: :
It can be seen that the frame information signal includes a signal which indicates the frame speed. This signal is comprised within three bits which are capable of indicating 8 speeds, these being 600, 1200, 2400, 4800, 9600, 19.2Y and 38.4IC, wlth capaclty for one ~urther speedi.
In the remainder of the description which follows, the case will be described where only the speeds 1200, 2400 and 4800 BPS are used.
.
~091/00655 ` PCT/U~90/02679 8 ~ 2 The system operates as follows. The transmitter puts together the sync portion of the frame in controller 15;
Depending on the volume of traffic and~or other factors, the controller 15 will determine the three bits within frame information signal which indicate the fxame speed.
The transmitter 17 transmits the sync portion 31 of the frame at a predetermined speed of 1200 bits per second.
Corresponding to the beginning of the first block of :~::
portion 32, the transmitter 17 switches to the bit rate of the frame, for example 2400 BPS, and the remainder of the frame 32 is transmitted at the higher bit rate.
The receiver 11 receives this signal, which is amplified in amplifier 20, mixed down to an IF frequency by mixer 21 and oscillator 29, ampli~ied in amplifl.~r 22, further mixed down in the frequency by mixer 23 and oscillator 25, and then filtered by Eilt~r 26. Th~
~iltered signal ~rom f:Llter 26 i9 demodulated at 1200 BPS
in demodulator 27, and the bit stream derived ~rom the signal is fed to microprocessor 28. On receipt of the frame info code word D or E, microprocessor 28 identifies the bit rate of the ~orthcoming ~rame, whereupon it adjusts the bandwidth of IF filter 26 via control line 29. In 25 response to a signal from control line 29, filter 26 ;
changes its bandwidth. In the present case, with the forthcoming frame bit rate determined as 2400 BPS, and the ;~
rate of the sync portion being 1200 BPS the filter 26 switches from the na~row bandwidth 26a to the intermediate bandwidth 26b. This is necessary because the narrow bandwidth, while giving better signal-to-noise at 1200 BPS, is too narrow for a 2900 BPS signal. One possible manner in which this change is implemented is illustrated in Figure 3.
Referring to that figure~ three ceramic ~ilters are shown 40, 41 and 42. Filter 40 has a typical bandwidth of 5.5 KHz ~ or - 10%. Filter 41 has a typical bandwidth of WO91/0~65~ 2 0 ~ ~ ~ 9 2 PCT/US90/0267~
8.25 KHz + or - 10% and filter 92 has a typical bandwidth of 11 KHz + or - 10~. A CMOS analog switch 43 is provided of the type MC14066B. The filter circuits 26 receives inputs from the second mixer 23 and provide the inputs to the filters 90,41 and 42. There is a three-bit control line 29 from the microprocessor 28 to the switch 93. The outputs of the filters 90, 41 and 42 are connected to an IF
amplifier 45, which is connected to the demodulator 27.
The filter operates as ~ollow5. On receipt of the frame speed code (1200 BPS), the microcomputer 28 provides a signal on control line 29 which operates analog switch 43 to remain connected to IF amp 45 from filter 40 for continued 1200 BPS operation. In this instance filters 41 and 42 are isolated from the IF amp 95.
If the frame 5peed i~ to be changed ~rom 1200 BPS to 4800 BPS, the microcomputer 28 rec~lves the appropriate ~rame speed code, and causes the switch 43 to dlsconnect filter 40 and connect the IF arnp ~5 to the ~ilter 42. In this instance, filters 40 and 41 are isolated from the circuit.
The demodulator 27 acts as a frequency discriminator, and the possible choices could be: at the bit rate of 1200, the high and low bit frequencies are at the carrier frequency + or -2.2KHz, at the bit rate of 2400 BPS, the frequencies are carrier + or -3.8 KHz. At 4800 BPS, the : ~requencies-are carrier ~ or -4.5 KHz.
:: 30 It should be understood that there may be numerous other ways of implementing the invention, particularly in implementing the variable bandwidth filter 26. It will also be appreciated that the filter 26, may be capable of providing two ~andwidths only, or more than three bandwidths, and for example wider bandwidths may be provided for higher bit rates such as 9600 BPS, 19.2 K and 38.4 K. It should be further appreciated that the receiver ~ O91/0065~ PCT/US90/02679 7 . : 2 ~
of the present invention may alternately be constructed ~ -with a single intermediate frequency, thereby eliminating ~:
elements 22, 23 and 25 from Figure 1. Alternately, more than two intermediate frequencies may be used.
What is claimed is:
Claims (10)
Claims
1. A selective call receiver, comprising:
means for receiving a modulated data signal having a variable bit rate and including a code indicative of the bit rate;
a demodulator;
a bandpass filter for filtering the signal prior to demodulation in the demodulator, said bandpass filter having an adjustable bandwidth; and means for adjusting the bandwidth of the bandpass filter in response to the code received.
means for receiving a modulated data signal having a variable bit rate and including a code indicative of the bit rate;
a demodulator;
a bandpass filter for filtering the signal prior to demodulation in the demodulator, said bandpass filter having an adjustable bandwidth; and means for adjusting the bandwidth of the bandpass filter in response to the code received.
2. The receiver of claim 1, wherein said means for adjusting the filter bandwidth are arranged to change the bandwidth a predetermined first time after receipt of the code.
3. The receiver of claim 2, wherein said means are arranged to increase the bandwidth at said first time from a narrower to a wider bandwidth.
4. The receiver of claim 3 wherein means are provided for switching the receiver from a lower to a higher bit rate receive mode at substantially the same time as said first time.
5. The receiver of claim 4 wherein means are provided for returning the receiver to said lower bit rate receive mode at a predetermined second time after said first time and for restoring the filter bandwidth from said wider to said narrower bandwidth at substantially the same time as said second time.
6. The receiver of claim 1 wherein said filter is arranged to provide a bandwidth selectable to correspond to at least two different bandwidths.
7. The receiver of claim 1, wherein said adjustable bandwidth filter comprises at least two discrete filters and switching means for directing the signal through a i selected one thereof.
8. The receiver of claim 8 wherein the discrete filters are ceramic filters.
WO 91/00655 PCT/US90/0267?
WO 91/00655 PCT/US90/0267?
9. A selective call system, comprising:
a transmitter for transmitting a modulated data signal, said transmitter including means for selecting a bit rate for the signal, and means for including a code in said signal indicating the bit rate determined;
a selective call receiver for receiving the signal including the code, said receiver having a demodulator and a bandpass filter for filtering the signal prior to demodulation in the demodulator, said bandpass filter having an adjustable bandwidth; said receiver also having means for adjusting the bandwidth of the bandpass filter in response to the code received.
WO 91/00655 PCT/US90/0267?
a transmitter for transmitting a modulated data signal, said transmitter including means for selecting a bit rate for the signal, and means for including a code in said signal indicating the bit rate determined;
a selective call receiver for receiving the signal including the code, said receiver having a demodulator and a bandpass filter for filtering the signal prior to demodulation in the demodulator, said bandpass filter having an adjustable bandwidth; said receiver also having means for adjusting the bandwidth of the bandpass filter in response to the code received.
WO 91/00655 PCT/US90/0267?
10. A method of operation of a selective call system, comprising the steps of:
transmitting a modulated data signal at a bit rate selected from a plurality of bit rates, said signal including a code indicating the bit rate;
receiving the signal at a selective call receiver having a demodulator and a bandpass filter for filtering the signal prior to demodulation in the demodulator, said bandpass filter having an adjustable bandwidth; and adjusting the bandwidth of the bandpass filter in response to the code received.
transmitting a modulated data signal at a bit rate selected from a plurality of bit rates, said signal including a code indicating the bit rate;
receiving the signal at a selective call receiver having a demodulator and a bandpass filter for filtering the signal prior to demodulation in the demodulator, said bandpass filter having an adjustable bandwidth; and adjusting the bandwidth of the bandpass filter in response to the code received.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US37116389A | 1989-06-26 | 1989-06-26 | |
| US371,163 | 1989-06-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2050892A1 true CA2050892A1 (en) | 1990-12-27 |
Family
ID=23462763
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002050892A Abandoned CA2050892A1 (en) | 1989-06-26 | 1990-05-17 | Receiver with variable predetection bandwidth based on expected data rate |
Country Status (3)
| Country | Link |
|---|---|
| CN (1) | CN1049588A (en) |
| CA (1) | CA2050892A1 (en) |
| WO (1) | WO1991000655A1 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4324603A1 (en) * | 1993-07-22 | 1995-01-26 | Becker Gmbh | IF filter arrangement in a receiver for FM received signals |
| EP0714181B1 (en) * | 1994-06-10 | 2005-04-20 | NTT DoCoMo, Inc. | Receiver |
| US6055268A (en) * | 1996-05-09 | 2000-04-25 | Texas Instruments Incorporated | Multimode digital modem |
| WO1998002986A1 (en) * | 1996-07-15 | 1998-01-22 | Oki Telecom | Subsequent frame variable data rate indication method for various variable data rate systems |
| EP0966806B1 (en) * | 1997-03-14 | 2004-12-01 | Siemens Aktiengesellschaft | Method for transmitting information to a mobile receiver such as a pager, using radio transmitters |
| JP3106999B2 (en) * | 1997-06-05 | 2000-11-06 | 日本電気株式会社 | Radio selective call receiver |
| US6862322B1 (en) * | 2000-05-19 | 2005-03-01 | International Business Machines Corporation | Switchable-bandwidth optical receiver |
| US7865135B2 (en) * | 2005-08-18 | 2011-01-04 | Lg Innotek Co., Ltd. | Apparatus for receiving satellite broadcasting and method thereof |
| US9578469B2 (en) | 2014-10-02 | 2017-02-21 | Motorola Solutions, Inc. | Method and system for direct mode communication within a talkgroup |
| CN105048966A (en) * | 2015-06-12 | 2015-11-11 | 中国电子科技集团公司第四十一研究所 | Multi-phase digital down conversion method for GHz high-speed sampling signal |
| CN112688701B (en) * | 2020-12-22 | 2022-05-31 | 北京奕斯伟计算技术有限公司 | Receiver circuit and receiver circuit control method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4008373A (en) * | 1975-10-03 | 1977-02-15 | Motorola, Inc. | Digital differential phase shift keyed modulator |
| JPS5961644U (en) * | 1982-10-15 | 1984-04-23 | 日本電気株式会社 | selective call receiver |
| AU599613B2 (en) * | 1986-10-21 | 1990-07-26 | Motorola, Inc. | Radio communication receiver with apparatus for altering bit rate of the receiver |
-
1990
- 1990-05-17 CA CA002050892A patent/CA2050892A1/en not_active Abandoned
- 1990-05-17 WO PCT/US1990/002679 patent/WO1991000655A1/en active Application Filing
- 1990-06-25 CN CN90103116.XA patent/CN1049588A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| CN1049588A (en) | 1991-02-27 |
| WO1991000655A1 (en) | 1991-01-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued | ||
| FZDE | Discontinued |
Effective date: 19921117 |