CN105048966A - Multi-phase digital down conversion method for GHz high-speed sampling signal - Google Patents

Abstract

The present invention relates to the technical field of signal processing, and especially relates to a multi-phase digital down conversion method for a GHz high-speed sampling signal. A multi-phase decomposition thought is utilized, multi-phase decomposition is performed for a GHz and above high-speed sampling signal to obtain a plurality of sub signal sequences with low sampling rate, quadrature mixing and multi-phase filter processing are respectively performed for each sub signal sequence, and finally quadrature digital down conversion processing of the high-speed sampling signal is achieved through numerical calculation at low operating frequency, thereby greatly reducing complexity of quadrature digital down conversion processing of the high-speed sampling signal. In addition, the multi-phase digital down conversion method of the present invention can achieve digital down conversion processing of various intermediate frequency signals with random bandwidth through structural extension and flexible parameter setting.

Description

A kind of multiphase digital down conversion method of gigahertz high-speed sampling signal

Technical field

The present invention relates to signal processing technology field, be specifically related to a kind of multiphase digital down conversion method of gigahertz high-speed sampling signal.

Background technology

The basic function of Digital Down Convert is that digital medium-frequency signal higher for speed is down-converted to digital baseband signal, and by extracting the sampling rate reducing signal.Fig. 1 is the basic model of Digital Down Convert.In figure, the output signal of high-speed a/d converter is sent into digital down converter, after the digital quadrature mixer that two multipliers are formed, be multiplied by the orthogonal sine signal that the digital signal of input and multiple sinusoidal signal generator produce, multiplied result is I, Q two paths of signals; Again respectively through the digital baseband signal extracted and after filtering, output data rate reduces.

Assuming that the IF input signals after A/D sampling is first carry out product with digital local oscillator signal in the basic model of Digital Down Convert, obtain in-phase signal and orthogonal signalling, namely

x _c(n)＝x(n)cos(2πf ₀n)(1)

x _s(n)＝x(n)sin(2πf ₀n)(2)

Again after filtering extraction, obtain the Output rusults of I passage and Q passage:

x _I(n)＝x _c(n)h(n)(3)

x _Q(n)＝x _s(n)h(n)(4)

Said process is traditional Digital Down Convert scheme.

For the broadband signal filtering extraction of high-speed sampling, there is the contradiction being difficult to be in harmonious proportion:

(1) high power extracts the contradiction between signal high fidelity.High power extraction is carried out to high-speed sampling signal, can signal data rate be reduced, so reduce the process such as follow-up filtering realize difficulty.But from signal time domain measurement angle, the time domain specification of measured signal will undistorted as far as possible reception and storage, requires that signal sampling rate is high as far as possible.

(2) high power extracts and analyzes greatly the contradiction between bandwidth.High power extracts and reduces signal sampling speed, increases the realizability of Digital Down Convert in engineering, but high as far as possible up to the analysis bandwidth requirement signal sampling speed of 500MHz, thus avoids lack sampling to cause signal aliasing distortion.

In addition, FPGA hardware platform realizes the classical Digital Down Convert shown in Fig. 1 and can run into following Railway Project:

(1) (be greater than 200MHz) when if signal sampling speed is higher, FPGA cannot receive with common I/O pin;

(2) high speed NCO cannot be realized with conventional look-up table;

(3) high-speed gear that frequency mixer is used cannot realize;

(4) high-speed gear in decimation filter and adder realize difficulty.

In summary, conventional digital down conversion method is the inapplicable process with large bandwidth high-speed sampling signal, must adopt signal transacting new construction and new method.

Summary of the invention

For the defect that prior art exists, the object of the invention is to the multiphase digital down conversion method proposing a kind of gigahertz high-speed sampling signal, by input signal and local oscillation signal are carried out poly phase, mixing is carried out to the parallel subsequence of M group input signal and local oscillation signal, to reduce the data rate often organizing subsequence signal, low operating frequency realizes the quadrature downconvert process of high-speed sampling signal.

For reaching above-mentioned purpose, on the one hand, the invention provides a kind of multiphase digital down conversion method of gigahertz high-speed sampling signal, comprising:

IF input signals x (n) of digital mixer etc. is postponed to be decomposed into M item:

$x\left(n\right)=\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right);$ M is positive integer;

Described mixing local oscillation signal Lo (n) etc. is postponed to be decomposed into M item:

$\mathrm{Lo}\left(n\right)=\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{Lo}}_q\left(n\right);$

By x _i(n) and Lo _qn () one_to_one corresponding carries out quadrature downconvert, obtain M output signal y _i(n);

By this M output signal y _in () is equivalent to y (n):

$\begin{array}{c}y\left(n\right)=x\left(n\right)\×\mathrm{Lo}\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\×\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{Lo}}_q\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\×{\mathrm{Lo}}_i\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{y}_i\left(n\right)\end{array}.$

On the other hand, the invention provides a kind of multiphase digital lower frequency changer circuit of gigahertz high-speed sampling signal, comprising:

M group Digital Down Convert circuit, for respectively to M group IF input signals x _i(n) and M group mixing local oscillation signal Lo _qn () one_to_one corresponding carries out quadrature downconvert; M is positive integer, i ∈ (0, M-1), q ∈ (0, M-1);

M group multiphase filter, for extracting and filtering the signal after M group quadrature downconvert respectively;

Wherein, every two adjacent groups IF input signals x _ibetween (n), and every two adjacent groups mixing local oscillation signal Lo _qbetween (n), the clock cycle that interval is identical.

The present invention can reach following beneficial effect:

The present invention utilizes poly phase thought, by the subsignal sequence that GHz and above high-speed sampling signal poly phase thereof are multiple low sampling rate, and quadrature downconvert and multiphase filtering process are carried out respectively to each subsequence, the last orthogonal digital down-converted being achieved high-speed sampling signal in low operating frequency by numerical computations, significantly reduces the complexity of high-speed sampling signal in orthogonal Digital Down Convert process; In addition, the present invention is arranged flexibly by structure extension and parameter, can realize the Digital Down Convert process of any bandwidth, arbitrarily intermediate-freuqncy signal.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the basic model schematic diagram of Digital Down Convert in prior art;

Fig. 2 is the flow chart of the multiphase digital down conversion method of a kind of gigahertz high-speed sampling of the present embodiment signal;

Fig. 3 is the structure chart of the multiphase digital lower frequency changer circuit of a kind of gigahertz high-speed sampling of the present embodiment signal;

Fig. 4 is that the parallel many group multiphase filterings of broadband high-speed sampled signal realize block diagram.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.

The present invention utilizes heterogeneous parallel processing technique mainly to solve following 2 problems of the digital mixing of high-speed sampling signal:

1, the digital quadrature mixing problem of GHz and above high-speed sampling signal.

The present invention adopts poly phase method to change high-speed sampling signal in orthogonal mixing structure, under the low clock rate of hardware, achieve the quadrature downconvert of high-speed sampling signal, solving conventional one-channel quadrature downconvert method cannot to the problem of GHz and the mixing of above high-speed sampling signal in orthogonal.

2, the multiphase filtering problem of GHz and above high-speed sampling broadband signal

Key of the present invention is the thought applying input signal and local oscillation signal poly phase, the input signal of high-speed sampling and local oscillation signal are expressed as the superposition of M group subsequence signal, wherein each group subsequence signal is made up of high-speed sampling input signal and each M of local oscillation signal the sequential value postponed successively, thus input signal and local oscillation signal are carried out poly phase, reduce the data rate (compared with former high-speed sampling signal, sampling rate reduces M doubly) often organizing subsequence signal.By carrying out mixing to the parallel subsequence of M group input signal and local oscillation signal, low operating frequency realizes the quadrature downconvert process of high-speed sampling signal.

Embodiment one

Fig. 2 is the flow chart of the multiphase digital down conversion method of a kind of gigahertz high-speed sampling of the present embodiment signal, as shown in the figure, comprising:

Step 201, postpones to be decomposed into M item by IF input signals x (n) of digital mixer etc.:

$x\left(n\right)=\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right);$ M is positive integer;

Suppose that the input signal of digital mixer is x (n), mixing local oscillation signal is Lo (n).The sampling period of input signal and local oscillation signal is T _s, sample frequency is f _s.Then input signal x (n) can be expressed as

$x\left(n\right)=\underset{k=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{x}_c\left({\mathrm{kT}}_s\right)\mathrm{\δ}\left[(n-k)T_s\right]---\left(1\right)$

Wherein, x _c(kT _s) be continuous time signal x _cthe sampling of (t); δ () is Dirac function.

For reducing the data rate of input signal, input signal x (n) being carried out poly phase, is decomposed into the superposition of M group subsequence signal.Make k=mM+i, x (n) can be shown as following form by decomposition

$\begin{array}{c}x\left(n\right)=\underset{k=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{x}_c\left({\mathrm{kT}}_s\right)\mathrm{\δ}\left[(n-k)T_s\right]\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}\underset{m=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{x}_c[{\mathrm{mMT}}_s+{\mathrm{iT}}_s]\mathrm{\δ}\left[(n-\mathrm{mM}-i)T_s\right]\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\end{array}---\left(2\right)$

Wherein,

$\begin{array}{c}{x}_i\left(n\right)=\underset{m=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{x}_c[{\mathrm{mMT}}_s+{\mathrm{iT}}_s]\mathrm{\δ}\left[(n-\mathrm{mM}-i)T_s\right]\\ =\underset{m=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{x}_c[m\left({\mathrm{mT}}_s\right)+{\mathrm{iT}}_s]\mathrm{\δ}[(n-\mathrm{mM})T_s-{\mathrm{iT}}_s]\end{array}i=\mathrm{0,2},\mathrm{L\; M}-1---\left(3\right)$

By x _in the expression formula of () is visible, x _in () can regard the sampling period as is MT _s, time migration is iT _ssignal, x _in () can regard x as _i+1the delay of (n).Therefore, formula (2) can be regarded as the poly phase of signal x (n).In addition, compared with signal x (n), x _in the sampling rate of () reduces M doubly, i.e. f _s/ M.

Step 202, postpones to be decomposed into M item by described mixing local oscillation signal Lo (n) etc.:

$\mathrm{Lo}\left(n\right)=\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{Lo}}_q\left(n\right);$

In like manner, suppose that the frequency of local oscillation signal Lo (n) is f ₀, initial phase is local oscillation signal also can be expressed as by poly phase

$\begin{array}{c}\mathrm{Lo}\left(n\right)=\underset{l=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Lo}}_c\left({\mathrm{lT}}_s\right)\mathrm{\δ}\left[(n-l)T_s\right]\\ =\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}\underset{p=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Lo}}_c[{\mathrm{pMT}}_s+{\mathrm{qT}}_s]\mathrm{\δ}\left[(n-\mathrm{pM}-q)T_s\right]\\ =\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{Lo}}_q\left(n\right)\end{array}---\left(4\right)$

Wherein,

$\begin{array}{c}{\mathrm{Lo}}_q\left(n\right)=\underset{p=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Lo}}_c[{\mathrm{pMT}}_s+{\mathrm{qT}}_s]\mathrm{\δ}\left[(n-\mathrm{pM}-q)T_s\right]\\ =\underset{p=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Lo}}_c[p\left({\mathrm{MT}}_s\right)+{\mathrm{qT}}_s]\mathrm{\δ}[(n-\mathrm{pM})T_s-q{T}_s]\end{array}---\left(5\right)$

Formula (4) represents that local oscillation signal Lo (n) is the superposition of M group subsequence local oscillation signal through poly phase.Lo _qn () can regard the sampling period as is MT _s, initial phase offset is 2 π f ₀qT _ssignal, Lo _qn the data sampling frequency of () reduces M doubly.Therefore, Lo _qn (), q=0, can regard the sampling period (or frequency) as between 2, LM-1, initial phase difference is 2 π f ₀t _s.

Step 203, by x _i(n) and Lo _qn () one_to_one corresponding carries out quadrature downconvert, obtain M output signal y _i(n);

Step 204, by this M output signal y _in () is equivalent to y (n):

Digital quadrature mixing process can be regarded input signal as and be multiplied with local oscillation signal and process, then the output signal y (n) after quadrature downconvert can be expressed as:

$\begin{array}{c}y\left(n\right)=x\left(n\right)\×\mathrm{Lo}\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\×\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{Lo}}_q\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\×{\mathrm{Lo}}_i\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{y}_i\left(n\right)\end{array}---\left(7\right)$

Wherein,

From formula (7), the output signal after quadrature downconvert can regard M group subsequence y as _ithe superposition of (n), and formula (8) represents y _in () is by subsequence x _i(n) and Lo _in () quadrature downconvert obtains.And x _i(n) and Lo _in the data rate of () is compared with Lo (n) with x (n), reduce M doubly.Therefore, formula (8) shows that the quadrature downconvert of high-speed sampling signal can be realized on low data rate by poly phase.

$\begin{array}{c}y\left(n\right)=x\left(n\right)\×\mathrm{Lo}\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\×\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{Lo}}_q\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\×{\mathrm{Lo}}_i\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{y}_i\left(n\right)\end{array}.$

Embodiment two

Fig. 3 is the structure chart of the multiphase digital lower frequency changer circuit of a kind of gigahertz high-speed sampling of the present embodiment signal, and wherein, DDS is Direct Digital Synthesizer, as shown in Figure 3, for 1.6GHz high-speed sampling signal, comprising:

M group Digital Down Convert circuit, for respectively to M group IF input signals x _i(n) and M group mixing local oscillation signal Lo _qn () one_to_one corresponding carries out quadrature downconvert; M is positive integer, i ∈ (0, M-1), q ∈ (0, M-1);

M group multiphase filter, for extracting and filtering the signal after M group quadrature downconvert respectively;

Wherein, every two adjacent groups IF input signals x _ibetween (n), and every two adjacent groups mixing local oscillation signal Lo _qbetween (n), the clock cycle that interval is identical.

Preferably, also comprise multiphase filter configuration module, for adjusting the width of described M group multiphase filter according to user instruction.

Wherein, at extraction and filtering stage, the present invention adopts many group multiphase filter parallel processing techniques, and 200MHz clock realizes 2 times of extractions of 1.6GHz sampled signal.As shown in Figure 4, for the parallel many group multiphase filterings of broadband high-speed sampled signal realize block diagram.

In the present invention, the 1.6GHz sampled signal after digital quadrature mixing is divided into 8 tunnels, directly as the input of first multiphase filter, carries out 8 times of extractions to high-speed sampling signal, exports the signal of 200MHz sample rate; The input of second multiphase filter is the signal after first multiphase filter input signal postpones 2 clock cycle, and exporting also is the signal that 200MHz samples; By that analogy, the input of the 4th multiphase filter is the signal after first multiphase filter input signal postpones 6 clock cycle.The 4 road signals exported are equivalent to the 800MHz sampled signal after 2 times of extractions.For making multiphase filtering bandwidth adjust as required, increase the flexibility that multiphase filter bandwidth is arranged, this project increases multiphase filter configuration feature, makes user can adjust filter width according to actual conditions on control inerface.

The present invention can reach following beneficial effect:

The present invention utilizes poly phase thought, by the subsignal sequence that GHz and above high-speed sampling signal poly phase thereof are multiple low sampling rate, and quadrature downconvert and multiphase filtering process are carried out respectively to each subsequence, the last orthogonal digital down-converted being achieved high-speed sampling signal in low operating frequency by numerical computations, significantly reduces the complexity of high-speed sampling signal in orthogonal Digital Down Convert process; In addition, the present invention is arranged flexibly by structure extension and parameter, can realize the Digital Down Convert process of any bandwidth, arbitrarily intermediate-freuqncy signal.

Those skilled in the art can also recognize the various illustrative components, blocks (illustrativelogicalblock) that the embodiment of the present invention is listed, unit, and step can pass through electronic hardware, computer software, or both combinations realize.For the replaceability (interchangeability) of clear displaying hardware and software, above-mentioned various illustrative components (illustrativecomponents), unit and step have universally described their function.Such function is the designing requirement realizing depending on specific application and whole system by hardware or software.Those skilled in the art for often kind of specifically application, can use the function described in the realization of various method, but this realization can should not be understood to the scope exceeding embodiment of the present invention protection.

Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (6)

1. a multiphase digital down conversion method for gigahertz high-speed sampling signal, is characterized in that, comprising:

IF input signals x (n) of digital mixer etc. is postponed to be decomposed into M item:

$x\left(n\right)=\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right);$ M is positive integer;

Described mixing local oscillation signal Lo (n) etc. is postponed to be decomposed into M item:

$\mathrm{Lo}\left(n\right)=\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{Lo}}_q\left(n\right);$

By x _i(n) and Lo _qn () one_to_one corresponding carries out quadrature downconvert, obtain M output signal y _i(n);

By this M output signal y _in () is equivalent to y (n):

$\begin{array}{c}y\left(n\right)=x\left(n\right)\×\mathrm{Lo}\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\×\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{Lo}}_q\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\×{\mathrm{Lo}}_i\left(n\right)\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{y}_i\left(n\right)\end{array}.$

2. method according to claim 1, is characterized in that, described IF input signals x (n) of digital mixer is carried out multinomial decomposition, waits delay to be decomposed into M item and specifically comprises:

Obtain the sampling period T of described IF input signals x (n) and mixing local oscillation signal Lo (n) _s, and sample frequency f _s;

Described IF input signals x (n) is decomposed according to following computational process:

wherein, x _c(kT _s) be continuous time signal x _cthe sampling of (t); δ () is Dirac function;

Make k=mM+i then:

$\begin{array}{c}x\left(n\right)=\underset{k=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{x}_c\left({\mathrm{kT}}_s\right)\mathrm{\δ}\left[(n-k)T_s\right]\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}\underset{m=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{x}_c[\mathrm{mM}{T}_s+i{T}_s]\mathrm{\δ}\left[(n-\mathrm{mM}-i)T_s\right]\\ =\underset{i=0}{\overset{M-1}{\mathrm{\Σ}}}{x}_i\left(n\right)\end{array};$

Wherein,

$\begin{array}{c}{x}_i\left(n\right)=\underset{m=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{x}_c[\mathrm{mM}{T}_s+i{T}_s]\mathrm{\δ}\left[(n-\mathrm{mM}-i)T_s\right]\\ =\underset{m=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{x}_c[m\left({\mathrm{MT}}_s\right)+i{T}_s]\mathrm{\δ}[(n-\mathrm{mM})T_s-i{T}_s]\end{array}.$

3. method according to claim 2, is characterized in that, described described mixing local oscillation signal Lo (n) is carried out multinomial decomposition, waits delay to be decomposed into M item and specifically comprises:

Obtain the frequency f of described mixing local oscillation signal Lo (n) ₀, and initial phase

Described mixing local oscillation signal Lo (n) is decomposed according to following computational process:

$\begin{array}{c}\mathrm{Lo}\left(n\right)=\underset{l=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Lo}}_c\left({\mathrm{lT}}_s\right)\mathrm{\δ}\left[(n-l)T_s\right]\\ =\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}\underset{p=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Lo}}_c[\mathrm{pM}{T}_s+q{T}_s]\mathrm{\δ}\left[(n-\mathrm{pM}-q)T_s\right]\\ =\underset{q=0}{\overset{M-1}{\mathrm{\Σ}}}{\mathrm{Lo}}_q\left(n\right)\end{array};$

Wherein,

$\begin{array}{c}{\mathrm{Lo}}_q\left(n\right)=\underset{p=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Lo}}_c[\mathrm{pM}{T}_s+q{T}_s]\mathrm{\δ}\left[(n-\mathrm{pM}-q)T_s\right]\\ =\underset{p=-\∞}{\overset{\∞}{\mathrm{\Σ}}}{\mathrm{Lo}}_c[p\left({\mathrm{MT}}_s\right)+q{T}_s]\mathrm{\δ}[(n-\mathrm{pM})T_s-q{T}_s]\end{array};$

4. method according to claim 3, is characterized in that:

By x _i(n) and Lo _qn () quadrature downconvert is outputed signal:

5. a multiphase digital lower frequency changer circuit for gigahertz high-speed sampling signal, is characterized in that, comprising:

M group Digital Down Convert circuit, for respectively to M group IF input signals x _i(n) and M group mixing local oscillation signal Lo _qn () one_to_one corresponding carries out quadrature downconvert; M is positive integer, i ∈ (0, M-1), q ∈ (0, M-1);

M group multiphase filter, for extracting and filtering the signal after M group quadrature downconvert respectively;

Wherein, every two adjacent groups IF input signals x _ibetween (n), and every two adjacent groups mixing local oscillation signal Lo _qbetween (n), the clock cycle that interval is identical.

6. circuit according to claim 5, is characterized in that, also comprises multiphase filter configuration module, for adjusting the width of described M group multiphase filter according to user instruction.