CN103313315B - Speed conversion equipment and method, base station equipment - Google Patents
Speed conversion equipment and method, base station equipment Download PDFInfo
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Abstract
The embodiment of the invention discloses a kind of speed conversion equipment and method, base station equipment, wherein, this device includes: pretreatment module, for input data being carried out pretreatment according to interpolation rate, obtain each interpolation nodes of described input data, input sample data that each interpolation nodes is corresponding, the interpolation coefficient that each interpolation nodes is corresponding, described interpolation rate is the speed ratio with the speed of output data of described input data；Memory module, is used for the interpolation coefficient preserving input sample data corresponding to each interpolation nodes, each interpolation nodes is corresponding；Output processing module, for interpolation coefficient corresponding with each interpolation nodes for input sample data corresponding for each interpolation nodes being multiplied accumulating mutually and carrying out the saturated process of rounding, obtain described output data, solve existing wave filter based on polynomial function speed conversion equipment exist along with application scenarios change must redesign wave filter, and design cost is higher, and the problem that logical process time delay is bigger.
Description
Technical field
The present embodiments relate to communication technical field, particularly relate to a kind of speed conversion equipment and method, base station equipment.
Background technology
In a wireless communication system, the bandwidth of various mobile standards differs, and the speed of its baseband signal is the most different.Traditional old base station can only be for a kind of base band business, and operator maximizes to make investment interests, it is desirable to multiple business can be supported in same base station, then occurs in that the Multi-Mode Base Station that can simultaneously support multiple business.Trans-rating technique can complete the conversion of multimode baseband signal speed; by analog-digital converter (AnalogtoDigitalConverter identical for rate adaptation different for base band side to wireless side; it is called for short ADC) and digital to analog converter (DigitaltoAnalogConverter; it is called for short DAC) in speed; so can use identical ADC and DAC module, including identical ADC and DAC clock.
Prior art programmable gate array (FieldProgrammableGateArray at the scene, it is called for short FPGA) the middle conversion using logical resource to realize multimode baseband signal speed, in FPGA realizes speed conversion, rate conversion circuit can be understood as a fractional multiple word filter circuit, this wave filter uses (N-1) secondary polynomial of one indeterminate its receptance function of function approximation, N is the exponent number of this wave filter, depend on system operations required precision, generally theory analysis combines with system performance testing and determines, rate conversion circuit solves at the coefficient of this (N-1) secondary polynomial of one indeterminate and builds on the basis of mark times filter circuit.
During realizing the present invention, inventor finds the rate conversion circuit of wave filter based on polynomial function in prior art, exists and must redesign wave filter, and the problem that design cost is higher, logical process time delay is bigger along with application scenarios changes.
Summary of the invention
The embodiment of the present invention provides a kind of speed conversion equipment and method, base station equipment, in order to solve existing wave filter based on polynomial function rate conversion circuit exist along with application scenarios change must redesign wave filter, and the problem that design cost is higher, logical process time delay is bigger.
The first aspect of the invention is to provide a kind of speed conversion equipment, including:
Pretreatment module, for input data being carried out pretreatment according to interpolation rate, obtain each interpolation nodes of described input data, input sample data that each interpolation nodes is corresponding, the interpolation coefficient that each interpolation nodes is corresponding, described interpolation rate is the speed ratio with the speed of output data of described input data；
Memory module, is used for the interpolation coefficient preserving input sample data corresponding to each interpolation nodes, each interpolation nodes is corresponding；
Output processing module, for being multiplied accumulating mutually by interpolation coefficient corresponding with each interpolation nodes for input sample data corresponding for each interpolation nodes and carrying out the saturated process of rounding, obtains described output data.
Another aspect of the present invention is to provide a kind of rate conversion method, including:
According to interpolation rate, input data are carried out pretreatment, in order to the input sample data obtaining each interpolation nodes of described input data, each interpolation nodes is corresponding, the interpolation coefficient that each interpolation nodes is corresponding, described interpolation rate is the speed ratio with the speed of output data of described input data；
Preserve input sample data corresponding to each interpolation nodes, interpolation coefficient that each interpolation nodes is corresponding；
Interpolation coefficient corresponding with each interpolation nodes for input sample data corresponding for each interpolation nodes multiplied accumulating mutually and carries out the saturated process of rounding, obtaining described output data.
An additional aspect of the present invention is to provide a kind of base station equipment, including: above-mentioned speed conversion equipment.
At least one in the most multiple technical schemes has the advantage that or effective effect:
The present embodiment is according to interpolation rate, input data are anticipated, to obtain each interpolation nodes, and input sample data corresponding to each interpolation nodes and interpolation coefficient, input sample data corresponding for each interpolation nodes are multiplied accumulating mutually with interpolation coefficient and exports after saturated for rounding process, obtain the output data after speed conversion, solve existing wave filter based on polynomial function rate conversion circuit exist along with application scenarios change must redesign wave filter, and design cost is higher, the problem bigger with logical process time delay, the renewal improving input data controls, eliminate the node-by-node algorithm process of interpolation coefficient, reduce logical process time delay, also reduce logic realization cost simultaneously, and need not when application scenarios changes redesign wave filter.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, the accompanying drawing used required in embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the speed transfer principle schematic diagram of prior art；
Fig. 2 is the input/output signal time diagram of the speed transfer principle shown in Fig. 1；
Fig. 3 is the structural representation of the rate conversion circuit of prior art；
The structural representation of the speed conversion equipment that Fig. 4 provides for the embodiment of the present invention one；
The structural representation of the speed conversion equipment that Fig. 5 provides for the embodiment of the present invention two；
Fig. 6 is that the speed conversion equipment of the embodiment of the present invention realizes principle schematic；
The schematic flow sheet of the rate conversion method that Fig. 7 provides for the embodiment of the present invention three.
Detailed description of the invention
For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, broadly fall into the scope of protection of the invention.
nullTechnical scheme，Can apply to various mobile cellular network，Such as: global system for mobile communications (GlobalSystemforMobileCommunications，It is called for short GSM) network、GPRS (general packet radio service) (GeneralPacketRadioService，It is called for short GPRS) network、CDMA (CodeDivisionMultipleAccess，It is called for short CDMA) network、CDMA2000 network、WCDMA (WidebandCodeDivisionMultipleAccess，It is called for short WCDMA) network、TD SDMA (TimeDivision-SynchronousCodeDivisionMultipleAccess，It is called for short TD-SCDMA) network、Long Term Evolution (LongTermEvolution，It is called for short LTE) network or World Interoperability for Microwave Access, WiMax (WorldInteroperabilityforMicrowaveAccess，It is called for short WiMAX) network etc..
For the ease of understanding the technical scheme of the embodiment of the present invention, first the principle of rate conversion circuit is described in detail.
Fig. 1 is the speed transfer principle schematic diagram of prior art, as it is shown in figure 1, with speed (1/T1) the discrete baseband signal (input data) that inputs reverts to continuous baseband signal after digital-to-analogue conversion D/A and filtering h (t), then with (1/T2) resampling is discrete baseband signal (output data), the speed of the discrete baseband signal after resampling has been converted into (1/T2), wherein, T1It is 1.554 megabyte per seconds (MegabytePersecond is called for short Mbps), T2For 6.312Mbps.
Fig. 2 is the input/output signal time diagram of the speed transfer principle shown in Fig. 1, according to rate conversion circuit input/output signal sequential shown in rate conversion circuit principle shown in Fig. 1 and Fig. 2, and combine Interpolation Principle, deduce out the recurrence formula of interpolation nodes I (k) and interpolation phase p (k), respectively formula (1) and formula (2).
Wherein, k is output sample sequence, I (k) and p (k) is then the interpolation nodes (input sample sequence) and interpolation phase (phase place of deviation input sample) that kth output sample is corresponding, Floor is a downward bracket function, such as Floor (4.8)=4, MOD is mod.
Interpolation rate R=(1/Tin)/(1/Tout)=Mir/Mor, Mir/Mor is the ratio of input rate and output speed, Mir is the input rate of speed conversion, such as 6.5MSPS, Mor is the output speed of speed conversion, such as 7.68MSPS, for example, the interpolation rate (speed ratio) of the present embodiment is a constant, it it is an irreducible fraction in form, for Mir/Mor, and Mir and Mor is coprime positive integer, Tin and Tout is then input sample data and output sample data durations, it it is unit of time, if Tin is the inverse of Mir=6.5MSPS, Tout is the inverse of Mor=7.68MSPS.
Fig. 3 is the structural representation of the rate conversion circuit of prior art, as shown in Figure 3:
Pushup storage (First-InFirst-Out, it is called for short FIFO) export and filter the reading and the generation of filtered phase controlling to be responsible for controlling FIFO, discuss for convenience, only describing the situation of Mir ＜ Mor, existing speed transfer principle is equally applicable to the situation of Mir ＞ Mor.Using mould Mor accumulator to add up Mir, accumulation period is Mor*Tout.When accumulated value is more than or equal to Mor, accumulated value deducts Mor, and exports spill over, instruction data input pin inputs a new numerical value to FIFO, the data read from FIFO are input to filtering interpolation module be filtered, i.e. multiply-add operation simultaneously, produce an interpolation output point；When accumulated value is less than Mor, only produce an interpolation output point.The output of mould Mor accumulator is used for node-by-node algorithm interpolation coefficient to after Mor delivery as interpolation phase.
Therefore; existing rate conversion circuit based on specific multinomial analog filter; when application scenarios changes; signal rate such as Multi-Mode Base Station changes; there is corresponding change the most therewith in interpolation rate R=(1/Tin)/(1/Tout)=Mir/Mor, causes the change of interpolation nodes and interpolation phase, thus cause the change of filter order and interpolation coefficient; therefore, it is necessary to redesign wave filter.
The existing wave filter simulated based on specific multinomial is when the data inputting FIFO process, main logic resource consumption calculates and input sample renewal control part at interpolation coefficient, and logical resource consumption can increase along with the increase of the complexity of interpolation coefficient computing formula, therefore, logic realization cost is of a relatively high.
The existing wave filter simulated based on specific multinomial, to each input sample data, will carry out the calculating of interpolation nodes, interpolation phase and interpolation coefficient, the most just can draw each output sample data, and therefore, logical process time delay is bigger.
The problem existed in view of above-mentioned prior art, embodiments provides a kind of speed conversion equipment, the structural representation of the speed conversion equipment that Fig. 4 provides for the embodiment of the present invention one, including:
Pretreatment module 41, for input data being carried out pretreatment according to interpolation rate, obtain each interpolation nodes of described input data, input sample data that each interpolation nodes is corresponding, the interpolation coefficient that each interpolation nodes is corresponding, described interpolation rate is the speed ratio with the speed of output data of described input data；
Memory module 42, is used for the interpolation coefficient preserving input sample data corresponding to each interpolation nodes, each interpolation nodes is corresponding；
Output processing module 43, for being multiplied accumulating mutually by interpolation coefficient corresponding with each interpolation nodes for input sample data corresponding for each interpolation nodes and carrying out the saturated process of rounding, obtains described output data.
The embodiment of the present invention is according to interpolation rate, input data are anticipated, to obtain each interpolation nodes, and input sample data corresponding to each interpolation nodes and interpolation coefficient, input sample data corresponding for each interpolation nodes are multiplied accumulating mutually with interpolation coefficient and exports after saturated for rounding process, obtain the output data after speed conversion, solve existing wave filter based on polynomial function rate conversion circuit exist along with application scenarios change must redesign wave filter, and design cost is higher, the problem bigger with logical process time delay, the renewal improving input data controls, eliminate the node-by-node algorithm process of interpolation coefficient, reduce logical process time delay, also reduce logic realization cost simultaneously, and need not when application scenarios changes redesign wave filter.
The structural representation of the speed conversion equipment that Fig. 5 provides for the embodiment of the present invention two, speed conversion equipment the further expanding on the basis of the speed conversion equipment of embodiment illustrated in fig. 4 of embodiment illustrated in fig. 5.
Pretreatment module 41 specifically may include that
First pretreatment unit 411, for input data being carried out pretreatment according to interpolation rate, obtains the input sample data that each interpolation nodes of described input data is corresponding with each interpolation nodes；
Second pretreatment unit 412, for each interpolation nodes obtained according to the first pretreatment unit 411, obtains the interpolation phase that each interpolation nodes is corresponding respectively, obtains, according to each interpolation phase, the interpolation coefficient that each interpolation phase is corresponding.
For example, the first pretreatment unit 411 can use the enumerator according to the design of interpolation rate to realize, and the second pretreatment unit 412 can use coefficient dispensing unit to realize.Specifically, the first pretreatment unit 411 according to interpolation rate, utilize interpolation nodes formula to obtain each interpolation nodes input data sample data corresponding with each interpolation nodes of input data；
Second pretreatment unit 412 utilizes interpolation phase formula to obtain the interpolation phase that each interpolation nodes is corresponding, and obtain, according to each interpolation phase, the interpolation coefficient that each interpolation phase is corresponding, for example, under the response approximating function determined, each interpolation coefficient is uniquely decided by interpolation phase, as under given response approximating function, typically can solve system of linear equations by visualization scientific algorithm instrument Matlab and obtain each interpolation coefficient, and be stored in the second memory element according to interpolation nodes rule correspondence, the embodiment of the present invention is not limited to a kind of response approximating function, because no matter using any response approximating function, finally all be converted to interpolation coefficient, it is stored in the second memory element.
Wherein, interpolation rate R=(1/Tin)/(1/Tout)=Mir/Mor, Mir are the input rate of speed conversion, and Mor is the output speed of speed conversion, and R is the ratio of input rate and output speed；
Interpolation nodes formula is:
Interpolation phase formula is:
Further, memory module 42 specifically may include that
First memory element 421, for preserving the corresponding relation of each interpolation nodes each input sample data corresponding with each interpolation nodes；
Second memory element 422, for preserving the corresponding relation of each interpolation nodes, each interpolation phase and each interpolation coefficient.
For example, the first memory element 421 and the second memory element 422 can be respectively adopted block random access memory and realize.
Further, output processing module 43 specifically may include that
Multiplier 431, processes to obtain each output sample data for doing interpolation coefficient corresponding with described interpolation nodes for input sample data corresponding for each interpolation nodes respectively to be multiplied, and described each output sample data is sent to adder 432；
Adder 432, for described each output sample data are carried out accumulation process, and is sent to saturation unit 433；
Saturation unit 433, the output sample data after adding up carry out the saturated process of rounding to obtain output data.
The embodiment of the present invention uses pretreatment module that input data are carried out pretreated technical characteristic, renewal to input data controls to have made to improve, eliminate the node-by-node algorithm process of interpolation coefficient, therefore, reduce logical process time delay, also reduce logic realization cost simultaneously, and need not when application scenarios changes redesign wave filter.
Fig. 6 is that the speed conversion equipment of the embodiment of the present invention realizes principle schematic, in order to further describe the technical scheme of the embodiment of the present invention, with global system for mobile communications (GlobalSystemofMobilecommunication, it is called for short GSM) & global mobile communication system (UniversalMobileTelecommunicationsSystem, it is called for short UMTS) as a example by bimodulus macro base station, GSM base band data rate is converted to 7.68MSPS by 6.5MSPS, thus GSM baseband signal is fitted to UMTS base band data rate.
Under above-mentioned application scenarios, interpolation rate R=Mir/Mor=6.5/7.68=325/384, according to interpolation nodes formula and interpolation phase formula, assume the initial value I (0)=1 of interpolation nodes, the initial value p (0)=0 of interpolation phase, can obtain interpolation nodes and normalization interpolation phase one to one with recursion；Table 1 is interpolation nodes I (k) the cyclically-varying rule of the present embodiment, and table 2 is normalization interpolation phase p (k) the cyclically-varying rule of the present embodiment.
Table 1
Table 2
As shown in Table 1 and Table 2, " S " in table 1 represents that current interpolation basic point uses same group of input sample data to calculate corresponding output sample data with a upper interpolation nodes, but as can be seen from Table 2, the interpolation phase of the interpolation phase of current interpolation basic point and a upper interpolation nodes also differs, describing for convenience, the interpolation nodes " S " represented referred to as stops to clap position.
In the application scenarios shown in Fig. 6, input base band data I/Q speed 6.5MSPS of speed conversion equipment, being 16bit signed number, output data rate is 7.68MSPS, and during output, the saturated process of rounding is 16bit signed number, interpolation rate R=Mir/Mor=325/384, then the storage depth of interpolation coefficient is 384, and interpolation coefficient is 18bit signed number, owing to work clock is 122.88MHz, so 8 carrier wave 16 tunnel I/Q data can be processed by multiplexing, realize cost with further reduction.It is pointed out that the embodiment of the present invention is not limited to above-mentioned application scenarios.
According to interpolation nodes Changing Pattern, the input base band data that speed is 6.5MSPS is carried out pretreatment, particularly as follows: using speed is the data synchronizing signal of 7.68MSPS, according to the interpolation nodes cyclically-varying rule table shown in table 1, stopping within 384 interpolation nodes cycles is clapped position and stops clapping 59 bats, in order to replace the 6.5MSPS speed inputting base band data, i.e. 7.68MSPS*325/384=6.5MSPS, and it is identical to stop stopping to clap position in bat position and table 1, by this pretreatment, obtain and interpolation nodes input sample data one to one, and input sample data mapping relations corresponding for described interpolation nodes are stored in the first memory element, and input data synchronizing signal to be automatically obtained the input sample data stopping clapping position interpolation constant.
According to normalization interpolation phase p (k) the cyclically-varying rule table shown in table 2, owing to interpolation output initial phase only affects the phase contrast of input and output, do not change base-band information, therefore interpolation phase corresponding interpolation nodes rule under given initial phase is carried out arrangement storage, the accumulator being then no longer necessary to mould 384 calculates the interpolation phase that each interpolation nodes is corresponding one by one, and only need to along with output data synchronizing signal (7.68MSPS) the most one by one+1 be incremented by take out, further according to interpolation phase, utilize interpolation coefficient computing formula to precalculate and obtain the interpolation coefficient that described interpolation phase is corresponding, and described interpolation coefficient corresponding interpolation nodes rule under given initial phase is carried out arrangement be stored in the second memory element, therefore the present embodiment is without node-by-node algorithm interpolation coefficient.It is pointed out that, when application scenarios changes, interpolation coefficient can be reconfigured by second pretreatment unit of the present embodiment according to interpolation rate.
When input data (in table 2, non-stopping claps position) when preprocessed data synchronizing signal is effective, last three sampling point data in the input sample data corresponding with being stored in previous interpolation nodes in the first memory element are spliced into new 4 sampling point data and re-write in the first memory element RAM64*16, and stopping clapping position, owing to data synchronizing signal is invalid, keep data constant, thus realize inputting automatically updating of data；First memory element outfan is under the control of output data syn-chronization, read four sampling point data under current interpolation basic point one by one, and read four interpolation coefficients corresponding with four sampling point data being positioned in RAM0, RAM1, RAM2, the RAM3 in the second memory element respectively, realize after pointwise multiplies accumulating mutually, the saturated output of rounding.
Finally, the interpolation coefficient that four corresponding for each interpolation nodes input sample data are corresponding with each input sample data respectively is carried out, by multiplying unit, the process that is multiplied, obtain four output sample data that each interpolation nodes is corresponding, four output sample data are carried out accumulation process and the saturated process of rounding by summing elements, obtain output data, it is achieved that the data rate transition of 6.5MSPS to 7.68MSPS.
Interpolation nodes and the cyclically-varying rule of interpolation phase is obtained according to interpolation rate, and according to interpolation nodes cyclically-varying rule, input data are carried out pretreatment, obtain corresponding interpolation nodes rule under given initial phase and carry out the input sample data arranged, and store in the first memory element, make input data synchronizing signal be automatically obtained the input sample data stopping clapping position interpolation constant, thus be greatly simplified input sample data and update control.
According to interpolation phase cyclically-varying rule, obtain corresponding interpolation nodes rule under given initial phase and carry out the interpolation coefficient arranged, and store in the second memory element, thus the accumulator being no longer necessary to mould 384 calculates the interpolation coefficient that each interpolation nodes is corresponding one by one, this logical block resource consumed with memory module replacement node-by-node algorithm and multiplier resources, be substantially reduced logical process time delay.
The pretreatment module of the present embodiment can change, according to different interpolation rates, the interpolation coefficient mapping relations that interpolation phase is corresponding, when application scenarios changes, it is not necessary to redesigns wave filter.
The schematic flow sheet of the rate conversion method that Fig. 7 provides for the embodiment of the present invention three, as it is shown in fig. 7, comprises:
Step 701, according to interpolation rate to input data carry out pretreatment, in order to the input sample data obtaining each interpolation nodes of described input data, each interpolation nodes is corresponding, the interpolation coefficient that each interpolation nodes is corresponding, described interpolation rate is the speed ratio with the speed of output data of described input data；
Wherein, wherein, according to interpolation rate to input data carry out pretreatment specifically include into:
The input sample data that each interpolation nodes of interpolation nodes formula acquisition input data is corresponding with each interpolation nodes can be utilized；
Utilize interpolation nodes formula and interpolation phase formula, obtain the interpolation phase that each interpolation nodes is corresponding respectively, obtain, according to each interpolation phase, the interpolation coefficient that each interpolation phase is corresponding.
For example, interpolation nodes and the cyclically-varying rule of interpolation phase is obtained according to interpolation rate, according to interpolation nodes cyclically-varying rule, input data are carried out pretreatment, obtain corresponding interpolation nodes rule under given initial phase and carry out the input sample data arranged.
It should be noted that, under the response approximating function determined, each interpolation coefficient is uniquely decided by interpolation phase, as under given response approximating function, typically can solve system of linear equations by visualization scientific algorithm instrument Matlab and obtain each interpolation coefficient, therefore, it can obtain corresponding interpolation nodes rule under given initial phase and carry out the interpolation coefficient arranged.
Above-mentioned interpolation rate is R=(1/Tin)/(1/Tout)=Mir/Mor, and Mir is the input rate of speed conversion, and Mor is the output speed of speed conversion, and R is the ratio of input rate and output speed；
Interpolation nodes formula is:
Interpolation phase formula is:
Step 702, preserve input sample data corresponding to each interpolation nodes, interpolation coefficient that each interpolation nodes is corresponding.
Specifically include: preserve the input sample data corresponding relation that each interpolation nodes is corresponding with each interpolation nodes in memory；The corresponding relation of each interpolation nodes, each interpolation phase and each interpolation coefficient is preserved in another memorizer.
For example, each input sample data arrange according to interpolation nodes cyclically-varying rule, therefore the corresponding relation of each input sample data corresponding with each interpolation nodes for each interpolation nodes can be preserved in memory, enabling to input data, to be automatically obtained the input sample data stopping clapping position interpolation under synchronizing signal constant, thus be greatly simplified input sample data and update and control.
For example, each interpolation coefficient also arranges according to interpolation nodes cyclically-varying rule, therefore, each interpolation nodes, each interpolation phase can also be preserved with the corresponding relation of each interpolation coefficient, thus the accumulator being no longer necessary to mould 384 calculates the interpolation coefficient that each interpolation nodes is corresponding one by one, this logical block resource consumed with memorizer replacement node-by-node algorithm and multiplier resources, it is possible to be substantially reduced logical process time delay.
Step 703, interpolation coefficient corresponding with each interpolation nodes for input sample data corresponding for each interpolation nodes multiplied accumulating mutually and carries out the saturated process of rounding, obtaining described output data.
For example, multiplication unit can be used input sample data corresponding for each interpolation nodes to be done the process that is multiplied respectively with interpolation coefficient to obtain each output sample data；Can use adder unit that each output sample data are carried out accumulation process；Output sample data after using saturation unit to add up carry out the saturated process of rounding to obtain output data.
The method of the present embodiment can realize the function of the speed conversion equipment of Fig. 4 or embodiment illustrated in fig. 5, and it realizes principle and technique effect repeats no more.
The embodiment of the present invention four provides a kind of base station equipment, including the speed conversion equipment described in above-described embodiment one or embodiment two, specifically in the Multi-Mode Base Station of wireless communication system, for the conversion of multimode baseband signal speed.
Last it is noted that above example is only in order to illustrate technical scheme, it is not intended to limit；Although the present invention being described in detail with reference to previous embodiment, it will be understood by those within the art that: the technical scheme described in foregoing embodiments still can be modified by it, or wherein portion of techniques feature is carried out equivalent；And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (10)
1. a speed conversion equipment, it is characterised in that including:
Pretreatment module, for obtaining interpolation nodes and the cyclically-varying rule of interpolation phase according to interpolation rate, and according to the cyclically-varying rule of described interpolation nodes, the data synchronizing signal using output speed carries out pretreatment to input data, obtain each interpolation nodes of described input data, the input sample data that each interpolation nodes is corresponding, and according to initial phase, the cyclically-varying rule of described interpolation phase obtains, with the data synchronizing signal of described output speed, the interpolation phase that each interpolation nodes is corresponding, the interpolation coefficient that described interpolation phase is corresponding is obtained according to described interpolation phase, described interpolation rate is the speed ratio with the speed of output data of described input data；
Memory module, is used for the interpolation coefficient preserving input sample data corresponding to each interpolation nodes, each interpolation nodes is corresponding；
Output processing module, for being multiplied accumulating mutually by interpolation coefficient corresponding with each interpolation nodes for input sample data corresponding for each interpolation nodes and carrying out the saturated process of rounding, obtains described output data.
Device the most according to claim 1, it is characterised in that described pretreatment module includes:
First pretreatment unit, for input data being carried out pretreatment according to interpolation rate, obtains the input sample data that each interpolation nodes of described input data is corresponding with each interpolation nodes；
Second pretreatment unit, for obtaining, according to each interpolation nodes, the interpolation phase that each interpolation nodes is corresponding respectively, obtains, according to each interpolation phase, the interpolation coefficient that each interpolation phase is corresponding.
Device the most according to claim 1, it is characterised in that described memory module includes:
First memory element, for preserving the corresponding relation of each interpolation nodes and each input sample data；
Second memory element, for preserving the corresponding relation of each interpolation nodes, each interpolation phase and each interpolation coefficient.
Device the most according to claim 3, it is characterised in that described output processing module includes:
Multiplier, for respectively interpolation coefficient corresponding with described interpolation nodes for input sample data corresponding for each interpolation nodes being done the process that is multiplied, obtains each output sample data, and described each output sample data is sent to adder；
Adder, for each output sample data are carried out accumulation process, and is sent to saturation unit；
Saturation unit, the output sample data after adding up carry out the saturated process of rounding to obtain output data.
5. according to the device according to any one of claim 1-4, it is characterised in that described memory module uses block random access memory to realize.
6. a rate conversion method, it is characterised in that including:
Interpolation nodes and the cyclically-varying rule of interpolation phase is obtained according to interpolation rate, and according to the cyclically-varying rule of described interpolation nodes, the data synchronizing signal using output speed carries out pretreatment to input data, in order to obtain each interpolation nodes of described input data, the input sample data that each interpolation nodes is corresponding, and according to initial phase, the cyclically-varying rule of described interpolation phase obtains, with the data synchronizing signal of described output speed, the interpolation phase that each interpolation nodes is corresponding, the interpolation coefficient that described interpolation phase is corresponding is obtained according to described interpolation phase, described interpolation rate is the speed ratio with the speed of output data of described input data；
Preserve input sample data corresponding to each interpolation nodes, interpolation coefficient that each interpolation nodes is corresponding；
Interpolation coefficient corresponding with each interpolation nodes for input sample data corresponding for each interpolation nodes multiplied accumulating mutually and carries out the saturated process of rounding, obtaining described output data.
Method the most according to claim 6, it is characterised in that described according to interpolation rate, input data are carried out pretreatment specifically include:
According to interpolation rate, input data are carried out pretreatment, the input sample data corresponding with each interpolation nodes in order to obtain each interpolation nodes of described input data；
Obtain, according to each interpolation nodes, the interpolation phase that each interpolation nodes is corresponding respectively, obtain, according to each interpolation phase, the interpolation coefficient that each interpolation phase is corresponding.
Method the most according to claim 7, it is characterised in that input sample data that each interpolation nodes of described preservation the is corresponding interpolation coefficient corresponding with each interpolation nodes specifically includes:
Preserve the corresponding relation of each interpolation nodes and each input sample data；
With the corresponding relation preserving each interpolation nodes, each interpolation phase and each interpolation coefficient.
9. according to the method according to any one of claim 6-8, it is characterized in that, described interpolation coefficient corresponding with each interpolation nodes for input sample data corresponding for each interpolation nodes multiplied accumulating mutually and carry out the saturated process of rounding, obtaining described output data and specifically include:
Respectively interpolation coefficient corresponding with described interpolation nodes for input sample data corresponding for each interpolation nodes is done the process that is multiplied to obtain each output sample data；
Described each output sample data are carried out accumulation process；
Output sample data after cumulative are carried out the saturated process of rounding to obtain output data.
10. a base station equipment, it is characterised in that include the speed conversion equipment as according to any one of claim 1-5.
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