CN103269222B - Implementation method and the device of variable symbol rate vector signal - Google Patents

Abstract

The invention discloses a kind of implementation method and device of variable symbol rate vector signal, comprise that the signal receiving is modulated to mapping to be processed, and obtains I, Q two-way modulation signal; Dui Mei road modulation signal forms respectively filtering processing and sigma-delta modulating transformation, obtains the chip rate of output signal; Jiang Mei road modulation signal carries out digital filtering, further eliminates the digitlization residual modulation that interference between chip rate and little transformation of variables bring and disturbs; Again the I road after digital filtering and Q road modulation signal are carried out to Digital Modulation and obtain a road modulation signal, and Digital Modulation Hou mono-road modulation signal is carried out to D/A conversion, obtain a road analog signal; Finally this analog signal is mixed on expection frequency. Can obtain fast more modulation form, the large-scale chip rate of high-resolution by sigma-delta modulating transformation, can be the research and development of communication equipment, chip, terminal and producing maintenance provides Vector Modulation signal.

Description

Implementation method and the device of variable symbol rate vector signal

Technical field

The present invention relates to communication technical field, relate in particular to a kind of realization side of variable symbol rate vector signalMethod and device.

Background technology

In order to comply with the demand of development in science and technology, digital modulation signals source is proposed by people, and it is first at a letterFully integrated numeral, vector, analog-modulated function in number source. For various digital standard and various numeral tuneSystem provides comprehensive modulation capability. Existing digital modulation signals method is mainly any by a binary channelsWave producer is realized, simultaneously by using interpolate value calculate and ensure that by Sampling techniques waveform is accurate, andMeet the test request of wireless digital communication system now by the mode storing sample of dark storage depth.Realizing at present variable symbol rate vector signal is mainly to realize by the clock of D/A converter.

But realize by the clock of D/A converter the clock that variable symbol speed needs postorder processing moduleAlso synchronous change, and between module, time delay is difficult to control, so how to realize a kind of simple and controlled change codeRate vector signal becomes present problem demanding prompt solution.

Summary of the invention

In view of above-mentioned analysis, the present invention aims to provide a kind of implementation method of variable symbol rate vector signalAnd device, effectively having avoided adopting the clock of D/A converter to realize variable symbol speed needs postorder to process mouldThe clock of piece is the problem of synchronous change also.

Object of the present invention is mainly achieved through the following technical solutions:

An implementation method for variable symbol rate vector signal, comprising:

The signal receiving is modulated to mapping and process, obtain I, Q two-way modulation signal;

Dui Mei road modulation signal forms respectively filtering processing, eliminates between the chip rate of each road modulation signalInterference;

Each road modulation signal after treatment shaping filter is carried out to sigma-delta modulating transformation, obtain predetermined chip rateOutput signal;

The output signal of the predetermined chip rate obtaining is carried out to digital filtering, further eliminate between chip rateInterference and the digitlization residual modulation that brings of little transformation of variables disturb;

Described I road after digital filtering and described Q road modulation signal are carried out to Digital Modulation and obtain a road modulationSignal, and Digital Modulation Hou mono-road modulation signal is carried out to D/A conversion, obtain a road analog signal;

This analog signal is mixed on expection frequency.

Preferably, each road modulation signal after treatment shaping filter is carried out to sigma-delta modulating transformation, be scheduled toThe step of the output signal of chip rate specifically comprises:

Each road modulation signal after treatment shaping filter is carried out to integer insert handling and decimal insert handling,Obtain the output signal of predetermined chip rate.

Preferably, each road modulation signal after treatment shaping filter being carried out to integer insert handling and decimal insertsEnter to process, the step that obtains the output signal of predetermined chip rate specifically comprises:

If the integer part of insertion rate is N, fractional part is .F;

Insertion rate in Dui Mei road is calculated respectively as follows:

N₁(Z)=.F(Z)+(1-Z^-1)E_q1(Z)；

N₂(Z)=-E_q1(Z)+(1-Z^-1)E_q2(Z)；

……

N_m(Z)=-E_qm-1(Z)+(1-Z^-1)E_qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N_outFor: N_out=[N.F(Z)+(1-Z^-1)^mE_qm], wherein [] is for retaining integerThe implication of part;

Wherein, Z is Laplce's variable, E_q1-E_qmFor quantizing noise signal, m=1,2,3,4 or 5.

Preferably, the signal receiving described in comprises noise sequence, standard code data or User Defined numberAccording to.

The present invention is a kind of implement device of variable symbol rate vector signal also, comprising:

IQ modulating unit, for the signal receiving is modulated to mapping, obtains I, Q two-way modulation signal;

Shaping filter unit, for forming respectively filtering place to described I road and described Q road modulation signalReason, eliminates the interference between the chip rate of each road modulation signal;

Variable plug-in unit, for adjusting the described I road after described shaping filter cell processing and described Q roadSignal processed carries out respectively sigma-delta modulating transformation, obtains the output signal of predetermined chip rate;

Digital filtering unit, defeated for the predetermined chip rate that obtains after described variable plug-in unit is processedGo out signal and carry out digital filtering, further eliminate the digitlization that interference between chip rate and little transformation of variables bringResidual modulation disturbs;

Digital Modulation unit, for adjusting the described I road after described digital filtering cell processing and described Q roadSignal processed carries out Digital Modulation and obtains a road modulation signal;

D/A converter unit, for by described Digital Modulation cell processing Digital Modulation Hou mono-road modulation signalCarry out D/A conversion, obtain a road analog signal, and this analog signal is mixed on expection frequency.

Preferably, described variable plug-in unit specifically for, by modulation letter in each road after treatment shaping filterNumber carry out integer insert handling and decimal insert handling, obtain the output signal of predetermined chip rate.

Preferably, described variable plug-in unit specifically for, the integer part of establishing insertion rate is N, fractional partBe divided into .F;

Insertion rate in Dui Mei road is calculated respectively as follows:

N₁(Z)=.F(Z)+(1-Z^-1)E_q1(Z)；

N₂(Z)=-E_q1(Z)+(1-Z^-1)E_q2(Z)；

……

N_m(Z)=-E_qm-1(Z)+(1-Z^-1)E_qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N_outFor: N_out=[N.F(Z)+(1-Z^-1)^mE_qm], wherein [] is for retaining integerThe implication of part;

Wherein, Z is Laplce's variable, E_q1-E_qmFor quantizing noise signal, m=1,2,3,4 or 5.

Preferably, the signal receiving described in comprises noise sequence, standard code data or User Defined numberAccording to.

Beneficial effect of the present invention is as follows:

The present invention has carried a kind of implementation method and device of variable symbol rate vector signal, modulates change by sigma-deltaChange and can obtain fast insertion rate, further obtain output signal, and this kind of modulation can obtain multipleModulation format, the large-scale chip rate of high-resolution, the research and development that can be communication equipment, chip, terminal withAnd production maintenance provides Vector Modulation signal.

Other features and advantages of the present invention will be set forth in the following description, and, part from explanationIn book, become apparent, or understand by implementing the present invention. Object of the present invention and other advantages canRealize and obtain by specifically noted structure in write description, claims and accompanying drawing.

Brief description of the drawings

Fig. 1 is the flow chart of the implementation method of variable symbol rate vector signal in the embodiment of the present invention 1;

Fig. 2 is sigma-delta modulating transformation figure in the embodiment of the present invention 1;

Fig. 3 is that orthogonal PSK in the embodiment of the present invention 1 (QPSK) modulation format planisphere is hinted obliquely at;

Fig. 4 is that in the embodiment of the present invention 1,8 system phase shift keyings (8PSK) modulation format planisphere is hinted obliquely at;

Fig. 5 is 16 ary quadrature amplitude keying (16QAM) modulation format planispheres in the embodiment of the present invention 1Hint obliquely at;

Fig. 6 is the implement device schematic diagram of variable symbol rate vector signal in the embodiment of the present invention 2.

Detailed description of the invention

Specifically describe the preferred embodiments of the present invention below in conjunction with accompanying drawing, wherein, accompanying drawing forms the application onePart, and together with embodiments of the present invention for explaining principle of the present invention.

Embodiment 1

The embodiment of the present invention provides a kind of implementation method of variable symbol rate vector signal, referring to Fig. 1, and bagDraw together: S101, by the signal receiving modulate mapping process, obtain I, Q two-way modulation signal;

The signal receiving described in the embodiment of the present invention comprises that noise sequence, standard code data or user are certainlyDefinition data.

S102, Dui Mei road modulation signal form respectively filtering processing, eliminate the code element of each road modulation signalInterference between speed;

S103, each road modulation signal after treatment shaping filter is carried out to sigma-delta modulating transformation, obtain output letterNumber chip rate;

Wherein, the shaping filter in the embodiment of the present invention is treated to FIR(FiniteImpulseResponse,Having limit for length's unit impulse response) shaping filter processes to eliminate intersymbol interference and digitlization residual modulation disturbs;

In the embodiment of the present invention, each road modulation signal after treatment shaping filter is carried out integer insert handling andDecimal insert handling, obtains integer part and the fractional part of the chip rate of output signal, as shown in Figure 2,Wherein this step specifically comprises:

If the integer part of the chip rate of output signal is N, fractional part is .F;

The insertion rate of Dui Mei road modulation signal is calculated respectively as follows:

N₁(Z)=.F(Z)+(1-Z^-1)E_q1(Z)；

N₂(Z)=-E_q1(Z)+(1-Z^-1)E_q2(Z)；

……

N_m(Z)=-E_qm-1(Z)+(1-Z^-1)E_qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N_outFor: N_out=[N_div], wherein [] is for retaining the implication of integer part;

Wherein, Z is Laplce's variable, E_q1-E_qmFor quantizing noise signal, m=1,2,3,4 or 5.

S104, Jiang Mei road modulation signal carry out digital filtering, further eliminate interference between chip rate and littleThe digitlization residual modulation that transformation of variables brings disturbs;

S105, the described I road after digital filtering and described Q road modulation signal are carried out to Digital Modulation obtain oneRoad modulation signal, and Digital Modulation Hou mono-road modulation signal is carried out to D/A conversion, obtain a road simulation letterNumber;

Be this owing to modulating mapping processing, shaping filter processing and digital filtering and Data Modulation processThe known technology in field, the present invention does not improve these contents at receiver side, so locate not describe in detail.

S106, by this analog signal be mixed to expection frequency on.

The embodiment of the present invention can obtain output signal data speed and code element fast by sigma-delta modulating transformationSpeed ratio, obtain integer part and the fractional part of insertion rate, and this kind of modulation can obtain multiple tuneForm processed, the large-scale chip rate of high-resolution, can be communication equipment, chip, terminal research and development andProduce maintenance Vector Modulation signal is provided.

It in Fig. 3-5, is the reference point planisphere of QPSK, 8QPSK and 16QAM. QPSK is modulated to two ratiosA special corresponding multiple real number, I is real, Q is plural imaginary part. In the time of test, reception signalPlanisphere respectively with the distributional class of Fig. 3-5 seemingly. It is the variable symbol rate vector signal of the embodiment of the present inventionThe signal quality of implementation method is higher.

Embodiment 2

The embodiment of the present invention is in multiple standards, more modulation form, chip rate changes on a large scaleIn vector signal source, solve fully integrated numeral, vector, analog-modulated function in a signal source,Comprehensive modulation capability is provided, has comprised various digital standard WCDMA, CMDA2000, TD-SCDMA etc.,Various Digital Modulation FSK, PSK, QAM etc. Meet the test request of wireless digital communication system now.A kind of high accuracy, high-resolution variable chip rate vector signal method for generation and device are described in this embodiment.To comprise 10 modules: data flow generation module, IQ modulation is hinted obliquely at, FIR shaping filter module, integer are insertedEnter module, decimal insert module, digital filtering module, Digital Modulation, D/A conversion module, up-converter moduleWith sigma-delta modulating transformation module. The present invention first carries out IQ modulation by data flow according to modulation format and hints obliquely at; ThenFIR wave filter shaping filter; Insert through integral multiple again, utilize sigma-delta modulating transformation unit controls decimal to insertUnit completes decimal and doubly inserts function, make chip rate that vector signal occurs without with D/A conversion timeClock hook, just can realize high accuracy, high-resolution; Through digital filtering unit, eliminate sigma-delta modulating transformation bandThe digitlization residual modulation coming, finally gives digital modulation module, modulates the signal on carrier wave, passes through D/AChange modulation signal is simulated, then upconvert to radio frequency output. This contrive equipment mainly applies to communication and establishesWhen the research and development such as standby, chip, terminal, production and maintenance, provide the numeral of Vector Modulation signal, certification authority to adjustThe occasions such as the test of signal authentication processed, communication device. Specifically carry out as follows:

(1) apparatus of the present invention are first by data flow generation module, produce PN sequence, standard code data,Or User Defined data;

(2) IQ modulation is hinted obliquely at module and is carried out data according to modulation format and hint obliquely at, and forms IQ two-way modulation signal;

(3) through FIR molding filtration module, IQ two-way modulation signal is carried out to FIR molding filtration, eliminateBetween data chips, disturb;

(4) first carrying out integral multiple by integer insert module according to the requirement of the chip rate of output signal insertsEnter;

(5) through decimal insert module, the speed of output signal output is adjusted into the time clock rate that D/A converts againRate;

(6) sigma-delta modulating transformation unit object control decimal insert module realizes I circuit-switched data stream Idata, Q roadData flow Qdata resampling, reaches the 5th step object.

The concrete model of sigma-delta modulating transformation unit as shown in Figure 2, has adopted m stable single order loop to formCascade form, integer part N and the fractional part .F of the insertion rate of input expection, E_qIt is quantizing noise. IntegrationThe transfer function of device is 1/ (1-Z^-1), the transfer function of differentiator is 1-Z^-1, Z is in discrete time-domainLaplace variable, integrator uses accumulator to complete, and full amount is overflowed as its output, and this process is one and getsModular arithmetic, feedback quantity is a time delay Z of unit^-1, loop relation is as follows:

N₁(Z)=.F(Z)+(1-Z^-1)E_q1(Z)；

N₂(Z)=-E_q1(Z)+(1-Z^-1)E_q2(Z)；

N_m(Z)=-E_qm-1(Z)+(1-Z^-1)E_qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Output insertion rate N_outFor: N_out=[N.F(Z)+(1-Z^-1)^mE_qm]_Round

I circuit-switched data stream I like this_data, Q circuit-switched data stream Q_dataAfter decimal insert module, form new I wayAccording to stream I_newdata, Q circuit-switched data stream Q_newdata；

(7) pass through again FIR digital filtering module, eliminate the numeral that intersymbol interference and sigma-delta modulating transformation bringChange residual modulation, Finite Impulse Response filter design is main consider in frequency response in band, band ripple, Out-of-band rejection etc. because ofElement, the analysis quality of guarantee signal is eliminated the digitlization residual modulation that sigma-delta modulating transformation brings simultaneously.

(8) digital modulation module produces modulation signal according to following formula;

S_data=I_newdata*A*sin2πf_ct+Q_newdata*A*cos2πf_ct；

Wherein A is carrier amplitude, f_cFor carrier frequency, t is the sampling time, S_dataFor Digital ModulationThe modulation signal that module produces;

(9) convert IQ numeral digital modulation signals to analog signal, signal carrier by D/A conversion moduleFrequency is f_c, wherein D/A conversion module clock f_A/DFor signal(-) carrier frequency f_cIntegral multiple;

(10) by up-converter module, signal is mixed on the Frequency point of expection needs, produces like this vector and adjustSignal processed meets the demand that real work is carried out.

Embodiment 3

The embodiment of the present invention provides a kind of implement device of variable symbol rate vector signal, referring to Fig. 6, and bagDraw together:

IQ modulating unit, for the signal receiving is modulated to mapping, obtains I, Q two-way modulation signal;

Shaping filter unit, for forming respectively filtering place to described I road and described Q road modulation signalReason, eliminates the interference between the chip rate of each road modulation signal;

Variable plug-in unit, for adjusting the described I road after described shaping filter cell processing and described Q roadSignal processed carries out respectively sigma-delta modulating transformation, obtains the output signal of predetermined chip rate;

Digital filtering unit, defeated for the predetermined chip rate that obtains after described variable plug-in unit is processedGo out signal and carry out digital filtering, further eliminate the digitlization that interference between chip rate and little transformation of variables bringResidual modulation disturbs;

Digital Modulation unit, for adjusting the described I road after described digital filtering cell processing and described Q roadSignal processed carries out Digital Modulation and obtains a road modulation signal;

D/A converter unit, for by described Digital Modulation cell processing Digital Modulation Hou mono-road modulation signalCarry out D/A conversion, obtain a road analog signal, and this analog signal is mixed on expection frequency.

Wherein, described variable plug-in unit specifically for, the integer part of establishing the chip rate of output signal isN, fractional part is .F;

The insertion rate of Dui Mei road modulation signal is calculated respectively as follows:

N₁(Z)=.F(Z)+(1-Z^-1)E_q1(Z)；

N₂(Z)=-E_q1(Z)+(1-Z^-1)E_q2(Z)；

……

N_m(Z)=-E_qm-1(Z)+(1-Z^-1)E_qm(Z)；

$N_{\mathrm{div}}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\mathrm{\Σ}}}{\left({1-Z}^{-1}\right)}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{\left({1-Z}^{-1}\right)}^m{E}_{\mathrm{qm}};$

Obtain exporting insertion rate N_outFor: N_out=[N.F(Z)+(1-Z^-1)^mE_qm], wherein [] is for retaining integerThe implication of part; Wherein, Z is Laplce's variable, E_q1-E_qmFor quantizing noise signal, m=1,2,3,4 or 5.

In sum, the embodiment of the present invention has been carried a kind of implementation method and dress of variable symbol rate vector signalPut, can obtain fast the data rate and chip rate ratio of output signal by sigma-delta modulating transformation, to obtain final productTo integer part and the fractional part of insertion rate, and this kind of modulation can obtain more modulation form, high scoreThe large-scale chip rate of the rate of distinguishing, can be the research and development of communication equipment, chip, terminal and producing maintenance providesVector Modulation signal.

The above, be only preferably detailed description of the invention of the present invention, but not office of protection scope of the present inventionBe limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in, can be easilyThe variation of expecting or replacement, within all should being encompassed in protection scope of the present invention. Therefore, protection of the present inventionScope should be as the criterion with the protection domain of claims.

Claims (8)

1. an implementation method for variable symbol rate vector signal, is characterized in that, comprising:

The signal receiving is modulated to mapping and process, obtain I, Q two-way modulation signal;

Dui Mei road modulation signal forms respectively filtering processing, eliminates between the chip rate of each road modulation signalInterference;

Each road modulation signal after treatment shaping filter is carried out to sigma-delta modulating transformation, obtain predetermined chip rateOutput signal;

The output signal of the predetermined chip rate obtaining is carried out to digital filtering, further eliminate between chip rateInterference and the digitlization residual modulation that brings of little transformation of variables disturb;

Described I road after digital filtering and described Q road modulation signal are carried out to Digital Modulation and obtain a road modulationSignal, and Digital Modulation Hou mono-road modulation signal is carried out to D/A conversion, obtain a road analog signal;

This analog signal is mixed on expection frequency.

2. method according to claim 1, is characterized in that, by each road after treatment shaping filterModulation signal carries out sigma-delta modulating transformation, and the step that obtains the output signal of predetermined chip rate specifically comprises:

Each road modulation signal after treatment shaping filter is carried out to integer insert handling and decimal insert handling,Obtain the output signal of predetermined chip rate.

3. method according to claim 2, is characterized in that, by each road after treatment shaping filterModulation signal carries out integer insert handling and decimal insert handling, obtains the output signal of predetermined chip rateStep specifically comprises:

If the integer part of insertion rate is N, fractional part is .F;

Insertion rate in Dui Mei road is calculated respectively as follows:

N₁(Z)＝.F(Z)+(1-Z^-1)E_q1(Z)；

N₂(Z)＝-E_q1(Z)+(1-Z^-1)E_q2(Z)；

……

N_m(Z)＝-E_qm-1(Z)+(1-Z^-1)E_qm(Z)；

$N_{div}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\Σ}}{(1-Z^{-1})}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{(1-Z^{-1})}^m{E}_{qm};$

Obtain exporting insertion rate N_outFor: N_out＝[N.F(Z)+(1-Z^-1)^mE_qm], wherein [] is for retaining integerThe implication of part;

Wherein, Z is Laplce's variable, E_q1-E_qmFor quantizing noise signal, m=1,2,3,4 or 5.

4. according to the method described in claim 1-3 any one, it is characterized in that, described in the letter that receivesNumber comprise noise sequence, standard code data or User Defined data.

5. an implement device for variable symbol rate vector signal, is characterized in that, comprising:

IQ modulating unit, for the signal receiving is modulated to mapping, obtains I, Q two-way modulation signal;

Shaping filter unit, for forming respectively filtering place to described I road and described Q road modulation signalReason, eliminates the interference between the chip rate of each road modulation signal;

Variable plug-in unit, for adjusting the described I road after described shaping filter cell processing and described Q roadSignal processed carries out respectively sigma-delta modulating transformation, obtains the output signal of predetermined chip rate;

Digital filtering unit, defeated for the predetermined chip rate that obtains after described variable plug-in unit is processedGo out signal and carry out digital filtering, further eliminate the digitlization that interference between chip rate and little transformation of variables bringResidual modulation disturbs;

Digital Modulation unit, for adjusting the described I road after described digital filtering cell processing and described Q roadSignal processed carries out Digital Modulation and obtains a road modulation signal;

D/A converter unit, for by described Digital Modulation cell processing Digital Modulation Hou mono-road modulation signalCarry out D/A conversion, obtain a road analog signal, and this analog signal is mixed on expection frequency.

6. device according to claim 5, is characterized in that,

Described variable plug-in unit specifically for, each road modulation signal after treatment shaping filter is carried out wholeCount insert handling and decimal insert handling, obtain the output signal of predetermined chip rate.

7. device according to claim 6, is characterized in that,

Described variable plug-in unit specifically for, the integer part of establishing insertion rate is N, fractional part is .F;

Insertion rate in Dui Mei road is calculated respectively as follows:

N₁(Z)＝.F(Z)+(1-Z^-1)E_q1(Z)；

N₂(Z)＝-E_q1(Z)+(1-Z^-1)E_q2(Z)；

……

N_m(Z)＝-E_qm-1(Z)+(1-Z^-1)E_qm(Z)；

$N_{div}\left(Z\right)=N\left(Z\right)+\underset{i=1}{\overset{m}{\Σ}}{(1-Z^{-1})}^{i-1}{N}_i\left(Z\right)=N.F\left(Z\right)+{(1-Z^{-1})}^m{E}_{qm};$

Obtain exporting insertion rate N_outFor: N_out＝[N.F(Z)+(1-Z^-1)^mE_qm], wherein [] is for retaining integerThe implication of part;

Wherein, Z is Laplce's variable, E_q1-E_qmFor quantizing noise signal, m=1,2,3,4 or 5.

8. according to the device described in claim 5-7 any one, it is characterized in that, described in the letter that receivesNumber comprise noise sequence, standard code data or User Defined data.