CN202334461U - Vector signal source plug-in type structure module based on peripheral extensible interface (PXI) bus - Google Patents
Vector signal source plug-in type structure module based on peripheral extensible interface (PXI) bus Download PDFInfo
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- CN202334461U CN202334461U CN 201120372118 CN201120372118U CN202334461U CN 202334461 U CN202334461 U CN 202334461U CN 201120372118 CN201120372118 CN 201120372118 CN 201120372118 U CN201120372118 U CN 201120372118U CN 202334461 U CN202334461 U CN 202334461U
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Abstract
The utility model discloses a vector signal source plug-in type structure module based on a peripheral extensible interface (PXI) bus. The vector signal source plug-in type structure module comprises a PXI interface circuit 1, a baseband signal generation circuit 2, a digital-to-analog conversion circuit 3, a frequency synthesis circuit 4, an import quota (IQ) orthogonal vector modulation circuit 5 and an adaptive logic circuit (ALC) control and vector signal source output circuit 6 as well as an external plug-in E which are combined together to form a modular structural whole. According to a software radio technology and an integrated circuit modular structure design theory, a math model is constructed; and a microwave and high speed digital processing chip is used for setting frequency, amplitude and power of a required vector signal source so as to perform real-time calculation, generation, modulation and output. From the process, the optimal shielding, grounding, decoupling, filtering and leakage preventing optimizing design is adopted, so that characteristics of rational layout, compact structure, ingenious installation, high expandability, high adaptability, high reliability and the like are realized; requirements of the current digital communication system on automatic test and analysis can be met completely; and a demand for development of a communication technology is met.
Description
Technical field
The utility model relates to a kind of signal source module, particularly a kind of vector signal source card insert type construction module based on the PXI bus.
Background technology
Since the PXI bussing technique comes out, developed widely based on the Auto-Test System of PXI bus.PXI bus vector signal source also occurs thereupon and obtains extensive application.Present domestic this series products that do not have.External main by the PXI-5670 vector signal generator of NI company and the PXI3020 radio-frequency signal generator of Aeroflex company.
According to the description of NI official website, NI PXI-5670 is a medelling 2.7GHz RF vector signal generator, and its power and flexibility can be satisfied product development and make omnidistance user demand from being designed into.The random waveform that NI PXI-5670 can carry out true 16 bit resolutions of 100MS/s speed 512MB internal memory and 20MHz real-time bandwidth takes place.PXI-5670 can generate self-defined and modulation format standard, comprises AM, FM, PM, ASK, FSK, MSK, GMSK, PSK, QPSK, PAM and QAM.PXI-5670 has LabVIEW version NI modulation kit, and its function and instrument can be used for generation, analysis, the visualization of signal, also can be used for processing standard and self-defining numeral and analog-modulated pattern.
The PXI3020 radio-frequency signal generator reference frequency output 250MHZ of Aeroflex company is to 2.5GHZ; Output level scope-120 arrives+5dBm; Digital modulation is used the 28MHZ radio frequency bandwidth, and the automatic waveform generator of double-channel is a 32M sampling point (128MB), generates softwarecompatible with the IQ data; The digital IQ modulation input of real-time is for low noise 3010/3011PXI RADIO FREQUENCY SYNTHESIZER provides LO input.
Above-mentioned two product baseband signals part all adopts the random waveform emergence pattern; Need to use as software such as IQ data generation software calculate baseband waveform in advance, and store plate into and carry in the internal memory, the playback through waveform obtains modulation signal; Its waveform calculating and download time are longer; And its wave shape playback length depends on that plate carries the size of memory size, in the test that needs long wave shape sequence to produce, uses, and how not enough storage is.
In the present platform product at home, in the majority with PXI data acquisition equipment and generation equipment, like PXI data collecting card, PXI waveform generator etc., this type is simple based on the application of PXI bus.And the existing P XI vector source module mode that all adopts random waveform to take place, its waveform calculates with download time longer, and wave shape playback length receives plate to carry the restriction of memory size size, is difficult to apply.
Summary of the invention
The purpose of the utility model is exactly in order to overcome the deficiency of above-mentioned prior art, and a kind of vector signal source card insert type construction module based on the PXI bus of reasonable in design, dependable performance is provided.
In order to achieve the above object, the technical scheme of the utility model employing is:
A kind of vector signal source card insert type construction module based on the PXI bus; Include PXI interface circuit 1, baseband signal generative circuit 2, D/A converting circuit 3, frequency synthesizer circuit 4, IQ orthogonal vector modulation circuit 5 and ALC control and the plug-in card E of vector signal source follower circuit 6 together with peripheral hardware, combining constitutes a modular construction integral body.Wherein:
Said PXI interface circuit 1 is the PCI+FPGA framework, be provided with pci interface chip U1, fpga chip U2 and local clock chip U3, and the address of U1, data and control port is connected with the PXI bus through plug-in card E directly; The HPI mouth of dsp chip U5 directly is connected in the HPI mouth of U1 and the baseband signal generative circuit 2; And fifo chip U6 directly is two-way the connection in U2 and the baseband signal generative circuit 2.
Said PXI interface circuit 1; Include pci interface chip U1, fpga chip U2 and local clock chip U3 again; Adopt the PCI+FPGA framework, and U1 is PCI 9030 interface chips, 32 33MHZ follower's chips of its accord with PCI V2.2 standard; Can make broken transmission speed of PCI up to 132MB/S, support multiplexed and non-multiplexed 32 bit address of local bus/data protocol; U2 is a FPGA XC3S400 chip, it in the PXI bus to triggering the electrical code requirement of bus, the response through the programming of FPGA being accomplished triggering signal and the generation realization PXI interface of triggering signal; U3 is the local clock chip, reaches as high as 60MHZ, to adapt to the requirement of different broken the transmission rates of PCI.
Said baseband signal generative circuit 2 includes dsp chip U5, fpga chip U7 and fifo chip U4 and U6 again, adopts the DSP+FPGA framework; And U5 is DSP TMS320C6416T; 32 process chip directly are connected with the HPI mouth of pci interface chip U1 through the HPI mouth, and via plug-in card E to PXI bus; Accept baseband signal and produce instruction, dynamically generate m sequence spread spectrum yardage word baseband signal; U7 is FPGA XC3S200, in order to accomplish digital baseband signal, produces digital I and digital Q baseband signal; U4 and U6 are FIFO first in first out control chip, in order to realize exchanges data work.
Said D/A converting circuit 3 is binary channels DAC chip U8, adopts the AD9777 chip, converts digital I and digital Q two ways of digital signals into Simulation with I and simulation Q two-way analog signal.
Said frequency synthesizer circuit 4; Include again DDS chip U9, PLL chip U10, LPF chip U11, PD chip U12, VCO chip U13 and/N chip U14; Adopt the DDS+PLL framework, and U9 is Direct Digital Frequency Synthesizers DDS AD9852/Analog Devices chip, so that high-resolution reference to be provided; Again through U10 phase-locked loop pll chip; Together with U14 frequency divider/N chip, U12 synthesizer PD chip, U11 LPF LPF chip and U13 VCO VCO chip, on the carrier frequency of appointment, supply IQ orthogonal vector modulation circuit 5 to use the frequency lock of synthetic source.
Said IQ orthogonal vector modulation circuit 5 is IQ quadrature modulation chip U15, and I, the Q two-way analog baseband signal of D/A converting circuit 3 output is modulated on the carrier frequency that frequency synthesizer circuit 4 provides becomes the Vector Modulation signal.
Said ALC control and vector signal source follower circuit 6; Include ALC modulation chip U16, Burst modulation chip U17, down-conversion chip U18, wave detector chip U19 and attenuator chip U20 again; Will be from the Vector Modulation signal of IQ orthogonal vector modulation circuit 5, its output power levels is exported as the vector signal source through attenuator chip U20 through the fixed ampllitude of ALC modulation chip U16 with other interlock circuits completion signals; The sub-fraction of radiofrequency signal converts direct voltage to through wave detector chip U19 in addition; Constitute loop detection, increase or reduce, realize that tested voltage equates with reference voltage to guarantee radio frequency power output.
The utility model is according to software and radio technique and employing integrated circuit modules structure design principle, and the systems soft ware routine operation on function includes measurement parameter setting and system operation two parts.Wherein measurement parameter is provided with the setting to functions such as frequency, amplitude, modulation parameter, triggering and radio frequency ON/OFF; And system operation can be divided into: online help, data importing, on-line calibration, system information setting, be written into and preserve, printing and macroefficiency and grand is provided with etc.Modular construction on function adopts the chip of high-speed digital signal treatment technology, high-speed digital-analog switch technology, low make an uproar mutually frequency synthesis technique and automatic electric-level control technology and Highgrade integration and miniaturization; Calculate in real time and generate baseband signal; And it is converted to required rf modulated signal, to obtain the different vector signal source from 100KHZ to 3GHZ.On technology, adopt the design of low-power consumption integral layout, surface mount and " drop in " technology make compact conformation; Rationally distributed; Install ingeniously, accomplish that implementation is more flexible, extensibility is easier; Satisfy test of current digit communication system and the requirement of analyzing fully, adapt to the needs of development communication technologies.
Description of drawings
Fig. 1 is the whole electrical schematic diagram of the utility model.
Symbol description among the figure:
The 1st, the PXI interface circuit, wherein U1 is a pci interface chip, and U2 is a fpga chip, and U3 is the local clock chip;
The 2nd, the baseband signal generative circuit, wherein U5 is a dsp chip, and U4 and U6 are fifo chips, and U7 is a fpga chip;
The 3rd, D/A converting circuit, wherein U8 is the DAC chip;
The 4th, frequency synthesizer circuit, wherein U9 is the DDS chip, and U10 is the PLL chip, and U11 is the LPF chip, and U12 is the PD chip, U13 is that VCO chip and U14 are/the N chip;
The 5th, IQ orthogonal vector modulation circuit, wherein U15 is an IQ quadrature modulation chip;
The 6th, ALC control and vector signal source follower circuit, wherein U16 is the ALC modulation chip, and U17 is the Burst modulation chip, and U18 is the down-conversion chip, and U19 is the wave detector chip, U20 is the attenuator chip.
Embodiment
See also shown in Figure 1ly, be the utility model specific embodiment.
As can beappreciated from fig. 1: the utility model includes PXI interface circuit 1, baseband signal generative circuit 2, D/A converting circuit 3, frequency synthesizer circuit 4, IQ orthogonal vector modulation circuit 5 and ALC control and the plug-in card E of vector signal source follower circuit 6 together with peripheral hardware, and combining constitutes a modular construction integral body.Wherein:
Said PXI interface circuit 1 is the PCI+FPGA framework, be provided with pci interface chip U1, fpga chip U2 and local clock chip U3, and the address of U1, data and control port is connected with the PXI bus through plug-in card E directly; The HPI mouth of dsp chip U5 directly is connected in the HPI mouth of U1 and the baseband signal generative circuit 2; And fifo chip U6 directly is two-way the connection in U2 and the baseband signal generative circuit 2.
Said baseband signal generative circuit 2 is the DSP+FPGA framework, is provided with dsp chip U5, fpga chip U7 and fifo chip U4 and U6, and the 2nd pin of U5 directly is connected with the 7th pin of U7; U5 is two-way with U4 and U6 and is connected; U4 is two-way with U7 and is connected; The 11st of U7 directly is connected with 4 pin with the 2nd of the binary channels DAC chip U8 of D/A converting circuit 3 respectively with 13 pin.
Said D/A converting circuit 3 is provided with binary channels DAC chip U8, and it the 15th directly is connected with 7 pin with the 5th of the IQ quadrature modulation chip U15 of IQ orthogonal vector modulation circuit 5 respectively with 17 pin.
Said frequency synthesizer circuit 4 is the DDS+PLL framework; Be provided with DDS chip U9, PLL chip U10, LPF chip U11, PD chip U12, VCO chip U13 and/N chip U14, and the 9th directly being connected with the 3rd pin of U10 and the 7th pin of U12 respectively successively of U9 with 5 pin; Then the 9th of U12 the directly is connected with the 11st pin of U14 and the 12nd pin of U11 respectively with 10 pin successively; And the 13rd pin of U11 directly is connected with the 7th pin of U13; The 9th of U13 directly is connected with the 21st pin of the IQ quadrature modulation chip U15 of the 10th pin of U14 and IQ orthogonal vector modulation circuit 5 respectively with 11 pin successively.
Said IQ orthogonal vector modulation circuit 5 is provided with IQ quadrature modulation chip U15, and the 1st pin of the ALC modulation chip U16 in its 15th pin and ALC control and the vector signal source follower circuit 6 directly is connected.
Said ALC control and vector signal source follower circuit 6; Be disposed with ALC modulation chip U16, Burst modulation chip U17, down-conversion chip U18, wave detector chip U19 and attenuator chip U20, and the output of down-conversion chip U18 is connected directly with the 5th pin of wave detector chip U19 and the 1st pin of attenuator chip U20 respectively directly; Then the 2nd pin of the 7th pin of U19 and U16 directly is connected.
Here, said plug-in card E is 3U PXI 4 groove position standard components, and wherein, 3U is of a size of 100mm * 160mm, and is provided with two connectors, and one is used 1 groove position to be numerical portion, so that the business of 32 PCI local buss to be provided; Another uses 3 groove positions to be analog part, so that the business of 64 PCI transmission and realization PXI electrical characteristic to be provided.
Its basic mechanical design feature is following in the utility model specific embodiment:
One, frequency characteristic
Frequency range 100KHZ～3GHZ
Maximum real-time bandwidth 20MHZ
Parameter frequency 10MHZ
Temperature stability ± 10
-6(optional)
Ageing rate ± 5 * 10
-7/ year
Frequency resolution 1HZ
Two, radio frequency output characteristic
Output power range-130dBm～+ 10dBm
Output amplitude accuracy ± 2dB
Amplitude resolution 0.1dB
Three, modulating characteristic
Analog-modulated FM, AM
Digital modulation FSK, ASK, BPSK, QPSK, 8PSK, 0QPSK, 16QAM, 32QAM, 64QAM, 256QAM and GMSK are optional.
Integrated level based on built-in microwave circuit chip of the utility model and high-speed figure process chip is high; Its electromagnetic environment is abominable; Consider tight electromagnetic compatibility, utilized advanced CAD software, like HP-ADS, HP-HFSS; Set up interference source Mathematical Modeling, coupling model and reception response model etc. and carry out design of Simulation, and adopted best shielding, ground connection, decoupled, filtering and prevent structural manufacturing process optimal design such as signal leakage.In addition, ripe surface mounting technology and multi-layer sheet The Application of Technology also help improving circuit reliability when providing the foundation for the integral miniaturization structure.Also have each chip all to select technical grade low-power consumption product for use, help heat radiation and reduce volume.
Above embodiment is the preferred embodiment of explanation the utility model, in order to the technical characterictic and the exploitativeness of explanation the utility model, is not in order to limit the right of applying for a patent of the utility model; Above simultaneously description should be understood and implemented for knowing those skilled in the art.Therefore, other are not breaking away under the prerequisite that the utility model discloses, and the change of the equivalence of completion or decoration all are included within the described claim.
The utility model is a rare vector signal source card insert type construction module based on the PXI bus, and creative, novelty, practicality and progressive meet the utility application important document, so file an application according to Patent Law.
Claims (6)
1. based on the vector signal source card insert type construction module of PXI bus; Include PXI interface circuit (1), baseband signal generative circuit (2), D/A converting circuit (3), frequency synthesizer circuit (4), IQ orthogonal vector modulation circuit (5) and ALC control and the plug-in card E of vector signal source follower circuit (6) together with peripheral hardware; Combining constitutes a modular construction integral body, it is characterized in that:
Said PXI interface circuit (1) is the PCI+FPGA framework, be provided with pci interface chip U1, fpga chip U2 and local clock chip U3, and the address of U1, data and control port is connected with the PXI bus through plug-in card E directly; The HPI mouth of U1 directly is connected with the HPI mouth of the middle dsp chip U5 of baseband signal generative circuit (2); And U2 directly is two-way the connection with the middle fifo chip U6 of baseband signal generative circuit (2).
2. the vector signal source card insert type construction module based on the PXI bus as claimed in claim 1 is characterized in that:
Said baseband signal generative circuit (2) is the DSP+FPGA framework, is provided with dsp chip U5, fpga chip U7 and fifo chip U4 and U6, and the 2nd pin of U5 directly is connected with the 7th pin of U7; U5 is two-way with U4 and U6 and is connected; U4 is two-way with U7 and is connected; The 11st of U7 directly is connected with 4 pin with the 2nd of the binary channels DAC chip U8 of D/A converting circuit (3) respectively with 13 pin.
3. the vector signal source card insert type construction module based on the PXI bus as claimed in claim 1 is characterized in that:
Said D/A converting circuit (3) is provided with binary channels DAC chip U8, and it the 15th directly is connected with 7 pin with the 5th of the IQ quadrature modulation chip U15 of IQ orthogonal vector modulation circuit ⑸ respectively with 17 pin.
4. the vector signal source card insert type construction module based on the PXI bus as claimed in claim 1 is characterized in that:
Said frequency synthesizer circuit (4) is the DDS+PLL framework; Be provided with DDS chip U9, PLL chip U10, LPF chip U11, PD chip U12, VCO chip U13 and/N chip U14, and the 9th directly being connected with the 3rd pin of U10 and the 7th pin of U12 respectively successively of U9 with 5 pin; Then the 9th of U12 the directly is connected with the 11st pin of U14 and the 12nd pin of U11 respectively with 10 pin successively; And the 13rd pin of U11 directly is connected with the 7th pin of U13; The 9th of U13 directly is connected with the 21st pin of the IQ quadrature modulation chip U15 of the 10th pin of U14 and IQ orthogonal vector modulation circuit (5) respectively with 11 pin successively.
5. the vector signal source card insert type construction module based on the PXI bus as claimed in claim 1 is characterized in that:
Said IQ orthogonal vector modulation circuit (5) is provided with IQ quadrature modulation chip U15, and the 1st pin of the ALC modulation chip U16 in its 15th pin and ALC control and the vector signal source follower circuit (6) directly is connected.
6. the vector signal source card insert type construction module based on the PXI bus as claimed in claim 1 is characterized in that:
Said ALC control and vector signal source follower circuit (6); Be disposed with ALC modulation chip U16, Burst modulation chip U17, down-conversion chip U18, wave detector chip U19 and attenuator chip U20, and the output of down-conversion chip U18 is connected directly with the 5th pin of wave detector chip U19 and the 1st pin of attenuator chip U20 respectively directly; Then the 2nd pin of the 7th pin of U19 and U16 directly is connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120372118 CN202334461U (en) | 2011-09-28 | 2011-09-28 | Vector signal source plug-in type structure module based on peripheral extensible interface (PXI) bus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120372118 CN202334461U (en) | 2011-09-28 | 2011-09-28 | Vector signal source plug-in type structure module based on peripheral extensible interface (PXI) bus |
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| CN202334461U true CN202334461U (en) | 2012-07-11 |
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|---|---|---|---|
| CN 201120372118 Expired - Fee Related CN202334461U (en) | 2011-09-28 | 2011-09-28 | Vector signal source plug-in type structure module based on peripheral extensible interface (PXI) bus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386894A (en) * | 2011-09-28 | 2012-03-21 | 中国人民解放军63963部队 | Vector signal source plug-in card-type structural module based on PCI extension for instrumentation (PXI) bus |
| CN102929758A (en) * | 2012-10-29 | 2013-02-13 | 北京航天测控技术有限公司 | Integrated triggering route device for PXI intelligent testing platform equipment |
| CN113258941A (en) * | 2021-05-11 | 2021-08-13 | 江苏信息职业技术学院 | Vector signal generation module and method |
-
2011
- 2011-09-28 CN CN 201120372118 patent/CN202334461U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386894A (en) * | 2011-09-28 | 2012-03-21 | 中国人民解放军63963部队 | Vector signal source plug-in card-type structural module based on PCI extension for instrumentation (PXI) bus |
| CN102929758A (en) * | 2012-10-29 | 2013-02-13 | 北京航天测控技术有限公司 | Integrated triggering route device for PXI intelligent testing platform equipment |
| CN102929758B (en) * | 2012-10-29 | 2014-09-03 | 北京航天测控技术有限公司 | Integrated triggering route device for PXI intelligent testing platform equipment |
| CN113258941A (en) * | 2021-05-11 | 2021-08-13 | 江苏信息职业技术学院 | Vector signal generation module and method |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120711 Termination date: 20140928 |
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| EXPY | Termination of patent right or utility model |