CN108259038A - A kind of broadband low spurious frequency agility apparatus for frequency synthesizing - Google Patents
A kind of broadband low spurious frequency agility apparatus for frequency synthesizing Download PDFInfo
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- CN108259038A CN108259038A CN201711386665.0A CN201711386665A CN108259038A CN 108259038 A CN108259038 A CN 108259038A CN 201711386665 A CN201711386665 A CN 201711386665A CN 108259038 A CN108259038 A CN 108259038A
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- frequency
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- analog
- bandpass filter
- 3ghz
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
Abstract
The invention discloses a kind of broadband low spurious frequency agility apparatus for frequency synthesizing.The device includes the FPGA circuitry module, digital analog converter, the first bandpass filter, the one 2 frequency multiplier, the second bandpass filter, the 2nd 2 frequency multiplier and the third bandpass filter that are sequentially connected；Further include sampling clock generation circuit module, the clock signal input terminal of the output terminal connection digital analog converter of sampling clock generation circuit module；The apparatus for frequency synthesizing is based on digital analog converter, target number signal is converted to target simulation signal, and the target simulation signal and 3GHZ analog clock signals are carried out frequency synthesis, it is expected analog signal with generation and exported using digital analog converter.The present invention realizes the purpose of broadband low spurious frequency agility frequency synthesis.
Description
Technical field
The present invention relates to frequency synthesis technique more particularly to a kind of broadband low spurious frequency agility apparatus for frequency synthesizing.
Background technology
Frequency synthesis technique is one of key technologies of electronic systems such as radar, communication, many modern electronic equipments and is
The function realization of system all relies on the performance of frequency synthesizer used.The development of radar and electronic warfare also requires modern electricity simultaneously
Subsystem is further promoted from a series of indexs such as the precision, stability and flexibility of frequency, and major requirement is extremely low phase
Position noise, the frequency switching time being exceedingly fast and high noise restraint.All stepping up to carry out high-precision high-speed agile both at home and abroad
The exploitation and development of frequency synthesizer.
Existing apparatus for frequency synthesizing is roughly divided into direct digital frequency synthesizer (DDS) and indirect frequency synthesizer
(frequency synthesizer of phase locking).DDS device has the characteristics that high frequency resolution, is exceedingly fast frequency agility speed, flexibility are high, but
It uses digital structure, spuious more and can not predict, and operating frequency range is also limited, no more than 1GHz.It is difficult to meet work
Journey needs.Phase-locked loop apparatus is a phase closed-loop control system, and input and output are realized using phase feedback control principle
Phase synchronization realizes the purpose of adjustment output frequency.Phase-locked loop apparatus is to make output signal by multiple phase bit comparison and amendment
Phase reaches dynamic lock-out state with frequency reference source phase, so as to produce high-precision frequency signal.Due to needing repeatedly ratio
Dynamic lock-out state is mutually can be only achieved, therefore frequency switching time is slower, about tens us.
Invention content
The technology of the present invention solves the problems, such as：Overcome spuious more and nothing existing for existing direct digital frequency synthesizer
Frequency switching time existing for the problem of method is predicted, and operating frequency range is also limited and existing indirect frequency synthesizer is slow
The problem of, provide a kind of broadband low spurious frequency agility apparatus for frequency synthesizing.
The present invention technical solution be：A kind of broadband low spurious frequency agility apparatus for frequency synthesizing, including FPGA circuitry
Module, sampling clock generation circuit module, digital analog converter, the first bandpass filter, the one 2 frequency multiplier, the second bandpass filter,
22 frequency multipliers and third bandpass filter；
The FPGA circuitry module generates target number signal, and the digital-to-analogue is supplied to turn the target number signal
Parallel operation；
100MHZ analog signals are converted to 3GHZ analog clock signals by the sampling clock generation circuit module, and by described in
3GHZ analog clock signals are supplied to the digital analog converter；
The target number signal is converted to the target simulation signal that frequency is f by the digital analog converter, and by described in
Target simulation signal carries out frequency synthesis with the 3GHZ analog clock signals, and letter is simulated to generate expectation of the frequency as f+3GHZ
Number and export；
The first bandpass filter removal clutter it is expected in analog signal；
One 2 frequency multiplier will remove noise wave removing after two frequency multiplication of expectation analog signal for frequency be 2f+6GHZ
Analog signal；
Second bandpass filter removes the harmonic wave in the analog signal of the 2f+6GHZ；
Two frequency multiplication of analog signal of 2f+6GHZ after removing harmonic wave is 4f+12GHZ for frequency by the 2nd 2 frequency multiplier
Analog signal；
The third bandpass filter removes the harmonic wave in the analog signal of the 4f+12GHZ.
Further, the frequency f of the target simulation signal is：0.8GHz≤f≤1.2GHz.
The present invention has the advantages that compared with prior art：
For the present invention by proposing a kind of broadband low spurious frequency agility apparatus for frequency synthesizing, which is based on digital-to-analogue
Converter doubles the frequency synthesis mode of frequency by high-speed DAC, and target number signal is converted to target using digital analog converter
Analog signal, and the target simulation signal and 3GHZ analog clock signals are subjected to frequency synthesis, it is expected to simulate letter with generation
Number and export, realize the effect of broadband low spurious frequency agility frequency synthesis.
Description of the drawings
Fig. 1 is a kind of structure chart of broadband low spurious frequency agility apparatus for frequency synthesizing in the embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is it is understood that described herein
Specific embodiment be used only for explain the present invention rather than limitation of the invention.It also should be noted that for the ease of
It describes, part related to the present invention rather than entire infrastructure is illustrated only in attached drawing.
Fig. 1 is a kind of structure chart of broadband low spurious frequency agility apparatus for frequency synthesizing in the embodiment of the present invention, reference chart
1, a kind of broadband low spurious frequency agility apparatus for frequency synthesizing provided in this embodiment, including FPGA circuitry module 1, sampling clock electricity
Road module 2, digital analog converter 3, the first bandpass filter 4, the one 2 frequency multiplier 5, the second bandpass filter 6, the 2nd 2 frequency multiplier 7
With third bandpass filter 8.
The FPGA circuitry module 1 generates target number signal, and the target number signal is supplied to the digital-to-analogue
Converter 3；
100MHZ analog signals are converted to 3GHZ analog clock signals by the sampling clock generation circuit module 2, and by described in
3GHZ analog clock signals are supplied to the digital analog converter 3；
The target number signal is converted to the target simulation signal that frequency is f by the digital analog converter 3, and by described in
Target simulation signal carries out frequency synthesis with the 3GHZ analog clock signals, and letter is simulated to generate expectation of the frequency as f+3GHZ
Number and export；
First bandpass filter 4 removes the clutter in the expectation analog signal；
One 2 frequency multiplier 5 will remove noise wave removing after two frequency multiplication of expectation analog signal for frequency be 2f+6GHZ
Analog signal；
Second bandpass filter 6 removes the harmonic wave in the analog signal of the 2f+6GHZ；
Two frequency multiplication of analog signal of 2f+6GHZ after removing harmonic wave is 4f+12GHZ for frequency by the 2nd 2 frequency multiplier 7
Analog signal；
The third bandpass filter 8 removes the harmonic wave in the analog signal of the 4f+12GHZ.
Optionally, the frequency f of the target simulation signal is：0.8GHz≤f≤1.2GHz.
A kind of operation principle of broadband low spurious frequency agility apparatus for frequency synthesizing provided in this embodiment is as follows：
Target number signal is generated using FPGA circuitry module 1；Using sampling clock generation circuit module 2,100MHZ is simulated
Signal is converted to 3GHZ analog clock signals.
The target number signal and the 3GHZ analog clock signals are transmitted to digital analog converter 3.
Using the digital analog converter 3, the target number signal is converted into the target simulation signal that frequency is f；
In the digital analog converter 3, the target simulation signal and the 3GHZ analog clock signals are subjected to frequency synthesis, with generation
The expectation analog signal of f+3GHZ.
In first bandpass filter 4, the clutter in the expectation analog signal of the f+3GHZ is removed.
The expectation analog signal of the f+3GHZ after noise wave removing will be gone through the one 2 frequency multiplier 5 and the second bandpass filter
6, it carries out two frequencys multiplication of first time and removes harmonic management；Again through the 2nd 2 frequency multiplier 7 and third bandpass filter 8, the is carried out
Secondary two frequencys multiplication and remove harmonic management；The analog signal of final output 4f+12GHZ.
Specifically：
FPGA circuitry module 1 generates target number signal, and the target number signal is supplied to digital analog converter 3；
100MHZ analog signals are converted to 3GHZ analog clock signals by sampling clock generation circuit module, and the 3GHZ clocks are simulated and are believed
Number it is supplied to digital analog converter 3.
The target number signal is converted to target simulation signal by digital analog converter 3, for example, the target simulation signal
It is closed for the analog signal of (1 ± 0.2) GHz, and by the target simulation signal and the 3GHZ analog clock signals into line frequency
Into to generate expectation analog signal and export.It is described it is expected to simulate letter when the target simulation signal is (1 ± 0.2) GHz
Number be (4 ± 0.2) GHz.
First bandpass filter, 4 receives frequency is the expectation analog signal of (4 ± 0.2) GHz, and removes the expectation simulation
Clutter in signal.
The expectation analog signal of (4 ± 0.2) GHz of noise wave removing is gone to be carried out through the one 2 frequency multiplier 5 at the frequency multiplication of first time
Reason, becomes (8 ± 0.4) GHz；Harmonic management is carried out through the second bandpass filter 6.Then, the analog signal of (8 ± 0.4) GHz
Again through the 2nd 2 frequency multiplier 7, secondary process of frequency multiplication is carried out, becomes (16 ± 0.8) GHz；It is carried out through third bandpass filter 8
Remove harmonic management.Finally, by the output terminal of third bandpass filter 8 by the analog signal output of (16 ± 0.8) GHz.
The technical solution of the present embodiment is by proposing a kind of broadband low spurious frequency agility apparatus for frequency synthesizing, the frequency synthesis
Device is based on digital analog converter, and the frequency synthesis mode of frequency is doubled by high-speed DAC, is believed target number using digital analog converter
Target simulation signal number is converted to, and the target simulation signal and 3GHZ analog clock signals are subjected to frequency synthesis, with life
It into expectation analog signal and exports, realizes the effect of broadband low spurious frequency agility frequency synthesis.
Note that it above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiment described here, can carry out for a person skilled in the art various apparent variations,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
It can include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (2)
1. a kind of broadband low spurious frequency agility apparatus for frequency synthesizing, which is characterized in that during including FPGA circuitry module (1), sampling
Clock circuit module (2), digital analog converter (3), the first bandpass filter (4), the one 2 frequency multiplier (5), the second bandpass filter
(6), the 2nd 2 frequency multiplier (7) and third bandpass filter (8)；
The FPGA circuitry module (1) generates target number signal, and the digital-to-analogue is supplied to turn the target number signal
Parallel operation (3)；
100MHZ analog signals are converted to 3GHZ analog clock signals by the sampling clock generation circuit module (2), and by described in
3GHZ analog clock signals are supplied to the digital analog converter (3)；
The target number signal is converted to the target simulation signal that frequency is f by the digital analog converter (3), and by the mesh
It marks analog signal and carries out frequency synthesis with the 3GHZ analog clock signals, to generate expectation analog signal of the frequency as f+3GHZ
And it exports；
First bandpass filter (4) the removal clutter it is expected in analog signal；
One 2 frequency multiplier (5) noise wave removing will be removed after two frequency multiplication of expectation analog signal for frequency be 2f+6GHZ mould
Intend signal；
Second bandpass filter (6) removes the harmonic wave in the analog signal of the 2f+6GHZ；
Two frequency multiplication of analog signal of 2f+6GHZ after removing harmonic wave is 4f+12GHZ for frequency by the 2nd 2 frequency multiplier (7)
Analog signal；
The third bandpass filter (8) removes the harmonic wave in the analog signal of the 4f+12GHZ.
2. low spurious frequency agility apparatus for frequency synthesizing in broadband according to claim 1, which is characterized in that the target simulation
The frequency f of signal is：0.8GHz≤f≤1.2GHz.
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| CN201711386665.0A CN108259038A (en) | 2017-12-20 | 2017-12-20 | A kind of broadband low spurious frequency agility apparatus for frequency synthesizing |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155275A (en) * | 2023-04-19 | 2023-05-23 | 成都世源频控技术股份有限公司 | Broadband fine stepping phase-locked source with repeatable phase |
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| EP1873919A1 (en) * | 2006-06-29 | 2008-01-02 | Nihon Dempa Kogyo Co., Ltd. | Frequency synthesizer |
| CN101552620A (en) * | 2009-05-25 | 2009-10-07 | 刘洛琨 | Method for demodulating reference Chirp ultra- wideband system group based on active frequency spectrum compression code |
| CN202424688U (en) * | 2012-02-29 | 2012-09-05 | 北京无线电计量测试研究所 | Millimeter wave broadband nimble frequency-changing signal source used for personnel security inspection device |
| CN107070464A (en) * | 2017-06-13 | 2017-08-18 | 吉林大学 | A kind of Multi-path synchronous frequency division multiplexing millimeter wave swept-frequency signal generation device and method |
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2017
- 2017-12-20 CN CN201711386665.0A patent/CN108259038A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1873919A1 (en) * | 2006-06-29 | 2008-01-02 | Nihon Dempa Kogyo Co., Ltd. | Frequency synthesizer |
| CN101552620A (en) * | 2009-05-25 | 2009-10-07 | 刘洛琨 | Method for demodulating reference Chirp ultra- wideband system group based on active frequency spectrum compression code |
| CN202424688U (en) * | 2012-02-29 | 2012-09-05 | 北京无线电计量测试研究所 | Millimeter wave broadband nimble frequency-changing signal source used for personnel security inspection device |
| CN107070464A (en) * | 2017-06-13 | 2017-08-18 | 吉林大学 | A kind of Multi-path synchronous frequency division multiplexing millimeter wave swept-frequency signal generation device and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116155275A (en) * | 2023-04-19 | 2023-05-23 | 成都世源频控技术股份有限公司 | Broadband fine stepping phase-locked source with repeatable phase |
| CN116155275B (en) * | 2023-04-19 | 2023-07-28 | 成都世源频控技术股份有限公司 | Broadband fine stepping phase-locked source with repeatable phase |
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Application publication date: 20180706 |