CN104836573B - A kind of synchronized clock system of super large area array CMOS cameras multipath high-speed signal - Google Patents
A kind of synchronized clock system of super large area array CMOS cameras multipath high-speed signal Download PDFInfo
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- CN104836573B CN104836573B CN201510218263.4A CN201510218263A CN104836573B CN 104836573 B CN104836573 B CN 104836573B CN 201510218263 A CN201510218263 A CN 201510218263A CN 104836573 B CN104836573 B CN 104836573B
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Abstract
A kind of synchronized clock system of super large area array CMOS cameras multipath high-speed signal, including work crystal oscillator, with reference to crystal oscillator, T VCXO, PLD FPGA, T the Clock management chips with phase locked looped function, T loop filters, T is positive integer, and each Clock management chip and reference crystal oscillator, VCXO structure, a loop filter constitute a phaselocked loop；For each phaselocked loop, according to the frequency dividing control amount of input, the output frequency of VCXO is divided, R+1 circuit-switched data synchronised clocks are produced.Present system exports homologous reference frequency using one with reference to crystal oscillator, can so export the consistent synchronised clock of T*R roads phase, solves the clock synchronization issue of multiple signals；Meanwhile, use Clock management chip to provide work clock for FPGA and handle corresponding view data with corresponding clock, it is ensured that FPGA output clock and the Complete Synchronization of data phase.
Description
Technical field
The present invention relates to a kind of signal synchronized clock system, the space remote sensing that is particularly suitable for use in satellite large area array cmos image is passed
The view data transmission of sensor camera system.
Background technology
Enhancing increasingly with remote sensing user to the continuous reconnaissance and surveillance demand of high-resolution, large area array cmos sensor is in height
Application advantage in rail remote sensing satellite is gradually highlighted.Because large area array cmos sensor can be while output multi-channel high speed image
Signal, therefore propose higher requirement to data transfer.Transmission needs to use multi-disc high speed number while multipath high-speed signal
Chip is passed, but excessive number of chips will make it that chip layout can not be compact, asks so as to long-distance transmissions inevitably occur
Topic, this can cause it is common changed by the FPGA clock duty cycles transmitted, and clock line is through multiple devices in plate
Shake can be also caused to increase.
Meanwhile, with continuing to develop for remote sensing satellite payload technology, and remote sensing satellite faced it is more and more multiple
Miscellaneous function, the requirement for improving star epigraph gathered data amount and message transmission rate also has become a trend.It is many high
It is all very high that fast number passes requirement of the chip to indices such as dutycycle, the clock jitters of data sync clock.And space environment
Certain deterioration can be caused to the clock quality more than or equal to 100MHz.Temperature change, radiation and strenuous vibration in space are all
It is possible to that the Duty Cycle Distortion of clock, shake can be allowed to increase.In face of so many limiting factor and environmental constraints, clock is improved steady
Fixed degree seems more and more important.
Traditional ground installation clock produces the work clock for simply being inputted crystal oscillator by FPGA and divided after internal DCM
With output, more precise and stable clock can be produced using the IP kernel of DCM+PLL functions.Spoke is resisted yet with space product
Penetrate, the strict demand of the index such as high-low temperature resistant, the FPGA product hierarchies that tradition is used can not be applied to space product, and at present may be used
FPGA products do not possess PLL functions again.Therefore need to design a kind of clock system for meeting Aerospace Standard to solve this
Problem.
Patent CN203563034U proposes a kind of clock duty correction circuit for reducing overshoot and shake, the invention
DCC delay chains are used, its circuit design is not suitable for the field that the present invention is applied.Patent CN102882623A proposes one
Kind of the configurable clock frequency synthesizer based on FPGA, this device can produce the clock signal of various frequencies, but by
All be in the clock signal of generation it is homologous, the dutycycle of its signal and shake all depend primarily on crystal oscillator be supplied to FPGA when
Clock quality, therefore shake can not be reduced, also uncontrollable dutycycle.
The content of the invention
Present invention solves the technical problem that being：Overcoming the deficiencies in the prior art, there is provided a kind of super large area array CMOS cameras
The synchronized clock system of multipath high-speed signal, transmission provides high stable while can be for space flight multipath high-speed sensed image signal
The synchronised clock of degree.
The present invention technical solution be：A kind of synchronised clock system of super large area array CMOS cameras multipath high-speed signal
System, including work crystal oscillator, with reference to crystal oscillator, T VCXO, the individual clocks with phase locked looped function of PLD FPGA, T
Managing chip, T loop filter, T is positive integer, wherein：
Work crystal oscillator：Work clock is provided for PLD FPGA；
PLD FPGA：On the basis of the work clock for the crystal oscillator that works, T*R is received from cmos image sensor
Road view data, R is positive integer, while producing T frequency dividing control amount PTAnd T Clock management chip is delivered to respectively, each
Frequency dividing control amount PTOne Clock management chip of correspondence；T circuit-switched data synchronised clocks are obtained from T Clock management chip, using every
Data sync clock exports on the R roads received in view data to outside R corresponding with the circuit-switched data synchronised clock all the way
Number passes chip, and chip is passed per one number of correspondence of view data all the way；
Clock management chip：Shared T, each Clock management chip and reference crystal oscillator, VCXO, a loop are filtered
Ripple device constitutes a phaselocked loop；For each phaselocked loop, according to the frequency dividing control amount P of inputT, to the output frequency of VCXO
Rate carries out PTFrequency dividing, produces R+1 circuit-switched data synchronised clocks, and wherein R circuit-switched datas synchronised clock is delivered to and the Clock management core respectively
The corresponding outside R numbers of piece pass chip, and remaining data sync clock all the way delivers to PLD FPGA；
With reference to crystal oscillator：Homologous reference clock is produced for T Clock management chip；
VCXO：Shared T, the charge pump signal exported according to corresponding Clock management chip produces respective phase
Clock signal, and feed back to Clock management chip；
Loop filter：Shared T, the HFS of the charge pump signal is filtered out, the voltage signal control after filtering
The frequency of oscillation of VCXO processed.
Described R >=2, and T >=2.The frequency of described R+1 circuit-switched data synchronised clocks is not less than 100M.Described ring
Path filter is the passive low ventilating filter of three ranks.
The advantage of the present invention compared with prior art is：
(1) present invention locks phase using Clock management chip with constituting one with reference to crystal oscillator, VCXO and loop filter
Ring, the high-frequency clock of phase stabilization can be provided a system to by FPGA control；
(2) clock system can be expanded as while being filtered using T Clock management chip, VCXO and loop in the present invention
Ripple device, exports homologous reference frequency with reference to crystal oscillator using one, can so export the consistent synchronised clock of T*R roads phase, solves
The certainly clock synchronization issue of multiple signals；
(3) use Clock management chip to provide work clock for FPGA in the present invention to replace being supplied directly to by external crystal-controlled oscillation
Work clock, corresponding view data is handled with corresponding clock, it is ensured that FPGA output clock and data phase it is complete
It is complete synchronous；
(4) position relationship that clock passes chip with number can be adjusted flexibly using Clock management chip in the present invention, reduced
Transmission range, simultaneously because Clock management chip drives ability is big, therefore is not susceptible to change in duty cycle.So solve multichannel
The asking due to a series of number of chips increases and brings board design placement-and-routings that high speed signal simultaneous transmission is faced
Topic, so as to avoid long-distance transmissions so that common changed by the FPGA clock duty cycles transmitted, clock line is worn
Cross multiple devices in plate and cause the problem of shake increases；
(5) loop filter in the present invention uses the passive loop filter of three ranks, can be compared with compared to second order filter
The ripple that good reduction reference frequency feedthrough is brought；It can simplify design and cost compared to active filter, and avoid active
The noise of extra loop is brought in active device part in structure, so as to control VCXO to produce stable feedback ginseng
Clock is examined, the stability that whole synchronized clock system produces high-speed clock signal is improved.
Brief description of the drawings
Fig. 1 is the theory of constitution figure of present system；
Fig. 2 is the cut-away view of Clock management chip；
Fig. 3 is the circuit diagram of third order PLL path filter；
Fig. 4 is a kind of concrete application frame diagram of present system.
Embodiment
The characteristics of being transmitted according to super large area array CMOS camera images, while output multi-channel high speed signal, the present invention is devised
One including work crystal oscillator A, with reference to B, T VCXOs of crystal oscillator, PLD FPGA, T with phase locked looped function
The clock system of Clock management chip, T loop filter, concrete structure is as shown in Figure 1.The system is respectively using T clock
Managing chip, VCXO, loop filter, and a reference crystal oscillator B, collectively form T phase-locked loop structures, can be simultaneously defeated
Go out the consistent synchronised clock of T*R roads phase, wherein T >=2, R >=2, T and R is positive integer, and R is each Clock management chip energy
Enough synchronised clock ways exported to R follow-up high-speed digital transmission chip.
Clock management chip is generally required configures its mode of operation by FPGA.After system electrification, it is necessary first to clock pipe
Reason chip is configured, and allows it according to predetermined mode of operation.When providing work to FPGA by work crystal oscillator A first
Clock Clock0, FPGA generation configuration words give Clock management chip, configure its normal work.FPGA, which is received, simultaneously comes from cmos image
The view data of sensor transmissions, and cache.The configuration words inputted in Clock management chip can control SPI logics selector to select
Logical divide ratio, the clock signal of frequency, is exported to FPGA and R high-speed digital transmission chip respectively needed for producing.FPGA, which is received, to be come
From the clock signal Clock1 of Clock management chip, the view data of caching is exported to corresponding high-speed digital transmission chip.It is described
Clock management chip can using the model such as CDC421A100, CDCE62005 of TI companies chip.
As shown in Fig. 2 being the cut-away view of Clock management chip, phase discriminator (PFD), SPI logic selectors are included
(SPI LOGIC), reference clock frequency divider (REF Diriver M), feedback divider (VCXO Diriver N), P frequency dividers,
Phase discriminator input selector (FB_MUX) and output frequency selector (Y0_MUX, Y1_MUX ...).SPI logic selectors can
Identification configuration words control the parameter M of reference clock frequency divider, parameter N, the P frequency divider (P Diriver) of feedback divider
Crossover frequency selected by parameter P, phase discriminator input selector and output frequency selector.Wherein configuration words set divide ratio will
Mode is reasonably divided according to formula (1) design alternative, final output frequency can select VCXO according to system requirements
VCXO P crossover frequencies output.VCXO_IN is the frequency of VCXO feedback, by Clock management chip output charge pump signal
CP_OUT adjusts output VCXO_IN after VCXO phase and feeds back to Clock management chip to VCXO.REF_CLK is ginseng
Examine the clock frequency of crystal oscillator B inputs.M, N, P are the divide ratio controlled by configuration words, and its size is according to three below equation
Calculating can determine that.
VCXO_IN/REF_CLK=(N*P)/M (1)
P=VCXO_IN/fout (2)
Fp=REF_CLK/M (3)
F in formulaoutFor output frequency；fpFor phase demodulation frequency, phase demodulation frequency is bigger, and phase error is bigger, so phase demodulation frequency
Should be as far as possible small, but the locking time of smaller phaselocked loop is longer, therefore the size of phase demodulation frequency will compromise selection.
Fig. 3 show third order PLL path filter circuit diagram, and the wave filter is used for filtering out charge pump signal CP_OUT high frequency
Part.If
Its transmission function is
Wherein s=j ω.R represents resistance value, and C represents capacitance.
The most important two indices of loop filter, one is loop bandwidth, and one is phase margin.Loop bandwidth compared with
Small, loop can suppress the noise from reference source, phase discriminator and frequency divider, but the noise of VCXO can not be pressed down well
System；But loop bandwidth it is larger when, although have preferable suppression to the noise of VCXO, but to the noise suppressed of other modules
It is poor, increase noise.Loop bandwidth can be typically taken between the 1/10-1/20 of reference frequency.Can by adjust resistance R2 come
Change loop bandwidth value.Phase margin is a very important performance parameter in circuit design, is mainly used to weigh negative-feedback
The stability of system, it can be regarded as to get over increased phase place change, phase margin before system enters unstable state
Greatly, system is more stable, but causes response speed to slow down, it is therefore necessary to which stability and response speed are considered, selection one
The individual phase margin for comparing compromise.For the system, the selection of phase margin is preferably between 55 ° to 80 °.
In order to ensure to be supplied to the clock of high-speed digital transmission chip consistent with the data signal phase that FPGA is exported, Clock management
Chip to export simultaneously all the way clock to FPGA as work clock Clock1.FPGA exports R with Clock1 as synchronised clock
Road view data gives corresponding R high-speed digital transmission chip.
If necessary to use two panels Clock management chip, each Clock management chip will export all the way clock signal to
FPGA, as work clock, is Clock1 and Clock2 respectively.FPGA need respectively with Clock1 and Clock2 as it is synchronous when
Clock output 2R roads single ended clock is supplied to corresponding 2R high-speed digital transmission chip (each clock one way of correspondence is passed).Two panels with
On similarly analogize.
For example, the view data that large area array cmos image sensor has five passages is exported simultaneously, data rate is
250MHz, as shown in Figure 4.In order to improve reliability, the high-speed digital transmission chip of 10 certain models is used to be connect in master backup mode
Receive, the receiving velocity that number passes chip requirement is not less than 100MHz.Certain model Clock management chip every can at most provide 5 tunnels
The single-ended LVCMOS clock signals of LVPECL differential clocks or 10 tunnels.Due to Clock management chip each pair clock output pin A/B
There is identical unmodifiable phase equalization, therefore make Y1_A, Y1_B in their active and standby single ended clock outputs each other, such as Fig. 2.
According to above-mentioned principle, this programme need to use two panels timer manager to provide clock signal.In order to keep clock signal sum it is believed that
Number phase concord, every timer manager export to number pass clock signal chip while, will also to FPGA provide one
Road clock, FPGA produces number with corresponding clock and passes signal output to corresponding number biography chip.
During system starts, FPGA first receives the 100MHz clocks that crystal oscillator A is provided, and produces configurable clock generator managing chip
2 groups of configuration words, allow the 4 road LVCMOS clock signals and LVPECL all the way of first Clock management chip output 100MHz frequencies
Differential clocks Clock1, allows the 6 road LVCMOS clock signals and all the way of second Clock management chip output 100MHz frequencies
LVPECL differential clocks Clock2.The 40MHz clock signal conducts that two panels Clock management chip is exported with same reference crystal oscillator B
Reference clock, enters line phase with respective 400MHz VCXO and is compared.The system phase demodulation frequency selects 200KHz, according to formula
(1) (2) (3) obtain parameter M, N, P respectively M=200, N=250, P=4.10 tunnels that two panels Clock management chip is produced
LVCMOS clock signals are directly output to high-speed digital transmission chip, when FPGA receives two difference from two panels Clock management chip
Clock, gives the master backup that number passes chip 1,2 the 1st, 2 circuit-switched datas with Clock1, number is given the 3rd, 4,5 circuit-switched datas with Clock2
Pass the master backup of chip 3,4,5.
Being shown according to actual test result, the digital dock manager (DCM) in fpga chip can be operated in 48~
Between 450MHz, the measured result of its input and output jitter tolerance is in 250ps~300ps.Export the dutycycle of clock
Measured result is 52%~55%.And the Clock System Design method of the present invention is used, can control output clock jitter
In 50ps or so, output clock duty cycle is strict controlled between 49%~51%.Therefore, can be very big using present system
Ground improves clock quality, reduces influence of the clock jitter to system signal noise ratio.
The content not being described in detail in description of the invention belongs to the known technology of those skilled in the art.
Claims (4)
1. a kind of synchronized clock system of super large area array CMOS cameras multipath high-speed signal, it is characterised in that：Including work crystal oscillator,
With reference to crystal oscillator, T VCXO, PLD FPGA, T the Clock management chips with phase locked looped function, T loops
Wave filter, T is positive integer, wherein：
Work crystal oscillator：Work clock is provided for PLD FPGA；
PLD FPGA：On the basis of the work clock for the crystal oscillator that works, T*R roads figure is received from cmos image sensor
As data, R is positive integer, while producing T frequency dividing control amount PTAnd T Clock management chip, each frequency dividing are delivered to respectively
Controlled quentity controlled variable PTOne Clock management chip of correspondence；T circuit-switched data synchronised clocks are obtained from T Clock management chip, using per all the way
Data sync clock exports on the R roads received in view data to outside R numbers corresponding with the circuit-switched data synchronised clock
Chip is passed, chip is passed per one number of correspondence of view data all the way；
Clock management chip：Shared T is individual, each Clock management chip and reference crystal oscillator, VCXO, a loop filter
Constitute a phaselocked loop；For each phaselocked loop, according to the frequency dividing control amount P of inputT, the output frequency of VCXO is entered
Row PTFrequency dividing, produces R+1 circuit-switched data synchronised clocks, and wherein R circuit-switched datas synchronised clock is delivered to and the Clock management chip pair respectively
The outside R numbers answered pass chip, and remaining data sync clock all the way delivers to PLD FPGA；
With reference to crystal oscillator：Homologous reference clock is produced for T Clock management chip；
VCXO：Shared T, the charge pump signal exported according to corresponding Clock management chip produces the clock of respective phase
Signal, and feed back to Clock management chip；
Loop filter：Shared T, the HFS of the charge pump signal is filtered out, the voltage signal control pressure after filtering
Control the frequency of oscillation of crystal oscillator.
2. a kind of synchronized clock system of super large area array CMOS cameras multipath high-speed signal according to claim 1, it is special
Levy and be：Described R >=2, and T >=2.
3. a kind of synchronized clock system of super large area array CMOS cameras multipath high-speed signal according to claim 1 or 2, its
It is characterised by：The frequency of described R+1 circuit-switched data synchronised clocks is not less than 100M.
4. a kind of synchronized clock system of super large area array CMOS cameras multipath high-speed signal according to claim 1 or 2, its
It is characterised by：Described loop filter is the passive low ventilating filter of three ranks.
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105847714B (en) * | 2016-05-24 | 2018-10-09 | 中国科学院长春光学精密机械与物理研究所 | The delay of CMOS input image datas corrects system |
| CN106131461A (en) * | 2016-06-28 | 2016-11-16 | 湖北久之洋红外系统股份有限公司 | A kind of multiple image sensor synchronous control system and image processing module |
| CN108881718B (en) * | 2018-06-22 | 2021-05-04 | 中国科学院长春光学精密机械与物理研究所 | Synchronous control method of multi-group TDI CMOS imaging system |
| CN109068023B (en) * | 2018-07-26 | 2020-12-18 | 西安理工大学 | Synchronous control system and control method for reading circuit of super-large area array image sensor |
| CN110635802B (en) * | 2019-09-29 | 2023-09-08 | 深圳开立生物医疗科技股份有限公司 | FPGA-based transmitting frequency adjusting system and ultrasonic equipment |
| CN111106828B (en) * | 2019-12-16 | 2023-04-28 | 天津津航计算技术研究所 | Communication system clock distribution management circuit |
| CN110958018A (en) * | 2019-12-19 | 2020-04-03 | 中船重工（武汉）凌久电子有限责任公司 | Design method for generating multi-frequency synchronous clock system |
| CN111736576B (en) * | 2020-08-03 | 2020-11-20 | 天津美腾科技股份有限公司 | Image time synchronization controller testing tool and testing method thereof |
| CN112350718B (en) * | 2020-09-25 | 2023-06-27 | 苏州华兴源创科技股份有限公司 | Clock source circuit, chassis and multi-chassis cascading system |
| CN113671432A (en) * | 2021-09-08 | 2021-11-19 | 上海电气(集团)总公司智惠医疗装备分公司 | Magnetic resonance spectrometer system for realizing clock synchronization of magnetic resonance spectrometer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7812659B1 (en) * | 2005-08-03 | 2010-10-12 | Altera Corporation | Clock signal circuitry for multi-channel data signaling |
| CN104155630A (en) * | 2014-08-08 | 2014-11-19 | 浙江大学 | High-speed data record storage and playback system |
| CN104536284A (en) * | 2014-10-10 | 2015-04-22 | 北京空间机电研究所 | Clock management circuit of remote sensing camera |
-
2015
- 2015-04-30 CN CN201510218263.4A patent/CN104836573B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7812659B1 (en) * | 2005-08-03 | 2010-10-12 | Altera Corporation | Clock signal circuitry for multi-channel data signaling |
| CN104155630A (en) * | 2014-08-08 | 2014-11-19 | 浙江大学 | High-speed data record storage and playback system |
| CN104536284A (en) * | 2014-10-10 | 2015-04-22 | 北京空间机电研究所 | Clock management circuit of remote sensing camera |
Non-Patent Citations (2)
| Title |
|---|
| Design and FPGA implementation of PLL-based quarter-rateclock and data recovery circuit;Mohammed H.Alser;et al;《2012 4th International Conference on Intelligent and Advanced Systems》;20120614;第2卷;第825-830页 * |
| FPGA中数字时钟管理模块的设计;王鲁豫;《中国优秀硕士学位论文全文数据库 信息科技辑》;20110315(第3期);第I135-331页 * |
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