TW201601566A - Synchronizable network - Google Patents

Abstract

The present invention relates to a synchronizable network comprising a plurality of nodes. The present invention specifically relates to clock distribution and self-organized synchronization in large scale networks. The present invention also relates to a method for synchronizing Network comprising a plurality of nodes. It is an objective of the present invention to provide a solution for synchronizing a network comprising a plurality of interconnected nodes that provides a stable synchronized state, especially for large scale networks. This is achieved in that the signal transmission speed and the length of each interconnection of the network is configured to cause a delay of the signals received by a node from the other node of the interconnection which is larger than one millionth of the free-running period of the controllable oscillator of the receiving node such that Network-wide synchronization of oscillators is achieved for all nodes of the network in a continuous self-organized process in interaction with the other node of the network.

Description

Synchronizable network

The invention also relates to a method of synchronizing a network comprising a plurality of nodes.

Today, hundreds of thousands of cores are integrated on a single wafer. To ensure a stable and well-defined system, the common synchronization strategy is to time the blocks separately. Global Non-Synchronous Area Synchronization (GALS) timing produces a simplified clock tree and allows clock generation on the wafer to minimize the number of I/O pins required. Therefore, within a heterogeneous MPSoC, the clock frequency and supply voltage can be dynamically adjusted for each core. However, flexibility, scalability, and other benefits of GALS timing technology are accompanied by performance penalties caused by additional communication latency between disjoint clock domains. This exactly describes the bottleneck of the GALS solution.

In contrast, for high performance micro-multiprocessors, a global synchronization design as shown in Figure 1 is used, in which all cores (11) of the timing network (13) share a master clock (12). Compared to GALS timing, the communication latency between cores is greatly reduced. Considering the next generation of MPSoC, it is necessary to synchronize very large wafer areas. To implement the primary clock base clock tree, see Figure 1, the clock signal within the MPSoC must be transmitted over a few millimeters, which is a well-known bottleneck for speed, power, and reliability. In addition, traditional global synchronous timing circuits have become too difficult for MPSoCs with many cores, increasing wafer size, and line-induced delays. In addition, the clock tree consumes a lot of power, which is critical to mobile communication systems.

Two timing technologies, GALS and globally synchronized design, limit their large-scale network, such as a large number of multiple input multiple output (MIMO) systems and MPSoC.

Another strategy for network synchronization and clock distribution is related to the self-organizing synchronization of distributed network nodes that lack the transmission master clock.

FM Orsatti, R. Carareto, JRC Piqueira, IET Circuit Devices Syst., 2008, Vol. 2, No. 6, pp. 495-508, "Mutually connected phase-locked loop networks: dynamical models and design parameters" The use of interconnected structures rather than master-slave structures to allocate clock signals is related. The mathematical model of the interconnected digital PLL network is numerically studied with the types of phase detectors limited to the JK positive and negative phase detectors and the charge pump phase detector. With the settings described in Orsatti et al., by using XOR PD, it is not possible to establish an interconnected network with three or more nodes. In addition, the number of signal transmissions is explicitly ignored. Depending on the individual node parameters and network connectivity, considering the node as a nonlinear oscillator with nonlinear coupling conditions, the conditions of the synchronization state are derived.

F.M. Orsatti, R. Carareto, J.R.C. Piqueira, Signal Processing 90 (2010) 2072-2082 "Multiple synchronous states in static delay-free interact connected PLL networks" relates to interconnected networks of digital phase-locked loops. The mathematical model of the interconnected digital PLL network is numerically studied with the types of phase detectors limited to the JK forward and reverse phase detectors. Even for static networks without delay, the network may have different synchronization states.

However, these files deal with networks that do not exist or can ignore time delays between oscillators. In addition, in both documents, the type of phase detector is limited to JK forward and/or charge pump phase detectors. Therefore, the presented solution does not include networks with different types of phase detectors, and cannot be applied to networks that exhibit significant time delays between network nodes.

WO 2013/178237 A1 relates to a communication network of interconnected communication nodes, each node comprising an oscillator coupled to an oscillator of another communication node. The oscillator generates a periodic sync pulse. The communication node further includes a transmitter for transmitting the synchronization pulse to the other communication node; a receiver for receiving the synchronization pulse from the other communication node; and a synchronization unit for receiving the synchronization pulse from the other communication node by The phase of the sync pulse generated by the oscillator is adjusted to synchronize the phase of the sync pulse generated by the oscillator with the sync pulse received from other communication nodes. The synchronization unit adjusts the phase of the sync pulse generated by the oscillator in such a way as to ensure guaranteed full network synchronization for all communication nodes of the communication network.

However, WO 2013/178237 A1 explicitly limits the transmission time delay of the synchronization pulses between the communication nodes to one eighth of the oscillator period. Therefore, this disclosure does not provide a suitable solution for networks exhibiting transmission time delays exceeding one-eighth of the oscillator period, such as high-integration chip networks. In addition, this solution assumes pulse coupling. Random sync pulse transmission is required to ensure synchronization. Therefore, this solution is not suitable for clock distribution with time-continuous coupling.

US 2009/183019 A1 relates to a system having multiple clock islands, each clocked by a common clock generator. A predetermined amount of clock skew can be introduced by the programmable delay element to blur the instantaneous power supply requirements of the respective logic over time. In addition, additional delays are used to compensate for clock skew between different clock islands for information transfer purposes.

Thus, the purpose of US 2009/183019 A1 is to establish a clock skew in a system with a single clock generator using programmable delay elements.

Here, the synchronization state is related to any state of the network that has a time independent difference between the network nodes. In such a network, each node of the network receives at least one input from another node and transmits its output to at least one other node.

This is achieved by a method of applying a patented range of node networks in accordance with a stand-alone device and a method of synchronizing a network according to an independent method.

The invention relates to a network comprising a plurality of interconnected nodes. The node includes a controllable oscillator that generates a time continuous sync signal for synchronizing a plurality of interconnected nodes of the network. The node further includes a controller for comparing and synchronizing the phase of the time-continuous synchronization signal generated by the controllable oscillator with another node of the slave network by adjusting the frequency of the time-synchronized signal generated by the controllable oscillator The received external time continuously synchronizes the phase of the signal. The time-continuous synchronization signal transmitted by another node delays the external time continuous synchronization signal received from another node of the network by a time delay. Such a delay can satisfy the function of being able to have a synchronized state in such a system. The time delay may be the transmission time delay of the transmission time between the transmission of the external time continuous synchronization signal from the other node and the subsequent reception of the external time continuous synchronization signal of the node. Adjust the connection length of the transmission sync signal and consider the signal transmission speed, tunable transmission time delay. In addition to the transmission time delay, the time delay can also include any tunable additional time delay.

The controller repeatedly adjusts the frequency of the time continuous sync signal generated by the controllable oscillator such that all nodes of the network achieve full network synchronization of the oscillator. Synchronization is thus achieved through the interaction of nodes in the network in a continuous self-organizing process.

The controller can be any control system that has a time continuous sync signal feedback generated by the tunable oscillator.

In particular, the combination of the controller and the controllable oscillator can form a phase locked loop (PLL). A PLL is an electronic component that can synchronize their synchronization signals by evaluating the phase differences of each other and thus adjusting their frequency. The controller includes a phase detector (PD) and a loop filter (LF). The controllable oscillator can be a voltage controlled oscillator (VCO). The phase detector compares the phase of the external time continuous sync signal with the phase of the continuously synchronized signal generated by the controllable oscillator. The tunable signal inverter can be placed in a feedback path between the controllable oscillator and the phase detector, and/or in each input path, and/or at a controllable oscillator and at least another node input Between the output paths.

Using an analog PLL as an example, a model for coupling PLLs with each other is described below. The invention is not limited to analog PLLs.

The VCO outputs a sine wave with a fixed amplitude, which can be set to 1, without loss of generality.

among them Means the phase of the oscillating signal, and Point out the PLL. The phase detector will input an external signal Multiply the output signal of the VCO . The time delay, for example due to the transmission time delay and/or the tunable extra time delay between the PLLs, is due to the delay of the received signal . In addition, the reason for the feedback delay between the VCO and the PD is the delay in the VCO signal. . However, the feedback delay can be zero.

This signal Is filtered by the loop filter

According to the impulse response of LF . LF output A control signal for the VCO is generated. By its inherent frequency The dynamic frequency of the VCO is given by the control signal Modulated

among them Means Time derivative, and It is the sensitivity of the VCO. In equation (2), the first term containing the phase difference describes the frequency component of the signal, and the second term containing the phase sum describes the high frequency component. In order to approximate LF as ideally, we ignore the high frequency components in equation (2). Therefore, the dynamic frequency of the VCO is given below.

among them Is the coupling strength and has a frequency dimension. A cosine function containing phase differences is called a coupling function. This is a closed phase equation for two mutually delayed coupled PLLs.

Equation (5) can be extended for use between coupled oscillators A phase model of a delay coupled PLL. Standard prior art PLLs only process a single input signal. The controller then synchronizes and compares the phase of the time-continuous synchronizing signal generated by the controllable oscillator with the external time received from a plurality of other nodes of the network by adjusting the frequency of the time-synchronized signal generated by the controllable oscillator. The phase of the sync signal.

An aspect of the invention relates to a combiner for combining external time continuous synchronization signals received from other nodes of the network to produce a combined external time continuous synchronization signal. The phase detector compares the phase of the time-continuous synchronizing signal generated by the controllable oscillator with the phase of the combined external time continuous synchronizing signal. The combiner can be part of a phase detector (PD). The combiner can be a positive phase adder. The phase detector (PD) can be a multiplier for analog signals or an XOR gate for digital signals. Alternatively, the phase detector can individually compare the phase of the time continuous sync signal generated by the controllable oscillator with the phase of each external time continuous sync signal to generate a plurality of phase detector signals. The combiner then combines the phase detector signals to control the controllable oscillator.

Used for The phase model of the coupled analog PLL is written as

The connection between the PLLs is made up of a coupling matrix Description, where ,among them pointed out as well as the connection between. Coupling strength by input signal The number is standardized. For having Global coupling coupling of the oscillator and for conditions with periodic boundary conditions The nearest neighbor coupling on the lattice gives two examples of the coupling matrix:

For the global in-phase synchronization state, the phase of all oscillators is satisfied

among them Means the set frequency of the synchronization state. Set frequency Satisfy among them And . This result is valid for any coupling topology if there are no disjoint sets of nodes.

One aspect of the invention relates to the time delay between tuning coupled PLLs. For any time delay between the coupled synchronizers, a stable in-phase synchronization solution equation (8) with a global frequency Ω cannot be achieved. Time delay is a design parameter and can be tuned by the design of additional delays and networks. The node may include a delay for inducing additional time delays to the transmission time delay. The time delay effectively induces a frequency dependent phase shift to the sync signal, and if properly tuned, the coupling characteristics are changed to make a stable sync state possible. The retarder can be any device suitable for inducing such a phase shift. The retarder may need to be specifically tuned for each input path.

The time delay can be the order in which the oscillator period can be controlled. In particular, it can exceed one eighth of the controllable oscillator period. Therefore, a network with a large delay can be synchronized.

The node can further include for inducing a feedback delay in the feedback path between the control oscillator and the phase detector Feedback delay. The feedback delay compensates for the time delay. The node may further comprise a tunable signal inverter for inducing signal inversion, in each input path and/or in a feedback path between the controllable oscillator and the phase detector and/or in a controllable oscillator A tunable signal inverter in the output path between. Set frequency depends on time delay And feedback delay difference between.

In addition, tunable time delay To minimize the perturbation response rate To achieve the in-phase synchronization state with maximum stability as will be explained.

For being disturbed Disturbed phase,

among them Is small, equation (6) is ,in Expanding to the first-order Taylor expansion produces linear motion of the disturbance,

among them

Proposed index Substituted in equation (11), where Is a complex number, and the characteristic equation is given by

among them Is the impulse response of LF Laplace conversion. If and only if all the answers to equation (13) are The in-phase synchronous state equation (8) is linearly stable. No time delay And feedback delay When there is no stable synchronization, there can be: for Equation (12) implies And equation (13) only allows Solution. This points to neutral stability where any small disturbances persist. Therefore, only time delay And feedback delay The non-zero difference allows for a stable in-phase synchronization state. It should be noted that the combined effects of the two in-phase synchronizations (non-attractive coupling, time delay induced by transmission delay) produce the desired technical effect.

The solution can be obtained by rewriting equation (13) in vector form.

among them And standardized coupling matrix ,among them . For any answer , the scalar coefficient on the left side of equation (14) is Characteristic value. The strategy for solving equation (14) is therefore to solve the equation . Phase corresponding feature vector Associated with a linearized dynamic decoupling set of perturbation modes.

For those that do not necessarily have the same specifications The induction of the phase model of a coupled PLL is written

Here Is the natural frequency, Is the coupling strength, Is the impulse response of LF, Is a coupling function (which is - periodic), Is the feedback delay of the PLL ,as well as Is PLL as well as The time delay between.

The synchronization state with time independent phase difference between PLLs is given by

Where Ω means the set frequency, and PLL Phase offset. If such a state exists, the set frequency Ω and the phase offset Meet the following Equation

among them And . For disturbance Disturbed phase,

among them Is small, equation (15) is ,in The expansion to the first-order Taylor expansion produces a linear dynamic of the disturbance. Perturbation response rate as shown previously The characteristic equation can be obtained as

among them Means The derivative of its independent variable.

For the synchronization state to be stabilized, the above must be satisfied The same conditions.

Therefore, for the desired set frequency Ω , tunable and feedback delay Combined time delay To maximize the disturbance rejection by optimizing the perturbation response rate To reach, see equation (19). In addition, for optimizing the disturbance response rate Further design parameters are controllable oscillator natural frequencies Coupling strength Coupling function And the impulse response of the filter inside the controller (ie loop filter) .

For systems where the specifications of individual PLLs vary only slightly, the natural frequency can be Coupling strength Coupling function Impulse response And feedback delay Set to Independent values to approximate system behavior well. For systems where the inter-connectivity specifications between PLLs vary only slightly, by delaying the time Set to as well as Independent values to approximate system behavior well.

An aspect of the invention relates to optimizing the perturbation response by tuning the cutoff frequency of the loop filter. Many loop filters can be given an impulse response by a gamma distribution To describe,

among them Is a gamma function, Corresponding to the order of the loop filter used, and Together, according to Determine the cutoff frequency . The conversion function of the filter is given by

The time continuous synchronization signal can be a digital signal or an analog signal. The node can be a timing node, and the time continuous synchronization signal can be a clock signal for the timing device. The invention is further related to a network comprising a plurality of interconnected, continuously coupled nodes. The network can be designed to produce the desired perturbation response rate and/or set frequency. The design parameters of the network are the distance between the node and another node that contributes to the time delay. The time delay corresponding to the optimal perturbation response rate can be achieved by adjusting only the distance and/or adjusting the additional time delay induced by the delay.

The invention is further related to a method for synchronizing a network comprising a plurality of interconnected nodes. The method includes generating a time continuous synchronization signal in each node; transmitting a time continuous synchronization signal of each node to at least one other respective node of the network; receiving a delay of at least another node from the network in each node The external time continuously synchronizing the signals; and synchronizing the phase of the continuous synchronizing signal in each node by repeatedly adjusting the frequency of the time continuous synchronizing signal to synchronize the phase of the signal with the external time received from at least one other node, so that Full network synchronization is achieved for all nodes of the network in a continuous self-organizing process.

For the example of a digital PLL with XOR PD, the coupling function Given ,among them Is a trigonometric function whose Fourier representation is given by

For an example where the individual PLLs of the same specification and the PLL are interconnected and there is no delay in the feedback path, the set frequency Ω of the in- phase synchronization state is satisfied.

Disturbance response rate for this example The characteristic equation is given by

Referring to FIG. 3, the PLL includes a phase detector 31, a loop filter 32, and a generation time continuous timing signal. Voltage controlled oscillator 33. The PLL synchronizes the phase of the timing signal generated by the VCO 33 with the external timing signal by adjusting the timing signal frequency of the VCO. Phase of the transmission (which is delayed by the transmission time indicated by the transmission delay 34) Delay) to achieve full network synchronization of the VCO for all timing nodes of the dynamic timing network. In order to do this, the phase detector 31 compares the external timing signals. Phase and timing signal generated by VCO 33 Phase to generate phase detector signal . This produces a control signal for the VCO 33 after filtering by the loop filter 32. .

Figure 4 shows the node of Figure 3, which includes an additional delay 45 in the input path to adjust the time delay. Transmission time delay And extra time delay Time delay . Phase detector 41 compares external delay timing signals with additional delay Phase and timing signal generated by VCO 43 Phase to generate phase detector signal . This produces a control signal for the VCO 43 after filtering by the loop filter 42 . A stable solution to the aggregate frequency of the network can be achieved by appropriately inducing additional time delays.

Figure 5 shows multiple external timing signals , , ,..., Timing node. Each input path includes an individual delay 551, 552, 553, 554 that induces an additional time delay for the transmission time delay indicated by the transmission delays 541, 542, 543, 544. Each phase detector 511, 512, 513, 514 individually compares the timing signals generated by the controllable oscillator 53 The phase is phased with each external clock signal to produce multiple phase detector signals. Combiner 56 combines the phase detector signals to produce a combined phase detector signal to control the controllable oscillator. The combined phase detector signal is filtered by loop filter 52 to generate a control signal for the VCO . The PLL of each timing node thus adjusts the frequency of the timing signals of each VCO to achieve full network synchronization of the VCO for all timing nodes of the dynamic timing network. A stable solution to the aggregate frequency of the network can be achieved by appropriately inducing individual additional time delays for each input path.

Figure 6 shows multiple external timing signals , , ,..., Timing node. Each input path includes an individual delay 651, 652, 653, 654 that induces an additional time delay for the transmission time delay indicated by the transmission delays 641, 642, 643, 644. In contrast to the embodiment in which the combiner shown in FIG. 5 incorporates multiple phase detector signals, in this embodiment, combiner 66 incorporates a plurality of external timing signals to produce a combined external timing signal. The phase detector 61 compares the phase of the timing signal generated by the VCO 63 with the phase of the combined external timing signal to generate a phase detector signal. . This produces a control signal for the VCO 63 after filtering by the loop filter 62. .

Figure 7 shows the timing node of Figure 4, which includes a feedback delay 77 for introducing a time delay in the feedback loop in the input path of the PLL including the phase detector 71, the loop filter 72, and the VCO 73, A tunable inverter 78 for introducing signal inversion in the feedback path between the controllable oscillator and the phase detector, and a tuning inverter 79. The feedback delay can be induced to compensate for the time delay.

Individual time delay in any of the above embodiments Is the design parameter. As will be explained with reference to Fig. 8, a stable synchronization state can be achieved by appropriate selection, and Fig. 8 shows the time delay of the timing network. The in-phase of the function and the global frequency of the inverted sync state The timing network includes two analog PLLs as timing nodes. The inverse synchronization state is characterized by . The solid line represents a stable solution and the dashed line represents an unstable solution. Thus, for the desired global frequency of the timing network, a time delay can be selected for a given natural frequency of the VCO to achieve the desired synchronization state and the global frequency of the network. If no additional time delay is induced, the transmission time delay corresponds to the time delay. Therefore, by selecting the distance between the network coupling nodes accordingly, a transmission time delay for generating a stable synchronization state can be achieved. The graph of Figure 8 shows the following system parameters: VCO natural frequency Coupling strength , LF order , LF cutoff frequency . The frequency of the different schemes can be obtained by letting the timing network evolve from different initial phase differences. For example, for All initial phase differences result in in-phase synchronization, see Figure 9, where the zero order parameter means no synchronization, and the value of 壹 implies full synchronization. For both scenarios being stable time delay values, the clock network evolves toward a solution based on its initial conditions. In addition, the time delay, natural frequency, coupling strength, filter response, feedback delay, and state of the inverter can be selected to minimize The perturbation given is minimized, see equation (14).

Figure 10 shows a graph showing the perturbation response rate versus time delay for a timing network comprising two analog PLLs as timing nodes. Corresponding to the coupling matrix of two mutually coupled PLLs Given and having eigenvalues as well as . It shows a distinct minimum in the region of the stabilization scheme, which corresponds to the time delay with respect to the disturbance response rate. It should be mentioned that for the desired global frequency, the maximum perturbation decay of the clock network can be achieved by simultaneously adjusting the time delay of the VCO and the natural frequency, see Figure 8, which takes the curve of the global frequency up or towards Pan down. The coupling strength of the loop filter and the cutoff frequency also affect the stability of the clock network. As in Figure 8, the curves also show the same parameters.

Figure 11 shows the perturbation response rate versus time delay for the timing network of the two analog PLLs as the timing nodes for different cutoff frequencies of the loop filter. Therefore, by appropriately tuning the time delay and the cutoff frequency, a minimum disturbance response rate can be achieved.

The present invention proposes an innovative synchronization strategy, particularly for spatially distributed clocks. These clocks are synchronized by a network coupled to a phase-locked loop. An important feature is the time delay in time-continuous coupling between phase-locked loops, which enables synchronization states in the presence of a stable synchronization state with a negligible time delay and a non-attractive coupling mechanism. . Since the transmission time delay is not limited to one eighth of the oscillator period (as in the example of the scheme disclosed in WO 2013/178237 A1), a network with a large time delay between nodes can be synchronized. Important applications are, for example, high-performance MPSoC architectures, distributed antenna arrays, and other large-scale electronic timing systems that utilize time-continuous signal communication. The present invention provides, in particular, a simplified clock network as compared to prior art tree structures. Synchronous networks can therefore have increased energy efficiency due to shorter connections and less amplification. Furthermore, due to the decentralized structure, it exhibits increased robustness against failure of individual components. In addition, the synchronous network is designed for high quality oscillations. Synchronous networks can be implemented using hardware components that are immediately available. Thus, this solution works in an innovative manner with the immediately available hardware, and additionally simplifies clock distribution, thereby reducing power consumption and increasing scalability.

Figure 12 shows the time delay of timing the network. The global frequency of the synchronous phase of the function in phase and phase-locked (in this case, inverting) The timing network includes two digital PLLs as timing nodes. The curve of Fig. 12 is obtained using the phase model of the digital PLL. They are shown for the following system parameters: VCO natural frequency Coupling strength LF order , LF cutoff frequency . The symbols show the data points measured in the experimental setup with the two digital PLLs specified in Figure 22.

Figure 13 shows the time delay of timing the network. The global frequency of the synchronous phase of the function in phase and phase-locked (in this case, inverting) The timing network includes two digital PLLs as timing nodes (with active inverters in the feedback path between the controllable oscillator and the phase detector). The graph of Fig. 13 is obtained using the phase model of the digital PLL. They are shown for the following system parameters: VCO natural frequency Coupling strength LF order , LF cutoff frequency . The symbols show the data points measured in the experimental setup with the two digital PLLs specified in Figure 22.

Figure 14 shows a graph showing the perturbation response rate of the timing network versus the perturbation response rate, the timing network including two digital PLLs as timing nodes. The curve of Fig. 14 is obtained using the phase model of the digital PLL. They are shown for the same parameters as in Figure 12. The symbols show the data points measured in the experimental setup with the two digital PLLs specified in Figure 22.

Figure 15 shows a graph showing the disturbance response rate versus time delay for a timing network that includes two digital PLLs as timing nodes (with a feedback path between the controllable oscillator and the phase detector) Active inverter). The curve of Fig. 15 is obtained using the phase model of the digital PLL. They are shown for the same parameters as in Figure 13. The symbols show the data points measured in the experimental setup with the two digital PLLs specified in Figure 22.

Figure 16 shows the time delay of timing the network. The in-phase of the function and the global frequency of the phase-locked synchronization state Where there is between the coupling nodes The phase difference network consists of nine digital PLLs as timing nodes on a 3x3 square lattice with periodic boundaries. The graph of Fig. 16 is obtained using the phase model of the digital PLL. They are shown for the following system parameters: VCO natural frequency Coupling strength LF order , LF cutoff frequency . The symbols show the data points measured in the experimental setup of nine digital PLLs on a 3x3 square lattice with the periodic boundaries given in Figure 23.

Figure 17 shows the time delay of timing the network. The in-phase of the function and the global frequency of the phase-locked synchronization state Where there is between the coupling nodes The phase difference network consists of nine digital PLLs as timing nodes on a 3x3 square lattice with open boundaries. The graph of Fig. 17 is obtained using the phase model of the digital PLL. They are shown for the following system parameters: VCO natural frequency Coupling strength LF order , LF cutoff frequency . The symbols show the data points measured in the experimental setup of nine digital PLLs on a 3x3 square lattice with specifications for the open boundary given in Figure 23.

Figure 18 shows the timing node of Figure 4 including a tunable inverter 189 for introducing signal inversion in the output path between the controllable oscillator of the PLL and the phase detector of at least one other node. .

Figure 19 shows the timing node of Figure 4 including a tunable inverter 199 for introducing signal inversion in the output path between the controllable oscillator of the PLL and the phase detector of at least one other node. And a tunable inverter 198 for introducing signal inversion in the feedback path between the controllable oscillator and the phase detector.

Figure 20 shows a dynamic timing network comprising interconnected timing nodes 201, 202, 203, 204 of a plurality of consecutive delay couplings. Each timing node is implemented as a PLL. The interconnection between the timing nodes 201, 202, 203 is unidirectional, and the interconnection between the timing nodes 202 and 204 is bidirectional. Thus, a timing network with continuously coupled delay coupled PLLs can include both unidirectional and bidirectional interconnections.

Figure 21 shows the node of Figure 3 including an additional delay 215 in the output path between the controllable oscillator and the phase detector of at least one other node to adjust the time delay.

Fig. 22 shows the specifications of the measured digital PLL shown in Figs. 12 to 15.

Fig. 23 shows the specifications of the measured digital PLL shown in Fig. 16 and Fig. 17.

11‧‧‧ core
12‧‧‧Master Clock
13, 22‧‧‧Time Network
21‧‧‧Timed node
31, 32, 41, 42, 52‧ ‧ controller
32, 42, 52, 62, 72‧‧‧ Loop Filter (LF)
33, 43, 53, 63, 73, 183, 193 ‧ ‧ controllable oscillator
34, 46, 541, 542, 543, 544, 641, 642, 643, 644, 186, 196, 214 ‧ ‧ transmission delay
45, 215, 551, 552, 553, 554, 651, 652, 653, 654, 185, 195‧‧‧ retarders
56, 66‧‧‧ combiner
511, 512, 513, 514, 71, 61, 181, 191, 211‧‧ ‧ phase detector (PD)
63, 73‧‧‧Voltage Controlled Oscillator (VCO)
77‧‧‧Feedback delay
79, 189, 199‧‧‧ tunable signal inverter

21‧‧‧Timed node

22‧‧‧Timed Network

Claims (15)

A network comprising a plurality of nodes, wherein each node is interconnected with at least another node of the network, and the interconnection indicates that the output of the interconnected first node is connected to the interconnected one The input of the second node, and the output of the second node and/or a third node is connected to the input of the first node; the each node comprises: a. a controllable oscillator configured to Generating a time continuous synchronization signal for synchronizing the plurality of interconnected nodes of the network; b. a controller configured to adjust a frequency of the continuous synchronization signal generated by the controllable oscillator by the time Comparing and synchronizing a phase of the time continuous synchronization signal generated by the controllable oscillator with a phase of an external time continuous synchronization signal received from another node of the network, the controller is further configured Repeatingly adjusting the frequency of the time continuous sync signal generated by the controllable oscillator; c. wherein the signal transmission speed and each interconnection of the network The length is configured to cause a delay of the signal received by a node from the other node or other nodes connected to each other, which is greater than a millionth of the natural period of the controllable oscillator of the receiving node First, to achieve full network synchronization of the oscillator in a continuous self-organization process for all nodes of the network in interaction with another node or other nodes of the network. A network as claimed in claim 1, wherein each node comprises an additional delay, the additional delay being configured within the interconnection or by the controller. The network described in claim 1 or 2, wherein in each node, a feedback delay a natural frequency of the controllable oscillator Coupling strength An impulse response of a filter in a controller Including a delay caused by an interconnected length And a delay caused by a delay on demand One delay It is configured such that the successive reduction of the phase difference associated with a phase locked synchronization state is reduced. The network described in claim 3, wherein in each node, a feedback delay a natural frequency of the controllable oscillator Coupling strength An impulse response of a filter in a controller Including a delay caused by an interconnected length And a delay caused by a delay on demand One delay Configured to make All solutions to the equation Satisfy ,among them Point out node as well as Interconnected between each other. The network of any one of clauses 1 to 4, wherein, in each node, the controller includes a phase detector configured to compare the phase of the external time continuous synchronization signal The phase of the signal is continuously synchronized with the time generated by the controllable oscillator. The network of claim 5, wherein each node further comprises a combiner to combine the external time continuous synchronization signals received from other nodes of the network to generate a combined external time continuous synchronization. a signal, and wherein the phase detector compares the phase of the time continuous synchronization signal generated by the controllable oscillator with the phase of the combined external time to continuously synchronize the signal. The network of claim 5, wherein in each node, the phase detector is configured to individually compare the phase and each of the time continuous synchronization signals generated by the controllable oscillator The external time continuously synchronizes the phase of the signal to generate a plurality of phase detector signals; and wherein the combiner combines the phase detector signals to control the controllable oscillator. The network of any one of clauses 3 to 6, wherein each node comprises a plurality of delays for inducing an additional time delay in addition to a transmission time delay to generate This delay of successively synchronizing signals for each received external time. The network of any one of clauses 1 to 8, wherein each controller comprises the combiner. The network of any one of clauses 1 to 9, wherein each node is included in a feedback path between the controllable oscillator and the phase detector for inducing a feedback time a delayed feedback delayer and/or a feedback path between the controllable oscillator and the phase detector for inverting a tunable signal inverter for the feedback signal, and/or a tunable signal inverter for inverting the input signal in an input path, and/or for inverting an output path between the controllable oscillator and the phase detector of at least one other node A tunable signal inverter of the output signal. The network of any one of clauses 1 to 10, wherein each node is a timing node, and wherein the time continuous synchronization signal is a clock signal for timing a device. A method for synchronizing a network comprising a plurality of nodes, wherein each of the nodes is interconnected with at least another node of the network, and the interconnection implies the output of the interconnected first node Connecting to the input of the interconnected second node, and the output of the second node and/or a third node is connected to the input of the first node; comprising the following steps: a controllable oscillation And generating, in each node, a time continuous synchronization signal for synchronizing the plurality of interconnected nodes of the network; b. adjusting, by a controller, the time continuous synchronization signal generated by the controllable oscillator a frequency to compare and synchronize a phase of the time-synchronized signal generated by the controllable oscillator to another node or other nodes of the network, with another node from the network or another The phase of an external time continuous synchronization signal received by some nodes; c. repeatedly adjusting the frequency of the time continuous synchronization signal generated by the controllable oscillator; d. The medium signal transmission speed and the length of each interconnect of the network are configured to cause a delay of the signal received by a node from the other node or other nodes that are interconnected, which is greater than the delay of the receiving node The one-thousandth of a million of the natural period of the oscillator can be controlled such that all nodes of the network oscillate in a continuous self-organizing process in interaction with another node or other nodes of the network Full network synchronization. The method for synchronizing a network according to the method of claim 12, wherein in each node, the phase of the external time continuous synchronization signal and the time continuous synchronization signal generated by the controllable oscillator The phases are compared. A method for synchronizing a network as described in claim 12 or 13, wherein in each of the nodes, the controller adjusts a time synchronization signal generated by the controllable oscillator by the time Frequency to compare and synchronize a phase of the time-continuous synchronization signal generated by the controllable oscillator, which is transmitted to another node of the network, consecutive to external time received from other nodes of the network The phase of the synchronization signal, - wherein the external time continuous synchronization signal received from another node or other nodes of the network is delayed by a time delay for the time continuous synchronization signal transmitted by the other node or other nodes; - wherein the controller repeatedly adjusts the frequency of the time continuous sync signal generated by the controllable oscillator such that all nodes of the network are interacting with another node of the network, A full network synchronization of the oscillator is achieved during a continuous self-organizing process. A method for synchronizing a network according to any one of clauses 12 to 14, wherein each phase detector individually compares the time continuous generated by the controllable oscillator. The phase of the sync signal continuously synchronizes the phase of the signal with each external time to generate a plurality of phase detector signals; and wherein the combiner combines the phase detector signals to control the controllable oscillator.