KR101783997B1 - A Cellular Oscillator Network Circuit using CMOS Inverter - Google Patents

Abstract

A cellular oscillator network circuit is disclosed. A cellular oscillation network circuit according to the present invention comprises: a receiver for receiving a power supply voltage signal to a cellular oscillation network circuit; And an oscillation unit for generating the received power supply voltage signal as a signal on the same level; And an output unit for outputting the generated signal of the same phase; Wherein the cellular oscillation network circuit comprises three nodes for forming a fractal structure, and an inverter is disposed between each of the three nodes, and the oscillation section generates a voltage Or temperature may be set to produce a signal on the same phase over a period of time if at least one of the changes occurs.

Description

[0001] The present invention relates to a cellular oscillation network circuit using a CMOS inverter,

The present invention relates to a ring oscillator (Ring OSC) and an oscillation control method using the same. More particularly, the present invention relates to a method of synchronizing a high-speed integrated circuit clock signal using a fractal structure oscillator.

According to the present invention, a jitter phenomenon and a clock skew phenomenon occurring in the oscillator can be reduced.

In addition, the oscillator circuit of the fractal structure using the inverter can reduce the size by using CMOS (Complementary Metal-Oxide Semiconductor), and the jitter phenomenon and the clock skew phenomenon are reduced by the fractal structure and the characteristics of the inverter, An excellent oscillator can be designed.

An oscillator circuit has some problems in generating a stable oscillation frequency. As the size of a conventional oscillator circuit increases, a jitter phenomenon occurs in which the frequency instantaneously shakes, and a clock skew phenomenon occurs in which the phase is delayed.

A ring-type oscillator is widely used as a clock generation circuit due to its efficiency, wide frequency range, and small area. The oscillation frequency of the ring oscillator is usually calculated according to the following equation (1).

Where N represents the number of delay cells, and td represents the delay time of one delay cell. Since the oscillation frequency of the ring oscillator is inversely proportional to N, there are limitations in operation reliability and area when many delay stages are used.

In addition, stability in the circuit for generating and distributing the high-speed clock frequency of the conventional GHz class is a major factor in performance. However, there is no oscillator using only an inverter, and development of an oscillator designed with a fractal structure to generate a high- Is required.

Particularly, clock generation and distribution of SoC (System on Chip), which requires a clock frequency of GHz, is a very important factor in circuit design. As the acceleration of the high integration of CMOS integrated circuits, This is because there is a technical need to process information in time and accurately synchronize the results.

SUMMARY OF THE INVENTION An object of the present invention is to provide a ring oscillator having a stable fractal structure.

In addition, according to the present invention, a jitter phenomenon in which an unstable frequency instantly occurs and a clock skew phenomenon in which a phase delay occurs can be reduced.

The present invention improves the performance of a conventional clock distribution technique and proposes a new type of power supply voltage and a clock generation and distribution circuit insensitive to temperature change using a fractal oscillation cellular network.

It is to be understood that the technical objectives of the present invention are not limited to the above-mentioned technical objects and other technical objects which are not mentioned in the following description are to be understood from the following description, It will be understood clearly by those with knowledge.

According to an aspect of the present invention, there is provided a cellular oscillation network circuit comprising: a receiver for receiving a power supply voltage signal in a cellular oscillation network circuit; And an oscillation unit for generating the received power supply voltage signal as a signal on the same level; And an output unit for outputting the generated signal of the same phase; Wherein the cellular oscillation network circuit comprises three nodes for forming a fractal structure, and an inverter is disposed between each of the three nodes, and the oscillation section generates a voltage Or temperature may be set to produce a signal on the same phase over a period of time if at least one of the changes occurs.

In addition, the oscillation unit may be set such that the output signal of the same phase has a clock skew of less than 1% of the cycle in accordance with a change in the voltage applied to the cellular oscillation network circuit.

In addition, the oscillation unit may be set such that the output signal of the same phase has a clock skew of less than 0.4% with respect to the cycle in accordance with a change in the internal temperature of the cellular oscillation network circuit.

In addition, the cellular oscillation network circuit may be configured by connecting an odd number of inverters between each node.

The odd number of inverters may be connected to each other in series.

In addition, the cellular oscillation network circuit may be operated at a GHz frequency range.

According to another aspect of the present invention, there is provided an oscillation control method comprising: switching power supply to a network circuit to an oscillating state; Generating an in-phase signal through a CMOS multi-layer metal process; And outputting the generated signal of the same phase, wherein the network circuit comprises three nodes in order to have a fractal structure, an inverter is disposed between the nodes, The signal on the same phase to be output is set to oscillate at the same frequency and the same phase, and when at least one of voltage or temperature changes in some local cells of the network circuit, Can be generated.

The present invention has the following effects.

According to the present invention, a simple ring oscillator can be used to reduce errors caused by clock skew phenomenon and asynchronous operation.

According to the present invention, a fast clock frequency can be generated by designing a fractal structure using only inverters.

According to the present invention, there is an advantageous effect of achieving overall synchronization even in a partial temperature and voltage difference using a ring oscillator of fractal structure.

1 is a diagram illustrating a cellular oscillation network structure according to the present invention.
2 is a diagram of a CMOS cellular oscillator network comprised of 108 inverters in accordance with the present invention.
3 is a conceptual diagram illustrating an implementation of an oscillation network using a multi-layer CMOS process according to the present invention.
4 is a flowchart illustrating an operation process in an oscillation network circuit of a fractal structure according to the present invention.
5 is a diagram showing an output waveform of the oscillation network circuit of the fractal structure according to the present invention.
FIG. 6 is a graph showing a waveform obtained by measuring a skew phenomenon of an oscillation network circuit of a fractal structure according to the present invention.
FIG. 7 is a graph showing waveforms of skew phenomenon according to a voltage change of an oscillation network circuit of a fractal structure according to the present invention. FIG.
8 is a graph showing waveforms of skew phenomenon according to a temperature change of an oscillation network circuit of a fractal structure according to the present invention.
FIG. 9 is a structural view showing an oscillation network circuit of a fractal structure according to the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, the same reference numerals will be used for the same constituent elements in the drawings, and redundant explanations for the same constituent elements will be omitted.

1 is a diagram illustrating a cellular oscillation network structure according to the present invention.

Due to the development of System on Chip (SoC) design technology, the clock signal (clock signal) of the integrated circuit (IC) constituting the system is mostly GHz high frequency.

The generation and distribution of the super high-speed clock signal can be an important factor in the design of the integrated circuit, and when clock skew phenomenon occurs in which the phase is delayed, the synchronization is not accurately performed, .

In the conventional PLL circuit, a phase detector (PD), a voltage controlled oscillator (VCO), a loop filter (Loop) Filter, and the like, so that the circuit configuration is complicated, and as the wiring area increases, the chip size also increases.

As shown in Fig. 1, in the large triangle 1-2-3, a triangle 4-5-6 having a smaller size and a triangle 7-8-9 having a smaller size continue to have the same structure And a fractal structure that can be extended can be confirmed.

The relatively small triangle (10-11-12) can be configured as an inverter for each basic cell, and the oscillator can be configured using CMOS as an extension of the basic triangle (10-11-12).

For example, for an inverter between node 1 and node 6 in a structure composed of triangles (1-6-5), node 1 may be an input signal and node 6 may be an output signal.

The ring oscillator of the fractal structure in the present invention can generate a high clock frequency of GHz level and can distribute the clock frequency. Fractal ring oscillator is a circuit that can stably generate a certain frequency in a circuit requiring high clock frequency of GHz. The proposed circuit has an advantageous effect of reducing the error operations that can be caused by the clock skew and jitter phenomenon of the existing complex PLL (Phase Locked Loop) circuit.

An odd number of inverters may be connected between each node. Preferably, an odd number of inverters may be connected in series between each node. By using an odd number of inverters, inversion can be prevented.

The fractal structure allows the size of the ring oscillator of the fractal structure to be extended. Fractional ring oscillators can be constructed with fewer than 15 to 45 nodes. In this case, one inverter has a phase difference of ⅓π, and three inverters constitute one cell, so that one cell has a phase difference of ⅔π. Thus, it can have one 2π cycle phase by three different inverters.

When powering a CMOS fractal oscillator circuit, it is possible to create an oscillating state with the same clock frequency at all nodes. Even if a frequency difference occurs in one node, the mutual phase difference is reduced due to the characteristic of the fractal oscillator structure, so that the same frequency can be converted and the phase can be controlled in the same manner.

The Cellular Oscillator Network plane (CON) according to the present invention can be implemented by the latest multi-layer built-in circuit processing and packaging techniques. The spacing between the digital and analog planes can be reduced with minimal interference.

2 is a diagram of a CMOS cellular oscillator network comprised of 108 inverters in accordance with the present invention.

1, the fractal structure can be infinitely extended by theoretically adding the number of inverters. FIG. 2 is a fractal cellular CMOS oscillating network having 108 inverters.

When power is supplied to the network circuit, it oscillates like a basic ring oscillator, and all nodes have the same frequency due to the structural characteristics of the network. Even if a local disturbance of a local node of a circuit occurs, the same phase and a global state change are generated in the whole network by being transmitted to the entire network.

In FIG. 2, the change in phase or frequency in the center cell 40-41-45 and the change in phase or frequency in the outer cell 16-17-18 may differ in the degree of clock skew.

In the case of the central cell 40-41-45, the propagation of the change in the fractal structure is easier than that of the outer cell 16-17-18, so that the clock skew can be small. Conversely, since the outer cell 16-17-18 is more difficult to propagate (spread) over the entire cellular oscillation network than the center cell 40-41-45, the clock skew may be large. However, this may vary depending on experimental data, and the clock skew of the outer cell may be less than the clock skew of the center cell.

In other words, if the value of the change applied to the circuit is large, it can be shown through the following experimental value that the value of the clock skew for the entire oscillation network can be small enough that the difference is insignificant depending on the position of the cell have.

3 is a conceptual diagram illustrating an implementation of an oscillation network using a multi-layer CMOS process according to the present invention.

It can be implemented with a simple structure without limitations in line distribution using a CMOS multi-layer metal process, and can have a structure for minimizing interference between digital and analog signals. These structural features enable minimization of clock skew and enable localized phase or frequency variation to be quickly distributed across the global network, resulting in inherent robustness to unbalanced load conditions. Lt; / RTI >

As shown in FIG. 3, the realization degree of the oscillation network can be conceptually represented by having four planes. Can be represented as a cellular oscillator network plane between the RF IC, the analog plane, and the digital plane, the analog plane and the digital plane.

4 is a flowchart illustrating an operation process in an oscillation network circuit of a fractal structure according to the present invention.

In step S410, power can be supplied to the oscillation network circuit. That is, the receiver of the oscillation network circuit can receive the supplied power supply voltage signal. When power is supplied to the network circuit, the oscillating network circuit composed of the ring oscillator of the fractal structure can be switched to the oscillating state.

In step S420, the oscillating network circuit may generate a signal on the in-phase through a CMOS multi-layer metal process. An In phase signal can be a broad concept signal including signals of the same phase or the same frequency.

Changes in local voltage or temperature that occur in some local cells of the fractal structure can be distributed throughout the oscillating network circuit by the structural features of the oscillating network circuit and produced in the same phase or at the same frequency .

The oscillation portion of the oscillation network circuit may perform the above oscillation process to generate a signal on the same phase. Particularly, the oscillation unit according to the present invention can be set to generate a signal on the same phase over a certain period of time when at least one of voltage or temperature change occurs in some local cell of the oscillation network circuit.

The oscillation unit according to the present invention is characterized in that the output signal of the equal phase is set to have a clock skew of less than 1% with respect to the cycle in accordance with the change of the voltage applied to the oscillation network circuit. As shown in FIG. 7, the value of the clock skew may be less than 1% of the cycle even if the power supply voltage value changes. Such a clock skew value may appear differently depending on the position of the cell of the oscillation network circuit.

The change in the power supply voltage in the central cell (40-41-45 cells in Fig. 2) of the oscillation network circuit and the change in the power supply voltage in the outer cell (16-17-18 cells in Fig. 2) are different from each other . In the case of a center cell, distribution according to a local change may be easier than with an outer cell.

In step S430, the oscillation network circuit can output the generated on-state signal. That is, the output portion of the oscillation network circuit can output the generated signal of the same phase. The output signal on the same phase may be a signal whose clock skew is reduced as a clock frequency. In addition, the present oscillation technique can be used as an oscillation technique in which the oscillation network circuit is reduced in voltage skew caused by a voltage change or a temperature change and is insensitive to a voltage change or a temperature change.

5 is a diagram showing an output waveform of the oscillation network circuit of the fractal structure according to the present invention.

5 (a) is a diagram showing a waveform output from a CMOS oscillation network circuit using 108 inverters, and FIG. 5 (b) is a diagram showing waveforms output from 15 in-phase nodes.

The output waveform is the simulation result, and the voltage is supplied in the same simulation environment of 300K, 3 volts.

As shown in FIG. 5 (a), it can be seen that the output waveform is largely adjusted to an in-phase signal in three phases since about 6 ns as time passes, and the three signals are 120 degrees difference Phase.

As shown in Fig. 5 (b), it can be seen that the output waveform is adjusted in phase in a total of 15 nodes. From about 4n afterwards, only one phase is outputted, and it is confirmed that signals of 15 different phases are adjusted to signals of the same phase.

FIG. 6 is a graph showing a waveform obtained by measuring a skew phenomenon of an oscillation network circuit of a fractal structure according to the present invention.

In FIG. 6, the clock skew value of the cellular oscillation network circuit is measured. The clock signal having the same 1.6 volt value has a clock skew of 0.000526 ns as compared with the first signal, 28.694246 ns for the first signal and 28.694775 ns for the second signal. .

FIG. 7 is a graph showing waveforms of skew phenomenon according to a voltage change of an oscillation network circuit of a fractal structure according to the present invention. FIG.

7 (a) is a waveform obtained by measuring a clock skew according to a power supply voltage change in a center cell, and FIG. 7 (b) is a waveform obtained by measuring a clock skew according to a power supply voltage change in the outer cell.

In this simulation, a 3V, 0.5μm CMOS process was used and the voltage variation range of the circuit power supply voltage was 3% of the 3V reference voltage.

The center cell in the present invention may be the cell 40-41-45 in FIG. 2, and the outer cell may be the cell 16-17-18 in FIG. As shown in Fig. 7 (a), a voltage decrease may occur in the center cell 40-41-45, and as shown in Fig. 7 (b), in the outer cell 16-17-18 Voltage loss can occur.

The clock skew values according to the voltage decrease changes were measured as shown in Table 1 below.

Voltage change in center cell Voltage change -0.5% -One% -1.5% -2% -2.5% -3% Skew
Rate Cell
domain 2% 0.021 0.023 0.235 0.273 0.257 0.742 5% 0.095 0.364 0.587 0.618 0.620 0.929 8% 0.430 0.745 0.868 0.916 0.960 1.061 Supply voltage range: 3 to 2.91 V The voltage change in the outer cell Voltage change -0.5% -One% -1.5% -2% -2.5% -3% Skew
Rate Cell
domain 2% 0.081 0.240 0.361 0.375 0.672 0.703 5% 0.159 0.451 0.502 0.628 0.722 0.841 8% 0.265 0.453 0.602 0.748 0.836 1.054

As shown in Table 1, it can be seen that the in-phase node clock skew is measured within a range of ~ 1% of the cycle according to the voltage change. As the clock skew is measured to be around 1%, it can be confirmed that it can be used for GHz-class high-speed clock generation and distribution circuit. It can be applied not only to chip but also to chip-to-chip or system-to-system have.

8 is a graph showing waveforms of skew phenomenon according to a temperature change of an oscillation network circuit of a fractal structure according to the present invention.

In this simulation, a 3V, 0.5μm CMOS process was used. The temperature range of power supply voltage of the circuit was varied from -40 ℃ to 85 ℃.

The clock skew values according to the temperature changes were measured as shown in Table 2 below.

Temperature change -5% -3% -One% 0% One% 3% 5% Skew rate 0.347 0.095 0.062 0 0.065 0.135 0.340 Temperature range: -40 ℃ ~ 85 ℃

As shown in Table 2, it can be seen that the difference in clock skew was measured to be less than 0.4% of the cycle. As the clock skew is measured to be around 0.4%, it can be seen that it can be used for GHz-class high-speed clock generation and distribution circuit, and it can be applied not only in chip but also chip-to-chip or system-to-system have.

FIG. 9 is a structural view showing an oscillation network circuit of a fractal structure according to the present invention.

As shown in FIG. 9, a CMOS layer in a cellular oscillation network using 108 inverters can be identified.

In the present invention, a multi-layered cellular oscillation network circuit is designed and a technique for generating and distributing a clock signal is proposed. Due to the structural nature of the fractal network, clock signals experimentally demonstrate low clock skew of less than 1% and 0.4% even at a 1.5% change in power supply voltage and a 5% variation in internal temperature, Speed clock generation and distribution circuits.

In other words, it is possible to obtain the same clock signal in a plurality of in-phase nodes, and it may mean that generation and distribution efficiency of GHz clock is high in view of low clock skew. It can be used sufficiently as a technique.

The functional operations described herein and embodiments of the present subject matter may be implemented in digital electronic circuitry or computer software, firmware or hardware, including combinations of structures disclosed herein, and structural equivalents thereof, .

Embodiments of the subject matter described herein may be implemented as one or more computer program products, in other words one or more modules for computer program instructions encoded on a type of program medium for execution by, or control over, the operation of the data processing apparatus Can be implemented. The type of program medium may be a propagated signal or a computer readable medium. A propagated signal is an artificially generated signal, such as a machine-generated electrical, optical or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by a computer. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a combination of materials that affect the machine readable propagation type signal, or a combination of one or more of the foregoing.

A computer program (also known as a program, software, software application, script or code) may be written in any form of programming language, including compiled or interpreted language, a priori or procedural language, Components, subroutines, or other units suitable for use in a computer environment.

A computer program does not necessarily correspond to a file in the file system. The program may be stored in a single file provided to the requested program, or in multiple interactive files (e.g., a file storing one or more modules, subprograms, or portions of code) (E.g., one or more scripts stored in a markup language document).

A computer program may be deployed to run on multiple computers or on one computer, located on a single site or distributed across multiple sites and interconnected by a communications network.

Additionally, the logic flows and structural block diagrams described in this patent document describe corresponding actions and / or specific methods supported by corresponding functions and steps supported by the disclosed structural means, It can also be used to build software structures and algorithms and their equivalents.

The processes and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output.

Processors suitable for the execution of computer programs include, for example, any one or more processors of both general purpose and special purpose microprocessors and any kind of digital computer. Generally, a processor will receive instructions and data from read-only memory, random access memory, or both.

A core element of a computer is a processor for executing instructions and one or more memory devices for storing instructions and data. In addition, the computer is generally operatively coupled to receive data from, transfer data to, or perform both of the operations of, for example, one or more mass storage devices for storing data such as magnetic, magneto-optical disks, Or will include. However, the computer need not have such a device.

The description sets forth the best mode of the invention, and is provided to illustrate the invention and to enable those skilled in the art to make and use the invention. The written description is not intended to limit the invention to the specific terminology presented.

Thus, while the present invention has been described in detail with reference to the above examples, those skilled in the art will be able to make adaptations, modifications, and variations on these examples without departing from the scope of the present invention. In other words, in order to achieve the intended effect of the present invention, all the functional blocks shown in the drawings are separately included or all the steps shown in the drawings are not necessarily followed in the order shown, It can be in the range.

Claims (12)

A receiver for receiving a power supply voltage signal in a cellular oscillation network circuit; And
An oscillation unit for generating the received power supply voltage signal as a signal on the same level; And
An output unit for outputting the generated signal of the same phase; Lt; / RTI >
The cellular oscillation network circuit comprising:
In order to have a fractal structure, three nodes constitute one cell, an inverter is arranged between each node,
Wherein when the voltage change occurs within a range of 3% or less within a certain local cell of the cellular oscillation network circuit,
Is set to be generated as a signal on the same phase as a predetermined time passes,
Wherein the clock skew phenomenon of the central side cell of the cellular oscillation network circuit is less than the clock skew phenomenon of the cell outside of the cellular oscillation network circuit.
The method according to claim 1,
Wherein,
In response to a change in the voltage applied to the cellular oscillation network circuit,
Characterized in that the output signal of the same phase is set to have a clock skew of less than 1% of the period.
The method according to claim 1,
Wherein,
Depending on the change in the internal temperature of the cellular oscillation network circuit,
Characterized in that the output signal of the same phase is set to have a clock skew within 0.4% of the period.
The method according to claim 1,
The cellular oscillation network circuit comprising:
And an odd number of inverters are connected between each node.
The method of claim 4,
And the odd number of inverters are connected in series with each other.
The method according to claim 1,
Wherein the cellular oscillation network circuit is operated at a GHz frequency range.
Switching to an oscillating state by supplying power to the network circuit;
Generating an in-phase signal through a CMOS multi-layer metal process; And
And outputting the generated signal of the same phase,
The network circuit comprising:
In order to have a fractal structure, three nodes constitute one cell, an inverter is arranged between each node,
The output signals of the same phase are set to oscillate at the same frequency and phase,
If a voltage change occurs within a range of 3% within some local cells of the network circuit,
As the time passes, it is generated as a signal on the same level,
Wherein a clock skew phenomenon of a central cell of the network circuit is less than a clock skew phenomenon of a cell outside the network circuit.
The method of claim 7,
The network circuit comprising:
In response to a change in the voltage applied to the network circuit,
Wherein the output signal of the same phase has a clock skew of less than 1% of the cycle.
[Claim 7]
The network circuit comprising:
In accordance with a change in the internal temperature of the network circuit,
Wherein the output signal of the equal phase has a clock skew within 0.4% of the cycle.
The method of claim 7,
The network circuit comprising:
And an odd number of inverters are connected between each node.
The method of claim 10,
And the odd number of inverters are connected in series with each other.
The method of claim 7,
Wherein the network circuit is operated at a GHz frequency.

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