KR101754224B1 - Method for synchronizing multi-chp system clock signal using ring oscillator and appatus thereof - Google Patents

Abstract

A ring oscillator is initiated. A ring oscillator according to the present invention includes: a receiver for receiving clock signals generated from a plurality of chips; And a connecting portion connecting each of a plurality of oscillator oscillators of the same fractal structure to each other with a corresponding end; And an output unit for outputting a signal oscillated by the oscillator of the same fractal structure; The oscillator can be set such that three nodes constitute one cell to have a fractal structure, an inverter is disposed between each node, and the clock signals are oscillated at the same frequency and same phase.

Description

TECHNICAL FIELD [0001] The present invention relates to a multi-chip system clock signal synchronizing method and apparatus using a ring oscillator,

The present invention relates to a ring oscillator (Ring OSC) and an oscillation control method using the same. More particularly, the present invention relates to a method of synchronizing a high-speed integrated circuit clock signal using a fractal structure oscillator.

According to the present invention, a jitter phenomenon and a clock skew phenomenon occurring in the oscillator can be reduced.

In addition, the oscillator circuit of the fractal structure using the inverter can reduce the size by using CMOS (Complementary Metal-Oxide Semiconductor), and the jitter phenomenon and the clock skew phenomenon are reduced by the fractal structure and the characteristics of the inverter, An excellent oscillator can be designed.

An oscillator circuit has some problems in generating a stable oscillation frequency. As the size of a conventional oscillator circuit increases, a jitter phenomenon occurs in which the frequency instantaneously shakes, and a clock skew phenomenon occurs in which the phase is delayed.

A ring-type oscillator is widely used as a clock generation circuit due to its efficiency, wide frequency range, and small area. The oscillation frequency of the ring oscillator is usually calculated according to the following equation (1).

Where N represents the number of delay cells, and td represents the delay time of one delay cell. Since the oscillation frequency of the ring oscillator is inversely proportional to N, there are limitations in operation reliability and area when many delay stages are used.

In addition, stability in the circuit for generating and distributing the high-speed clock frequency of the conventional GHz class is a major factor in performance. However, there is no oscillator using only an inverter, and development of an oscillator designed with a fractal structure to generate a high- Is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a ring oscillator having a stable fractal structure.

In addition, according to the present invention, a jitter phenomenon in which an unstable frequency instantly occurs and a clock skew phenomenon in which a phase delay occurs can be reduced.

It is to be understood that the technical objectives of the present invention are not limited to the above-mentioned technical objects and other technical objects which are not mentioned in the following description are to be understood from the following description, It will be understood clearly by those with knowledge.

According to an aspect of the present invention, there is provided an oscillation control method including: receiving clock signals generated from a plurality of chips; Oscillating the input clock signals in a plurality of oscillators of the same fractal structure; And outputting the oscillated signal, wherein the oscillator is configured such that three nodes constitute one cell to have a fractal structure, an inverter is disposed between each node, And can be set to oscillate in the same phase.

Preferably, the oscillator is a Complementary Metal-Oxide Semiconductor (CMOS) oscillator.

Preferably, the oscillator is a Transistor-Transistor Logic (TTL) oscillator.

In addition, the oscillator may be configured by connecting an odd number of inverters between each node.

The odd number of inverters may be connected to each other in series.

In addition, the oscillator may be operated at a GHz frequency range.

According to another aspect of the present invention, there is provided a ring oscillator including: a receiver for receiving clock signals generated from a plurality of chips; And a connecting portion connecting each of a plurality of oscillator oscillators of the same fractal structure to each other with a corresponding end; And an output unit for outputting a signal oscillated by the oscillator of the same fractal structure; The oscillator can be set such that three nodes constitute one cell to have a fractal structure, an inverter is disposed between each node, and the clock signals are oscillated at the same frequency and same phase.

The present invention has the following effects.

According to the present invention, a simple ring oscillator can be used to reduce errors caused by clock skew phenomenon and asynchronous operation.

According to the present invention, a fast clock frequency can be generated by designing a fractal structure using only inverters.

According to the present invention, there is an advantageous effect of achieving overall synchronization even in a partial temperature and voltage difference using a ring oscillator of fractal structure.

1 is a diagram showing a structure of a ring oscillator according to the present invention.
2 is a flowchart illustrating an oscillation control process in a ring oscillator according to the present invention.
3 is a block diagram conceptually showing the structure of a ring oscillator according to the present invention.
4 is a view showing a ring oscillator of a fractal structure according to the present invention.
5 is a diagram showing output waveforms under the same voltage condition in the ring oscillator according to the present invention.
6 is a diagram showing an output waveform according to a 1% voltage change in a ring oscillator.
7 is a graph showing a waveform obtained by measuring skew phenomenon with a 1% voltage change in a ring oscillator.
8 is a diagram showing a phase difference according to a 2% voltage change in a multi-chip system.
9 is a diagram showing an output waveform according to a voltage change of 2% in a multi-chip system according to the present invention.
FIG. 10 is a diagram showing a skew phenomenon of a TTL circuit in a multi-chip system according to the present invention.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail.

It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, the same reference numerals will be used for the same constituent elements in the drawings, and redundant explanations for the same constituent elements will be omitted.

1 is a diagram showing a structure of a ring oscillator according to the present invention.

Due to the development of System on Chip (SoC) design technology, the clock signal (clock signal) of the integrated circuit (IC) constituting the system is mostly GHz high frequency.

The generation and distribution of the super high-speed clock signal can be an important factor in the design of the integrated circuit, and when clock skew phenomenon occurs in which the phase is delayed, the synchronization is not accurately performed, .

In the conventional PLL circuit, a phase detector (PD), a voltage controlled oscillator (VCO), a loop filter (Loop) Filter, and the like, so that the circuit configuration is complicated, and as the wiring area increases, the chip size also increases.

The oscillation can be controlled by using a plurality of ring oscillators in order to prevent clock skew phenomenon and asynchronous operation in accordance with a difference in power supply voltage between chips.

In the ring oscillator of FIG. 1, all nodes operate at the same frequency at the time of oscillation, and a ring oscillator in the entire multi-chip can inevitably output the same frequency even when a plurality of ring oscillators different from each other are connected. The connections between the ring oscillators can be realized by simple external lines between inphase nodes.

As shown in FIG. 1, the oscillator used in the two chips and the two ring oscillators may each consist of fifteen inverters. Two ring oscillators can be connected to the in-phase node by three connector lines (CL, CL-1, CL-2 and CL-3).

Even if there is a slight difference in the voltage supplied to the two chips, the entire oscillator network can oscillate in the same frequency and phase by three connecting lines.

2 is a flowchart illustrating an oscillation control process in a ring oscillator according to the present invention.

In step S210, the receiver of the ring oscillator can receive the clock signal generated from the plurality of chips. In the case of a multi-chip system, the voltage and phase generated in each chip may be different, and the ring oscillator may receive such a clock signal to support operation in the ring oscillator network.

In step S220, the ring oscillator can oscillate the input clock signals at a plurality of oscillators having the same fractal structure. 1, the two oscillators may be ring oscillators each having a fractal structure, and in-phase nodes may be connected to each other by three connection lines CL-1, CL-2 and CL-3.

With this oscillator network structure, even though there is a difference in voltage supplied between the chips, the entire oscillator network can oscillate at the same frequency and same phase.

In step S230, the output unit may output the clock signal oscillated in the oscillator of the same fractal structure. In this case, the output signals may have the same frequency and the same phase.

3 is a block diagram conceptually showing the structure of a ring oscillator according to the present invention.

3, the ring oscillator 300 may include a receiving unit 310, a connecting line 320, and an output unit 330.

The receiving unit 310 according to the present invention can receive clock signals generated from a plurality of chips. In a multi-chip system, since the operation voltage, frequency, and phase required in a plurality of chips may be different from each other, the respective clock frequencies may also be different from each other.

The connecting line 320 according to the present invention can connect each end of a plurality of oscillators of the same fractal structure to the corresponding end. The three connection lines CL-1, CL-2 and CL-3 in FIG. 1 can connect the nodes having the same phase to each other with the three terminals of the fractal structure oscillator.

The output unit 330 according to the present invention can output a signal oscillated by an oscillator having the same fractal structure. The output signal is preferably a circuit oscillated at the same frequency and the same phase.

4 is a view showing a ring oscillator of a fractal structure according to the present invention.

As shown in Fig. 4, in the large triangle 1-2-3, a triangle 4-5-6 having a smaller size and a triangle 7-8-9 having a smaller size continue to have the same structure And a fractal structure that can be extended can be confirmed.

The relatively small triangle (10-11-12) can be configured as an inverter for each basic cell, and the oscillator can be configured using CMOS as an extension of the basic triangle (10-11-12).

For example, for an inverter between node 1 and node 6 in a structure composed of triangles (1-6-5), node 1 may be an input signal, and node 6 may be an output signal.

The ring oscillator of the fractal structure in the present invention can generate a high clock frequency of GHz level and can distribute the clock frequency. Fractal ring oscillator is a circuit that can stably generate a certain frequency in a circuit requiring high clock frequency of GHz. The proposed circuit has an advantageous effect of reducing the error operations that can be caused by the clock skew and jitter phenomenon of the existing complex PLL (Phase Locked Loop) circuit.

An odd number of inverters may be connected between each node. Preferably, an odd number of inverters may be connected in series between each node. By using an odd number of inverters, inversion can be prevented.

The fractal structure allows the size of the ring oscillator of the fractal structure to be extended. Fractional ring oscillators can be constructed with fewer than 15 to 45 nodes. In this case, one inverter has a phase difference of ⅓π, and three inverters constitute one cell, so that one cell has a phase difference of ⅔π. Thus, it can have one 2π cycle phase by three different inverters.

When powering a CMOS fractal oscillator circuit, it is possible to create an oscillating state with the same clock frequency at all nodes. Even if a frequency difference occurs in one node, the mutual phase difference is reduced due to the characteristic of the fractal oscillator structure, so that the same frequency can be converted and the phase can be controlled in the same manner.

The Cellular Oscillator Network plane (CON) according to the present invention can be implemented by the latest multi-layer built-in circuit processing and packaging techniques. The interval between the digital and analog planes can be reduced to minimum interference.

5 is a diagram showing output waveforms under the same voltage condition in the ring oscillator according to the present invention.

5 (a) shows the output waveform of the ring oscillator output through the simulation program, and Fig. 5 (b) shows the actually measured output waveform.

If the same voltage source is provided to two chips, the same frequency on the same phase is generated, and it can be seen that the center node (node # 13 in FIG.

6 is a diagram showing an output waveform according to a 1% voltage change in a ring oscillator.

6A is a simulation output waveform in a ring oscillator with a + 1% voltage change, and FIG. 6B is an actual measurement waveform in a TTL (Transistor-Transistor Logic).

It can be seen from the waveform that the phase difference between two clock signals occurs in the time interval of 8ns to 10ns.

7 is a graph showing a waveform obtained by measuring skew phenomenon with a 1% voltage change in a ring oscillator.

FIG. 7 is an enlarged view of the phase difference in FIG. 6. FIG. 7 (a) shows a simulation waveform and FIG. 7 (b) shows an actual measured waveform.

As shown in Fig. 7 (a), it can be confirmed that a skew phenomenon occurs between the two chips (CHIP-1 and CHIP-2) as the voltage is changed by 1%. The phase is delayed from 6.4 ns to 6.42 ns.

8 is a diagram showing a phase difference according to a 2% voltage change in a multi-chip system.

8 is a waveform output with a + 2% change in voltage under conditions similar to those of the experiments of FIGS. As shown, it can be seen that a symmetric phase difference of 143 ps occurs when there is a maximum 2% voltage difference between two chips. The phase difference is equivalent to 22.04% of the cycle.

Hereinafter, effects of the clock signal synchronization technique in the multi-chip system proposed by the present invention will be described.

9 is a diagram showing an output waveform according to a voltage change of 2% in a multi-chip system according to the present invention.

When three nodes are connected and measured using the oscillator network of the structure of the fractal ring oscillator of FIG. 1, the waveform as shown in FIG. 9 can be output. Fig. 9 (a) is a simulation output waveform, and Fig. 9 (b) is an actually measured waveform.

As shown in Figs. 9 (a) and 9 (b), when passing through a ring oscillator having a fractal structure, it can be confirmed that the skew phenomenon remarkably decreases through the chip to chip operation and is measured at the same frequency.

FIG. 10 is a diagram showing a skew phenomenon of a TTL circuit in a multi-chip system according to the present invention.

10 shows a simulation according to a voltage change of 2% and a skew phenomenon of a TTL circuit. As shown in FIG. 10, even when a signal having a voltage difference of 2% is input as oscillated by a fractal ring oscillator, It can be confirmed that a symmetrical phase difference occurs. It can be seen that the phase difference is remarkably reduced when compared with the symmetric phase difference of 143 ps in the general 2% voltage difference shown in FIG. 8, and the phase difference is only 2.98% with respect to the cycle.

As described above, the clock signal can be synchronized by using a ring oscillator insensitive to the power supply voltage. Through the proposed technique, clock skew is measured within 19.51ps of simulation standard, even though the power supply voltage difference between two different chips is 2%.

It is possible to obtain the same clock signal at a plurality of in-phase nodes, and it can be said that the generation and distribution efficiency of the GHz clock is high in view of low clock skew, and is a component technology complementing currently used PLL and DLL.

The functional operations described herein and embodiments of the present subject matter may be implemented in digital electronic circuitry or computer software, firmware or hardware, including combinations of structures disclosed herein, and structural equivalents thereof, .

Embodiments of the subject matter described herein may be implemented as one or more computer program products, in other words one or more modules for computer program instructions encoded on a type of program medium for execution by, or control over, the operation of the data processing apparatus Can be implemented. The type of program medium may be a propagated signal or a computer readable medium. A propagated signal is an artificially generated signal, such as a machine-generated electrical, optical or electromagnetic signal, generated to encode information for transmission to a suitable receiver device for execution by a computer. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a combination of materials that affect the machine readable propagation type signal, or a combination of one or more of the foregoing.

A computer program (also known as a program, software, software application, script or code) may be written in any form of programming language, including compiled or interpreted language, a priori or procedural language, Components, subroutines, or other units suitable for use in a computer environment.

A computer program does not necessarily correspond to a file in the file system. The program may be stored in a single file provided to the requested program, or in multiple interactive files (e.g., a file storing one or more modules, subprograms, or portions of code) (E.g., one or more scripts stored in a markup language document).

A computer program may be deployed to run on multiple computers or on one computer, located on a single site or distributed across multiple sites and interconnected by a communications network.

Additionally, the logic flows and structural block diagrams described in this patent document describe corresponding actions and / or specific methods supported by corresponding functions and steps supported by the disclosed structural means, It can also be used to build software structures and algorithms and their equivalents.

The processes and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output.

Processors suitable for the execution of computer programs include, for example, any one or more processors of both general purpose and special purpose microprocessors and any kind of digital computer. Generally, a processor will receive instructions and data from read-only memory, random access memory, or both.

A core element of a computer is a processor for executing instructions and one or more memory devices for storing instructions and data. In addition, the computer is generally operatively coupled to receive data from, transfer data to, or perform both of the operations of, for example, one or more mass storage devices for storing data such as magnetic, magneto-optical disks, Or will include. However, the computer need not have such a device.

The description sets forth the best mode of the invention, and is provided to illustrate the invention and to enable those skilled in the art to make and use the invention. The written description is not intended to limit the invention to the specific terminology presented.

Thus, while the present invention has been described in detail with reference to the above examples, those skilled in the art will be able to make adaptations, modifications, and variations on these examples without departing from the scope of the present invention. In other words, in order to achieve the intended effect of the present invention, all the functional blocks shown in the drawings are separately included or all the steps shown in the drawings are not necessarily followed in the order shown, It can be in the range.

Claims (13)

Receiving clock signals generated from a plurality of chips;
Oscillating the input clock signals in a plurality of oscillators of the same fractal structure; And
And outputting the oscillated signal,
The oscillator includes:
In order to have a fractal structure, three nodes constitute one cell, an inverter is arranged between each node,
The clock signals are set to oscillate at the same frequency and phase,
The plurality of oscillators having the same fractal structure,
Wherein the oscillator is an oscillator composed of the same number of inverters and having the same size as each other.
The method according to claim 1,
The oscillator includes:
Wherein the oscillator is a CMOS (Complementary Metal-Oxide Semiconductor) oscillator.
Claim 1:
The oscillator includes:
A transistor-transistor logic (TTL) oscillator.
The method according to claim 1,
The oscillator includes:
And an odd number of inverters are connected between each node.
The method of claim 4,
And the odd number of inverters are connected in series with each other.
The method according to claim 1,
Wherein the oscillator is operated at a GHz frequency.
A receiver for receiving clock signals generated from a plurality of chips; And
A connection portion connecting a plurality of oscillator oscillators of the same fractal structure to each other with a corresponding end; And
An output unit for outputting a signal oscillated by the oscillator of the same fractal structure; Lt; / RTI >
The oscillator includes:
In order to have a fractal structure, three nodes constitute one cell, an inverter is arranged between each node,
The clock signals are set to oscillate at the same frequency and phase,
The plurality of oscillators having the same fractal structure,
Wherein the oscillator is composed of the same number of inverters and is an oscillator having the same size as each other.
The method of claim 7,
The oscillator includes:
A complementary metal-oxide semiconductor (CMOS) oscillator.
The method of claim 7,
The oscillator includes:
And a TTL (Transistor-Transistor Logic) oscillator.
The method of claim 7,
The oscillator includes:
And an odd number of inverters are connected between each node.
The method of claim 10,
And the odd number of inverters are connected in series to each other.
The method of claim 7,
Characterized in that the oscillator is operated at a GHz frequency range.
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