CN104836573A - Synchronized clock system for ultra-large area array CMOS camera multipath high-speed signals - Google Patents

Abstract

The invention discloses a synchronized clock system for ultra-large area array CMOS camera multipath high-speed signals. The system comprises a work crystal oscillator, a reference crystal oscillator, T voltage controlled crystal oscillators, a programmable logic device (FPGA), T clock management chips having phase-locked loop functions, and T loop filters, wherein T is a positive integer. A phase-locked loop is formed by one clock management chip, the reference crystal oscillator, one voltage controlled crystal oscillator and one loop filter. Each phase-locked loop performs frequency division on the output frequency of the corresponding voltage controlled crystal oscillator according to input frequency division control quantities, and generates R+1 paths of data synchronized clocks. According to the invention, the system employs one reference crystal oscillator to output homologous reference frequency, so that T*R paths of synchronized clocks having consistent phases can be output, and a clock synchronization problem of multipath signals is solved. Furthermore, the clock management chips are employed to provide work clocks for the FPGA, and image data is processed by the corresponding clocks, so that the synchronization of output clocks and data phases of the FPGA can be completely guaranteed.

Description

The synchronized clock system of a kind of super large face battle array CMOS camera multipath high-speed signal

Technical field

The present invention relates to a kind of signal synchronized clock system, be particularly useful for the image data transmission of space remote sensing satellite large array CMOS image sensor camera system.

Background technology

Along with remote sensing user is to the enhancing increasingly of the continuous reconnaissance and surveillance demand of high-resolution, the large face application advantage of battle array cmos sensor in high rail remote sensing satellite highlights gradually.Because large face battle array cmos sensor can simultaneously output multi-channel high speed image signal, therefore have higher requirement to transfer of data.While multipath high-speed signal, transmission needs to adopt multi-disc high-speed digital transmission chip, but too much number of chips will make chip layout cannot be compact, thus inevitably there is long-distance transmissions problem, this can make the common clock duty cycle transmitted by FPGA change, and clock line also can cause shake to increase through multiple device in plate.

Meanwhile, along with the development of remote sensing satellite payload technology, and the function become increasingly complex that remote sensing satellite faces, the requirement improving star epigraph image data amount and message transmission rate has also become a trend.The requirement of a lot of high-speed digital transmission chip to the indices such as duty ratio, clock jitter of data sync clock is all very high.And space environment can cause certain deterioration to the clock quality being more than or equal to 100MHz.Variations in temperature in space, radiation and strenuous vibration all likely can enable clock Duty Cycle Distortion, shake increase.In the face of so many limiting factor and environmental constraints, improve clock stability and seem more and more important.

The work clock that crystal oscillator is just inputted by FPGA by traditional ground installation clock generating distributes output after the DCM of inside, and more precise and stable clock can adopt the IP kernel of DCM+PLL function to produce.But because space product is to the strict demand of the index such as radioresistance, high-low temperature resistant, the FPGA product hierarchy that tradition uses cannot be applicable to space product, and FPGA product available at present does not possess PLL function.Therefore a kind of clock system meeting Aerospace Standard of design is needed to solve this problem.

Patent CN203563034U proposes a kind of clock duty correction circuit reducing overshoot and shake, and this invention uses DCC delay chain, and its circuit design is not suitable for the field of the present invention's application.Patent CN102882623A proposes a kind of configurable clock frequency synthesizer based on FPGA, this device can produce the clock signal of various frequency, but because the clock signal produced is all homology, duty ratio and the shake of its signal all depend primarily on the clock quality that crystal oscillator is supplied to FPGA, therefore shake can not be reduced, also uncontrollable duty ratio.

Summary of the invention

The technical problem that the present invention solves is: overcome the deficiencies in the prior art, provide the synchronized clock system of a kind of super large face battle array CMOS camera multipath high-speed signal, can for transmitting the synchronised clock providing high stability while space flight multipath high-speed sensed image signal.

Technical solution of the present invention is: the synchronized clock system of a kind of super large face battle array CMOS camera multipath high-speed signal, comprise Clock management chip, a T loop filter of work crystal oscillator, reference crystal oscillator, a T VCXO, programmable logic device FPGA, T band phase locked looped function, T is positive integer, wherein:

Work crystal oscillator: for programmable logic device FPGA provides work clock;

Programmable logic device FPGA: with the work clock of the crystal oscillator that works for benchmark, receive T*R road view data from cmos image sensor, R is positive integer, produces T frequency dividing control amount P simultaneously _tand deliver to T Clock management chip respectively, each frequency dividing control amount P _ta corresponding Clock management chip; T circuit-switched data synchronised clock is obtained from T Clock management chip, utilize each circuit-switched data synchronised clock the R road received in view data to be exported to the outside R number corresponding with this circuit-switched data synchronised clock and pass chip, the corresponding number of each road view data passes chip;

Clock management chip: total T, each Clock management chip and reference crystal oscillator, VCXO structure, a loop filter form a phase-locked loop; For each phase-locked loop, according to the frequency dividing control amount P of input _t, P is carried out to the output frequency of VCXO _tfrequency division, produce R+1 circuit-switched data synchronised clock, wherein R circuit-switched data synchronised clock is delivered to the outside R number corresponding with this Clock management chip respectively and is passed chip, and programmable logic device FPGA delivered to by a remaining circuit-switched data synchronised clock;

With reference to crystal oscillator: for T Clock management chip produces the reference clock of homology;

VCXO: total T, according to the clock signal of the charge pump signal generation respective phase that the Clock management chip of correspondence exports, and feeds back to Clock management chip;

Loop filter: total T, the HFS of charge pump signal described in filtering, the voltage signal after filtering controls the frequency of oscillation of VCXO.

Described R >=2, and T >=2.The frequency of described R+1 circuit-switched data synchronised clock is not less than 100M.Described loop filter is the passive low ventilating filter on three rank.

The present invention's advantage is compared with prior art:

(1) the present invention utilizes Clock management chip to form a phase-locked loop with reference to crystal oscillator, VCXO and loop filter, can be provided the high-frequency clock of phase stabilization by the control of FPGA to system;

(2) in the present invention, clock system can be expanded as using T Clock management chip, VCXO and loop filter simultaneously, one is adopted to export homology reference frequency with reference to crystal oscillator, the synchronised clock that T*R road phase place is consistent can be exported like this, solve the clock synchronization issue of multiple signals;

(3) adopt Clock management chip to provide work clock to replace directly being supplied to work clock by external crystal-controlled oscillation for FPGA in the present invention, by the corresponding view data of clock process of correspondence, the output clock of FPGA and the Complete Synchronization of data phase can be ensured;

(4) adopt Clock management chip can adjust clock flexibly and count the position relationship passing chip in the present invention, reduce transmission range, simultaneously because Clock management chip drives ability is large, therefore not easily change in duty cycle occurs.Solve the problem that multipath high-speed signal transmits the faced a series of board design placement-and-routings brought because number of chips increases simultaneously like this, thus avoid long-distance transmissions the common clock duty cycle transmitted by FPGA is changed, the problem that clock line causes shake to increase through multiple device in plate;

(5) loop filter in the present invention adopts the passive loop filter on three rank, compares second order filter and can reduce the ripple that reference frequency feedthrough brings preferably; Comparing active filter can simplified design and cost, and avoid the active device part in active structure to bring the noise of extra loop, thus control VCXO can produce stable feedback reference clock, improve the stability that whole synchronized clock system produces high-speed clock signal.

Accompanying drawing explanation

Fig. 1 is the theory of constitution figure of present system;

Fig. 2 is the cut-away view of Clock management chip;

Fig. 3 is the circuit diagram of third order PLL path filter;

Fig. 4 is a kind of embody rule frame diagram of present system.

Embodiment

According to the feature of super large face battle array CMOS camera image transmission, output multi-channel high speed signal simultaneously, the present invention devises one and comprises work crystal oscillator A, reference crystal oscillator B, T VCXO, programmable logic device FPGA, T band the Clock management chip of phase locked looped function, the clock system of a T loop filter, and concrete structure as shown in Figure 1.This system uses T Clock management chip, VCXO, loop filter respectively, and a reference crystal oscillator B, a common formation T phase-locked loop structures, the synchronised clock that T*R road phase place is consistent can be exported simultaneously, wherein T >=2, R >=2, T and R is positive integer, and R is the synchronised clock way that each Clock management chip can export to follow-up R high-speed digital transmission chip.

Clock management chip generally needs to configure its mode of operation by FPGA.After system electrification, first need to be configured Clock management chip, make it can according to predetermined mode of operation.First provide work clock Clock0 by work crystal oscillator A to FPGA, FPGA produces configuration words to Clock management chip, configures it and normally works.FPGA receives the view data from cmos image sensor transmission simultaneously, and buffer memory.The configuration words inputted in Clock management chip can control SPI logic selector gating divide ratio, produces the clock signal of required frequency, exports to FPGA and R high-speed digital transmission chip respectively.FPGA receives the clock signal C lock1 from Clock management chip, and the view data of buffer memory is exported to corresponding high-speed digital transmission chip.Described Clock management chip can adopt the chip of the models such as CDC421A100, CDCE62005 of TI company.

As shown in Figure 2, for the cut-away view of Clock management chip, comprise phase discriminator (PFD), SPI logic selector (SPI LOGIC), reference clock frequency divider (REF Diriver M), feedback divider (VCXO Diriver N), P frequency divider, phase discriminator input selector (FB_MUX) and output frequency selector (Y0_MUX, Y1_MUX ...).SPI logic selector identifiable design configuration words controls the parameter M of reference clock frequency divider, the Parameter N of feedback divider, the parameter P of P frequency divider (P Diriver), phase discriminator input selector and the crossover frequency selected by output frequency selector.Wherein configuration words divide ratio is set will according to the rational frequency division mode of formula (1) design alternative, final output frequency can select the P crossover frequency of VCXO VCXO to export according to system requirements.VCXO_IN is the frequency of VCXO feedback, by Clock management chip outputting charge pump signal CP_OUT to VCXO, exports VCXO_IN and feed back to Clock management chip after adjustment VCXO phase place.REF_CLK is the clock frequency with reference to crystal oscillator B input.M, N, P divide ratio all for being controlled by configuration words, its size calculates can determine according to following three equation.

VCXO_IN/REF_CLK＝(N*P)/M (1)

P＝VCXO_IN/fout (2)

fp＝REF_CLK/M (3)

F in formula _outfor output frequency; f _pfor phase demodulation frequency, phase demodulation frequency is larger, and phase error is larger, so phase demodulation frequency should be as far as possible little, but the locking time of less phase-locked loop is longer, and therefore the size of phase demodulation frequency will be compromised selection.

Figure 3 shows that third order PLL path filter circuit diagram, this filter is used for the HFS of filtering charge pump signal CP_OUT.If

$\left\{\begin{array}{c}{x}_0=C_2{R}_1\\ x_1=C_1{C}_2{C}_3{R}_1{R}_2\\ x_2=C_1{C}_2{R}_1+C_1{C}_3{R}_2+C_2{C}_3{R}_1+C_2{C}_3{R}_2\\ x_3=C_1+C_2+C_3\end{array}\right.---\left(4\right)$

Its transfer function is

$H\left(s\right)=\frac{1+{\mathrm{sx}}_0}{s^3{x}_1+s^2{x}_2+{\mathrm{sx}}_3}---\left(5\right)$

Wherein s=j ω.R represents resistance value, and C represents capacitance.

The most important two indices of loop filter, one is loop bandwidth, and one is phase margin.Loop bandwidth is less, and loop can suppress the noise from reference source, phase discriminator and frequency divider, but can not well suppress the noise of VCXO; When but loop bandwidth is larger, although have good suppression to the noise of VCXO, poor to the noise suppressed of other modules, noise is increased.Loop bandwidth generally can be got between the 1/10-1/20 of reference frequency.Loop bandwidth value can be changed by adjusting resistance R2.Phase margin is a very important performance parameter in circuit design, be mainly used to the stability weighing degeneration factor, it can be regarded as the phase place change that can increase before system enters labile state, phase margin is larger, system is more stable, but cause response speed to slow down, therefore must consider stability and response speed, select a phase margin comparing compromise.For this system, the selection of phase margin is best between 55 ° to 80 °.

Consistent with the data signal phase that FPGA exports in order to ensure the clock being supplied to high-speed digital transmission chip, Clock management chip will export a road clock to FPGA as work clock Clock1 simultaneously.FPGA Clock1 exports R road view data to R corresponding high-speed digital transmission chip as synchronised clock.

If need to use two panels Clock management chip, each Clock management chip will export a road clock signal to FPGA as work clock, is Clock1 and Clock2 respectively.FPGA needs to export 2R road single ended clock with Clock1 and Clock2 as synchronised clock respectively and is supplied to corresponding 2R high-speed digital transmission chip (the corresponding way of each clock passes).More than two panels in like manner analogize.

Such as, large face array CMOS image sensor has the view data of five passages to export simultaneously, and data rate is 250MHz, as shown in Figure 4.In order to improve reliability, adopt the high-speed digital transmission chip of 10 certain models to receive with main backup mode, the receiving velocity that number passes chip requirement is not less than 100MHz.The every sheet of certain model Clock management chip can provide at most 5 road LVPECL differential clocks or 10 tunnels single-ended LVCMOS clock signal.Because Clock management chip often couple of clock output pin A/B has identical unmodifiable phase equalization, therefore make their active and standby single ended clock output each other, such as, in Fig. 3 Y1_A, Y1_B.According to above-mentioned principle, this programme need use two panels timer manager to provide clock signal.In order to keep the phase place concord of clock signal and data-signal, every sheet timer manager also will provide a road clock to FPGA while exporting to number biography clock signal chip, and FPGA exports to corresponding number by the corresponding clock generating number number of delivering a letter and passes chip.

During system starts, first FPGA receives the 100MHz clock that crystal oscillator A provides, produce 2 group configuration words of configurable clock generator managing chip, allow first Clock management chip export 4 road LVCMOS clock signals and a road LVPECL differential clocks Clock1 of 100MHz frequency, allow second Clock management chip export 6 road LVCMOS clock signals and a road LVPECL differential clocks Clock2 of 100MHz frequency.Two panels Clock management chip as with reference to clock, carries out phase compare with the VCXO of respective 400MHz by the same 40MHz clock signal with reference to crystal oscillator B output.This system phase demodulation frequency selects 200KHz, obtains parameter M, N, P are respectively M=200, N=250, P=4 according to formula (1) (2) (3).The 10 road LVCMOS clock signals that two panels Clock management chip produces directly export to high-speed digital transmission chip, FPGA receives two differential clocks from two panels Clock management chip, with Clock1 the 1st, 2 circuit-switched data give active and standby part that number passes chip 1,2, with Clock2 the 3rd, 4,5 circuit-switched data give active and standby part that number passes chip 3,4,5.

Show according to actual test result, the digital dock manager (DCM) in fpga chip can be operated between 48 ~ 450MHz, and the measured result of its input and output jitter tolerance is all at 250ps ~ 300ps.The duty ratio measured result of output clock is all 52% ~ 55%.And using Clock System Design method of the present invention, output clock can be made to shake and control at about 50ps, output clock duty ratio is strict controlled between 49% ~ 51%.Therefore, adopt present system greatly can improve clock quality, reduce clock jitter to the impact of system signal noise ratio.

The content be not described in detail in specification of the present invention belongs to the known technology of those skilled in the art.

Claims (4)

1. the synchronized clock system of a super large face battle array CMOS camera multipath high-speed signal, it is characterized in that: the Clock management chip, the T loop filter that comprise work crystal oscillator, reference crystal oscillator, a T VCXO, programmable logic device FPGA, T band phase locked looped function, T is positive integer, wherein:

Work crystal oscillator: for programmable logic device FPGA provides work clock;

Programmable logic device FPGA: with the work clock of the crystal oscillator that works for benchmark, receive T*R road view data from cmos image sensor, R is positive integer, produces T frequency dividing control amount P simultaneously _tand deliver to T Clock management chip respectively, each frequency dividing control amount P _ta corresponding Clock management chip; T circuit-switched data synchronised clock is obtained from T Clock management chip, utilize each circuit-switched data synchronised clock the R road received in view data to be exported to the outside R number corresponding with this circuit-switched data synchronised clock and pass chip, the corresponding number of each road view data passes chip;

Clock management chip: total T, each Clock management chip and reference crystal oscillator, VCXO structure, a loop filter form a phase-locked loop; For each phase-locked loop, according to the frequency dividing control amount P of input _t, P is carried out to the output frequency of VCXO _tfrequency division, produce R+1 circuit-switched data synchronised clock, wherein R circuit-switched data synchronised clock is delivered to the outside R number corresponding with this Clock management chip respectively and is passed chip, and programmable logic device FPGA delivered to by a remaining circuit-switched data synchronised clock;

With reference to crystal oscillator: for T Clock management chip produces the reference clock of homology;

VCXO: total T, according to the clock signal of the charge pump signal generation respective phase that the Clock management chip of correspondence exports, and feeds back to Clock management chip;

Loop filter: total T, the HFS of charge pump signal described in filtering, the voltage signal after filtering controls the frequency of oscillation of VCXO.

2. the synchronized clock system of a kind of super large face according to claim 1 battle array CMOS camera multipath high-speed signal, is characterized in that: described R >=2, and T >=2.

3. the synchronized clock system of a kind of super large face according to claim 1 and 2 battle array CMOS camera multipath high-speed signal, is characterized in that: the frequency of described R+1 circuit-switched data synchronised clock is not less than 100M.

4. the synchronized clock system of a kind of super large face according to claim 1 and 2 battle array CMOS camera multipath high-speed signal, is characterized in that: described loop filter is the passive low ventilating filter on three rank.