CN111736576A - Image time synchronization controller testing tool and testing method thereof - Google Patents
Image time synchronization controller testing tool and testing method thereof Download PDFInfo
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- CN111736576A CN111736576A CN202010764912.1A CN202010764912A CN111736576A CN 111736576 A CN111736576 A CN 111736576A CN 202010764912 A CN202010764912 A CN 202010764912A CN 111736576 A CN111736576 A CN 111736576A
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Abstract
The invention provides a testing tool and a testing method for an image time synchronization controller, belonging to the technical field of interface testing.A processor, a primary transmission input port, a primary transmission output port, a secondary transmission input port and a secondary transmission output port which are respectively and electrically connected with the processor are arranged in the image time synchronization controller; the system comprises a power supply, an image collector, a switch, an upper computer and a high-low temperature test box, wherein a plurality of image time synchronization controllers are positioned in the high-low temperature test box; the image collector is electrically connected with the first image time synchronization controller and sends an image signal to the first image time synchronization controller, and the image time synchronization controller feeds the image signal back to the switch; the exchanger sends and receives the image signal to the subsequent image time synchronization controller in sequence; the upper computer is electrically connected with the switch, and the upper computer receives the image signals fed back by the image time synchronization controllers through the switch. The cascade test of a plurality of image time synchronization controllers is realized, and the test efficiency is improved.
Description
Technical Field
The invention relates to the technical field of interface testing, in particular to a testing tool and a testing method for an image time synchronization controller.
Background
The image time synchronization controller is used for processing image information and sending an image signal to the image time synchronization controller through the image collector so that the image time synchronization controller can process images. When the image time synchronization controller is used, the image time synchronization controller is generally used in an environment with large temperature difference, and therefore whether signal transmission of each interface of the image time synchronization controller is normal or not in the environment with large temperature difference needs to be tested before the image time synchronization controller is used.
Generally, high and low temperature tests are adopted to simulate a use environment with large temperature difference, the image time synchronization controller is placed in a high and low temperature test box, and signal tests are carried out on each interface of a single image time synchronization controller. However, the time for simulating the high and low temperature cycle state in the high and low temperature test box is long, and during batch test, a plurality of image time synchronization controllers need to be tested in the high and low temperature test box, and the high and low temperature cycle in the high and low temperature test box needs to be performed for a plurality of times, so that the test efficiency of the batch image time synchronization controllers is low.
Disclosure of Invention
The invention aims to provide a testing tool and a testing method for an image time synchronous controller, which can finish batch testing of the image time synchronous controller in a high-low temperature testing box at one time and have high testing efficiency.
The embodiment of the invention is realized by the following steps:
one aspect of the embodiments of the present invention provides an image time synchronization controller testing tool, configured to test a plurality of image time synchronization controllers, where a processor, a primary transmission input port, a primary transmission output port, a secondary transmission input port, and a secondary transmission output port are arranged in each of the image time synchronization controllers, and are electrically connected to the processor; the image time synchronization controller testing tool comprises a power supply, an image collector, a switch, an upper computer and a high and low temperature testing box, wherein the power supply is electrically connected with the plurality of image time synchronization controllers respectively and used for supplying power to the plurality of image time synchronization controllers respectively; the plurality of image time synchronization controllers are positioned in the high and low temperature test box; the image collector is electrically connected with a primary transmission input port of a first image time synchronization controller and used for sending image signals to the first image time synchronization controller, and the first image time synchronization controller receives the image signals through the primary transmission input port and feeds the image signals back to the switch through the processor and the primary transmission output port in sequence; the switch is provided with a plurality of ports, a first primary transmission output port of the image time synchronization controller, a first secondary transmission input port of the image time synchronization controller, a first secondary transmission output port of the image time synchronization controller are respectively and electrically connected with the ports of the switch in a one-to-one correspondence manner, a plurality of subsequent primary transmission input ports of the image time synchronization controller, a plurality of primary transmission output ports of the image time synchronization controller, a plurality of secondary transmission input ports of the image time synchronization controller and a plurality of secondary transmission output ports of the image time synchronization controller are also electrically connected with the ports of the switch in a one-to-one correspondence manner, and image signals sent by the image collector sequentially pass through the primary transmission input port of the image time synchronization controller, the processor of the first image time synchronization controller, A first-level transmission output port of the first image time synchronization controller, the switch, a second-level transmission input port of the first image time synchronization controller, a processor of the first image time synchronization controller, and a second-level transmission output port of the first image time synchronization controller are fed back to the switch, according to the transmission mode of the image signals, the exchanger transmits the image signals back to the exchanger through a primary transmission input port of a plurality of subsequent image time synchronization controllers, a processor of the plurality of image time synchronization controllers, a primary transmission output port of the plurality of image time synchronization controllers, a secondary transmission input port of the plurality of image time synchronization controllers, a processor of the plurality of image time synchronization controllers and a secondary transmission output port of the plurality of image time synchronization controllers in sequence; the upper computer is electrically connected with the switch and receives image signals fed back after sequentially passing through the plurality of image time synchronization controllers through the switch; and the upper computer also receives a plurality of working states of a plurality of ports corresponding to the image time synchronization controller, which are monitored and sent by the switch.
Optionally, still be equipped with a plurality of 485 interfaces on the image time synchronization controller, the host computer respectively with the treater and a plurality of 485 interface electricity is connected, and is a plurality of 485 interfaces respectively with the treater electricity is connected, the host computer sends the signal respectively and gives a plurality of 485 interfaces, and is a plurality of 485 interfaces will respectively the signal feedback gives the treater, the treater is again with a plurality of the signal feedback is to the host computer.
Optionally, a conversion interface is arranged between the upper computer and the plurality of 485 interfaces.
Optionally, the upper computer is electrically connected to the plurality of 485 interfaces through twisted pairs.
Optionally, the switch is a three-layer network management switch.
Optionally, still include display and key mouse, the display with the key mouse respectively with the host computer electrical connection, the display is used for showing the information that the host computer was derived, the key mouse is used for operating the host computer.
Another aspect of this embodiment provides a method for testing a plurality of image time synchronization controllers by using the above-mentioned testing tool for image time synchronization controllers, including: the exchanger sequentially sends and receives image signals to each image time synchronization controller according to the working state of each transmission interface of each image time synchronization controller; the switch feeds back the state of each port to the upper computer; the exchanger feeds back image signals fed back after sequentially passing through the plurality of image time synchronization controllers to the upper computer.
Optionally, the sequentially sending and receiving the image signal to each image time synchronization controller by the switch according to the operating state of each transmission interface of each image time synchronization controller includes: when the port of the switch is interrupted with the image signal transmission of the transmission interface of the image time synchronization controller, the switch feeds back the state of the port to the upper computer, and the switch transmits the image signal to the next transmission interface.
Optionally, the method further comprises: the upper computer respectively sends signals to a plurality of 485 interfaces of each image time synchronization controller; and receiving signals fed back by the processors through a plurality of 485 interfaces of each image time synchronization controller.
The embodiment of the invention has the beneficial effects that:
the image time synchronization controller testing tool and the testing method thereof provided by the embodiment of the invention support the cascade test of a plurality of image time synchronization controllers, the plurality of image time synchronization controllers are placed in a high-low temperature testing box, an image signal is sent to a first image time synchronization controller through an image collector, the image time synchronization controller receives the image signal through a primary transmission input port of the image time synchronization controller and feeds the image signal back to an exchanger through a processor and a primary transmission output port of the image time synchronization controller in sequence, and primary image signal transmission is completed. The switch is provided with a plurality of ports, a primary transmission output port of a first image time synchronization controller, a secondary transmission input port of the first image time synchronization controller and a secondary transmission output port of the first image time synchronization controller are respectively and correspondingly electrically connected with the plurality of ports of the switch, the primary transmission input ports of a plurality of subsequent image time synchronization controllers except the first one, the primary transmission output ports of the plurality of image time synchronization controllers, the secondary transmission input ports of the plurality of image time synchronization controllers and the secondary transmission output ports of the plurality of image time synchronization controllers are also in one-to-one correspondence with the plurality of ports of the switch, thus, the first image time synchronization controller feeds back the image signals received by the first-stage transmission input port of the first image time synchronization controller to the switch through the processor and the first-stage transmission output port of the first image time synchronization controller in sequence to complete first-stage transmission; the exchanger transmits the image signal to a secondary transmission input port of the first image time synchronization controller, and the image signal is fed back to the exchanger through the processor and the secondary transmission output port in sequence to complete secondary image signal transmission. The exchanger feeds back the image signal of the secondary transmission output port of the first image time synchronization controller to the exchanger and then transmits the image signal to the primary transmission input port of the second image time synchronization controller, then the second image time synchronization controller completes the primary image signal transmission and the secondary image signal transmission in sequence according to the processes, and completes the image signal transmission of the plurality of image time synchronization controllers one by one in sequence so as to test whether the transmission interface of each image time synchronization controller is normally transmitted in the high-low temperature test box. The upper computer is electrically connected with the switch, and the switch transmits the image signal fed back by the last image time synchronization controller to the upper computer. Thus, a plurality of image time synchronization controllers form a series loop through the switch, image signals are sent to the first image time synchronization controller from the image collector, then the image signals are sequentially transmitted to the next image time synchronization controller through the switch, and finally the upper computer receives the image signals of the last image time synchronization controller; the upper computer also receives the working states of a plurality of ports of the switch so as to monitor the state of each port of the switch and position the fault position of the transmission interface of the image time synchronization controller. The image time synchronization controller testing tool and the testing method thereof provided by the embodiment of the invention test whether the transmission interfaces of all the image time synchronization controllers on the serial loop can normally transmit image signals. Therefore, the working state of each peer transmission interface of a plurality of image time synchronous controllers can be tested in a high-low temperature test box in one temperature cycle, the test efficiency is greatly improved, and the test time of a single image time synchronous controller is shortened.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a testing tool for an image time synchronization controller according to an embodiment of the present invention;
fig. 2 is a second schematic structural diagram of a testing tool for an image time synchronization controller according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for testing an image time synchronization controller according to an embodiment of the present invention.
Icon 1-camera; 2-bond mouse; 3-a switch; 4-image time synchronization controller; 5-a power supply; 6-a display; 7-an upper computer; 8-twisted pair; converting 10-USB to 485 conversion interface; LAN 1-primary transport output; LAN 2-primary transport input port; LAN 3-secondary transport input port; LAN 4-two-level transport outlet.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Example one
The image time synchronization controller 4 is one of important hardware of the TDS intelligent dry separator, is a core device of an image recognition system, and is mainly used for time synchronization triggering of the image recognition system.
When the image time synchronization controller 4 is used, an image signal is sent to the image time synchronization controller 4 through the image collector, so that the image time synchronization controller 4 performs image processing. In addition, the image time synchronization controller 4 is generally used in an environment with a large temperature difference, and in order to ensure normal use, a high-temperature and low-temperature test is required to simulate a use environment with a large temperature difference before use, so as to test whether image signal transmission of each interface of the image time synchronization controller 4 is normal.
In the conventional test, a single image time synchronization controller 4 is placed in a high-low temperature test box, and a signal test is performed on each interface of the single image time synchronization controller 4. However, the time for simulating the one-time high and low temperature cycle state in the high and low temperature test box is long, the temperature in the high and low temperature test box needs to be increased from minus 20 degrees to 60 degrees and then decreased from 60 degrees to minus 20 degrees, the cycle is repeated, and the single image time synchronization controller 4 performs the test at the temperature of the cycle. When the batch image time synchronization controller 4 is to be tested, a plurality of temperature cycles are to be completed in the high-low temperature test box, so that the batch image time synchronization controller 4 is long in test time and low in test efficiency.
On this basis, this embodiment provides an image time synchronization controller test fixture, can once accomplish the batch test of several image time synchronization controllers 4 in high low temperature test box, and single image time synchronization controller 4 test time is short, and batch test efficiency is high.
Referring to fig. 1, the present embodiment provides an image time synchronization controller testing tool, which is used for testing a plurality of image time synchronization controllers 4, the plurality of image time synchronization controllers 4 are located in a high and low temperature testing box (not shown in fig. 2), a processor (not shown in fig. 2) is disposed in the image time synchronization controller 4, and a primary transmission input port LAN2, a primary transmission output port LAN1, a secondary transmission input port LAN3, and a secondary transmission output port LAN4, which are electrically connected to the processor, respectively.
The image time synchronization controller testing tool comprises a power supply 5, an image collector, a switch 3, an upper computer 7 and a high-low temperature testing box, wherein the power supply 5 is electrically connected with a plurality of image time synchronization controllers 4 through power supply 5 lines respectively and used for supplying power to the plurality of image time synchronization controllers 4 respectively; the power supply 5 is a 24VDC (24 volts dc) power supply 5.
Of course, the image collector, the switch 3, the upper computer 7, the high and low temperature test box and the like also have power supplies for supplying power to the image collector, the power supplies are necessary functions of electric devices, and detailed description is omitted here.
As shown in fig. 2, the image collector may be a camera 1, the camera 1 is electrically connected to a first image time synchronization controller 4 for sending image signals to the image time synchronization controller 4, and the first image time synchronization controller 4 receives the image signals through its primary transmission input port LAN2 and feeds back the image signals to the switch 3 through its processor and primary transmission output port LAN1 in turn, so as to complete primary image signal transmission.
The switch 3 has a plurality of ports, the primary transfer output port LAN1 of the first image time synchronization controller 4, the secondary transfer input port LAN3 of the first image time synchronization controller 4, and the secondary transfer output port LAN4 of the first image time synchronization controller 4 are electrically connected to the plurality of ports of the switch 3 in a one-to-one correspondence, the primary transfer input ports LAN2 of the plurality of subsequent image time synchronization controllers 4 except the first one, the primary transfer output port LAN1 of the plurality of image time synchronization controllers 4, the secondary transfer input ports LAN3 of the plurality of image time synchronization controllers 4, and the secondary transfer output ports LAN4 of the plurality of image time synchronization controllers 4 are electrically connected to the plurality of ports of the switch 3 in a one-to-one correspondence, and the image signal transmitted from the camera 1 sequentially passes through the primary transfer input port LAN2 of the first image time synchronization controller 4, the processor of the first image time synchronization controller, The primary transmission output port LAN1 of the first image time synchronization controller 4, the switch 3, the secondary transmission input port LAN3 of the first image time synchronization controller 4, the processor of the first image time synchronization controller 4, and the secondary transmission output port LAN4 of the first image time synchronization controller 4 are fed back to the switch, and according to the transmission mode of the image signals, the switch 3 transmits the image signals back to the switch 3 via the primary transmission input ports LAN2 of the subsequent plurality of image time synchronization controllers 4, the processors of the plurality of image time synchronization controllers 4, the primary transmission output ports LAN1 of the plurality of image time synchronization controllers 4, the secondary transmission input ports LAN3 of the plurality of image time synchronization controllers 4, the processors of the plurality of image time synchronization controllers 4, and the secondary transmission output ports LAN4 of the plurality of image time synchronization controllers 4 in sequence.
Specifically, the switch 3 has a plurality of ports, each port is correspondingly connected with a corresponding transmission interface, and the plurality of ports are electrically connected with the primary transmission output port LAN1 of the first image time synchronization controller 4, the secondary transmission input port LAN3 of the first image time synchronization controller 4, and the secondary transmission output port LAN4 of the first image time synchronization controller 4 in sequence, so that the first image time synchronization controller 4 receives the image signal of the camera 1 through the primary transmission input port LAN2 thereof, and feeds back the image signal to the switch 3 through the processor thereof and the primary transmission output port LAN1 thereof in sequence, and then completes the primary image signal transmission; the switch 3 transmits the image signal to the secondary transmission input port LAN3 of the first image time synchronization controller 4, and then feeds back the image signal to the switch 3 through the processor and the secondary transmission output port LAN4 in sequence, thereby completing the transmission of the secondary image signal. This completes the image signal transmission of the first image time synchronization controller 4.
When the image signal of the second image time synchronization controller 4 is transmitted, the switch 3 retransmits the image signal fed back to the switch 3 from the secondary transmission output port LAN4 of the first image time synchronization controller 4 to the primary transmission input port LAN2 of the second image time synchronization controller 4, then the image signal is transmitted to the switch 3 via the processor of the second image time synchronization controller 4, the primary transmission output port LAN1 of the second image time synchronization controller 4, the switch 3 transmits the image signal to the secondary transmission input port LAN3 of the second image time synchronization controller 4, and is fed back to the switch 3 through the processor of the second image time synchronization controller 4 and the secondary transmission output port LAN4 of the second image time synchronization controller 4 in sequence, thereby completing the primary image signal transmission and the secondary image signal transmission of the second image time synchronization controller 4.
Then, the image signal is transmitted to the third image time synchronization controller 4 and the fourth image time synchronization controller 4 … … through the switch 3, and so on, and the image signal transmission of the plurality of image time synchronization controllers 4 is completed one by one according to the transmission process, so as to test whether the peer transmission interface of each image time synchronization controller 4 is normally transmitted in the high and low temperature test box.
The upper computer 7 is electrically connected with the switch 3, the upper computer 7 receives image signals fed back after sequentially passing through the plurality of image time synchronization controllers 4 through the switch 3, and the upper computer 7 also receives the working states of a plurality of ports of the switch 3.
The upper computer 7 receives the image signal of the last image time synchronization controller 4 transmitted by the switch 3, so that a plurality of image time synchronization controllers 4 form a serial loop through the switch 3, the upper computer 7 receives the image signal of the last image time synchronization controller 4, and whether the same-level transmission interfaces of all the image time synchronization controllers 4 on the serial loop can normally transmit the image signal is tested.
It should be noted that before the test starts, it is ensured that each port of the switch 3 has the capability of normally transmitting signals, and at the same time, the upper computer 7 performs function setting on the switch 3, so that the switch 3 can complete the predetermined information conversion requirement. In the test process, when image signals are transmitted in the plurality of image time synchronization controllers 4 in sequence, if no fault occurs in the process of transmitting the image signals, the control of the upper computer 7 is not needed.
In addition, the switch 3 is a three-layer network management switch 3, the three-layer network management switch 3 is mainly used for internal network division and management, and the division mode can be used for network segment division according to geographical positions, departments, floors and the like, namely a so-called Vlan function. The same Vlan can be divided by the port between every two layers of the switch 3, when a certain transmission interface of a certain image time synchronization controller 4 fails and cannot transmit, the port through which the switch 3 is communicated with the interface cannot receive an image signal, but because of the Vlan function, the switch 3 can skip the failed interface, and the image signal is transmitted to the next-stage transmission interface through the Vlan of the next layer, so that the image signal can be transmitted to the next-stage transmission interface.
On the other hand, the upper computer 7 also receives the operating states of the ports of the switch 3 to monitor the states of the ports of the switch 3. The upper computer 7 can receive and analyze the states of all the ports of the switch 3.
The port states of the switch 3 include a transmission normal state and a transmission interruption state.
When a transmission interface of a certain image time synchronization controller 4 is normal, the transmission interface and the port of the switch 3 can normally transmit, the switch 3 feeds back the normal transmission state to the upper computer 7, when an image signal passes through the transmission interface, the image signal is normally transmitted between the transmission interface and the port of the switch 3, at the moment, the upper computer 7 does not receive the image signal in the test process, only receives the normal transmission state of the port of the switch 3, and judges whether the corresponding transmission interface is normal or not.
When a transmission interface of a certain image time synchronization controller 4 breaks down, the transmission of the transmission interface and a port of the switch 3 is interrupted, the switch 3 feeds the transmission interruption state back to the upper computer 7, and the upper computer 7 can locate the position where the failure occurs, so that the image time synchronization controller 4 and the transmission interface thereof which break down are found.
In the test process, host computer 7 reads the state of every port of switch 3 in real time, when the transmission image signal process broke down, and certain port transmission interrupt state is received to host computer 7, and host computer 7 can carry out the function setting to switch 3 again automatically, makes image signal can skip the trouble transmission interface that corresponds image time synchronization controller 4, continues transmission image signal through next stage transmission interface to this guarantees image signal one-level transmission.
The primary transport input port LAN2 and the primary transport output port LAN1 are the same level of transport interface, and the secondary transport input port LAN3 and the secondary transport output port LAN4 are the same level of transport interface. When one transmission interface in the same level transmission interface has a fault, the same level transmission interface is judged to have the fault, and the other transmission interface in the same level transmission interface does not need to judge whether the transmission interface is normal or not.
Here, when a failure occurs in one of the primary transfer interfaces of the first image time synchronization controller 4, that is, the primary transfer input port LAN2 of the first image time synchronization controller 4 and the primary transfer output port LAN1 of the first image time synchronization controller 4, the entire transfer cannot be performed.
If the primary transmission input port LAN2 of the first image time synchronization controller 4 fails, the image signal transmitted from the camera 1 cannot be received, and accordingly, the primary transmission output port LAN1 of the first image time synchronization controller 4 cannot receive the image signal, that is, cannot transmit the image signal to the corresponding port of the switch 3, and the whole transmission cannot be performed. The upper computer 7 can locate the position where the fault occurs, and judges that the first-level transmission input port LAN2 of the first image time synchronization controller 4 has the fault.
Similarly, when the primary transmission output port LAN1 of the first image time synchronization controller 4 fails, the image signal received by the primary transmission input port LAN2 of the first image time synchronization controller 4 cannot be transmitted to the primary transmission output port LAN1 of the first image time synchronization controller 4, the transmission between the ports corresponding to the switch 3 is interrupted, the subsequent whole transmission cannot be performed, and the upper computer 7 can locate the failed position.
There are three processing modes for the two situations:
first, before starting the inspection, the primary transfer input port LAN2 of the first image time synchronization controller 4 and the primary transfer output port LAN1 of the first image time synchronization controller 4 are tested in advance to ensure that the subsequent transfer can be performed. The first image time synchronization controller 4 may be replaced if any one of the primary transmission input port LAN2 of the first image time synchronization controller 4 and the primary transmission output port LAN1 of the first image time synchronization controller 4 fails.
Second, when the detection is performed, if any one of the primary transmission input port LAN2 of the first image time synchronization controller 4 and the primary transmission output port LAN1 of the first image time synchronization controller 4 fails, the switch 3 cannot receive the image signal, and at this time, the first image time synchronization controller 4 can be replaced by human intervention.
Thirdly, when the detection is performed, if any one of the primary transmission input port LAN2 of the first image time synchronization controller 4 and the primary transmission output port LAN1 of the first image time synchronization controller 4 fails, the switch 3 cannot receive the image signal, and at this time, the camera 1 may be directly connected to one port of the switch 3, so that the image signal sent by the camera 1 is directly transmitted to the switch 3, and then the switch 3 transmits the image signal to the secondary transmission input port LAN3 of the first image time synchronization controller 4, and sequentially transmits the image signal.
Therefore, the primary transmission input port LAN2 of the first image time synchronization controller 4 and the primary transmission output port LAN1 of the first image time synchronization controller 4 are preconditions for ensuring that the transmission can be performed normally.
For efficiency, each transmission interface of the first image time synchronization controller 4 may be manually tested before testing to ensure that at least the primary transmission input port LAN2 of the first image time synchronization controller 4 and the primary transmission output port LAN1 of the first image time synchronization controller 4 are normal during testing.
During the test, when a failure occurs in the other transmission interfaces except the primary transmission input port LAN2 of the first image time synchronization controller 4 and the primary transmission output port LAN1 of the first image time synchronization controller 4, the Vlan function of the switch 3 automatically skips the failed transmission interface, and the next transmission is performed.
The image time synchronization controller test tool further comprises a display 6 and a keyboard and mouse 2, the display 6 and the keyboard and mouse 2 are respectively electrically connected with the upper computer 7, the display 6 provides an interface for displaying information derived by the upper computer 7, and the keyboard and mouse 2 is used for operating the upper computer 7. Therefore, information checking and operation are convenient.
The image time synchronization controller test tool supports the cascade test of a plurality of image time synchronization controllers 4, the image time synchronization controllers 4 are placed in a high-temperature and low-temperature test box, an image signal is sent to a first image time synchronization controller 4 through a camera 1, the image time synchronization controller 4 receives the image signal through a primary transmission input port LAN2 of the image time synchronization controller and feeds back the image signal to an exchanger 3 through a processor and a primary transmission output port LAN1 of the image time synchronization controller in sequence, and primary image signal transmission is completed.
The switch 3 has a plurality of ports, the primary transmission output port LAN1 of the first image time synchronization controller 4, the secondary transmission input port LAN3 of the first image time synchronization controller 4, and the secondary transmission output port LAN4 of the first image time synchronization controller 4 are electrically connected to the plurality of ports of the switch 3 in a one-to-one correspondence, respectively, the primary transmission input ports LAN2 of the plurality of image time synchronization controllers other than the first, the primary transmission output port LAN1 of the plurality of image time synchronization controllers, the secondary transmission input ports LAN3 of the plurality of image time synchronization controllers, and the secondary transmission output port LAN4 of the plurality of image time synchronization controllers are also electrically connected to the plurality of ports of the switch 3 in a one-to-one correspondence, so that after the image signal received by the first image time synchronization controller 4 through its primary transmission input port LAN2 is fed back to the switch 3 through its processor and its primary transmission output port LAN1 in sequence, completing the primary transmission; the switch 3 transmits the image signal to the secondary transmission input port LAN3 of the first image time synchronization controller 4, and then feeds back the image signal to the switch 3 via the processor thereof and the secondary transmission output port LAN4 in turn, thereby completing the transmission of the secondary image signal. The switch 3 transmits the image signal fed back to the switch 3 from the secondary transmission output port LAN4 of the first image time synchronization controller 4 to the primary transmission input port LAN2 of the second image time synchronization controller 4, and then the second image time synchronization controller 4 completes the primary image signal transmission and the secondary image signal transmission in sequence according to the above process, and completes the image signal transmission of the plurality of image time synchronization controllers one by one in sequence, so as to test whether the peer transmission interface of each image time synchronization controller 4 is normally transmitted in the high and low temperature test box.
The upper computer 7 is electrically connected with the exchanger 3, and the exchanger 3 transmits the image signal fed back by the last image time synchronization controller 4 to the upper computer 7. Thus, the plurality of image time synchronization controllers 4 form a serial loop through the switch 3, the camera 1 sends image signals to the first image time synchronization controller 4, the switch 3 sequentially transmits the image signals to the next image time synchronization controller 4, and the upper computer 7 receives the image signals of the last image time synchronization controller 4, so that whether the transmission interfaces of all the image time synchronization controllers 4 on the serial loop can normally transmit the image signals is tested. Meanwhile, the upper computer 7 also monitors the state of each port of the switch 3 to locate a fault transmission interface of the image time synchronization controller 4. By the image time synchronous controller testing tool, the working state of each level of transmission interfaces of a plurality of image time synchronous controllers 4 can be tested in a high-low temperature testing box in one temperature cycle, the testing efficiency is greatly improved, and the testing time of a single image time synchronous controller 4 is shortened.
Still be equipped with a plurality of 485 interfaces on the image time synchronization controller 4, host computer 7 is connected with treater and a plurality of 485 interface electricity respectively, a plurality of 485 interfaces are connected with the treater electricity respectively, host computer 7 sends the signal respectively and gives a plurality of 485 interfaces, a plurality of 485 interfaces feed back the signal to the treater respectively, the treater feeds back a plurality of signals to host computer 7 again, form a closed loop's signal feedback loop, whether it is normal to transmit with every 485 interface on the test image time synchronization controller 4.
Illustratively, as shown IN fig. 2, the 485 interfaces on the image time synchronization controller 4 are one 485 IN interface and four 485 IN/OUT interfaces.
The signals of the upper computer 7 and the 485 interface are different types of signals and need to be converted. A conversion interface is arranged between the upper computer 7 and the plurality of 485 interfaces and is a USB-to-485 conversion interface 10, and after the USB-to-485 conversion interface 10 converts signals sent by the upper computer 7, the converted signals are received by the 485 interfaces.
The upper computer 7 is electrically connected with the plurality of 485 interfaces through twisted-pair lines 8. Twisted pair 8 (TP) is the most common transmission medium in integrated wiring engineering, and is composed of two copper wires with insulation protection layers. Two insulated copper wires are twisted together according to a certain density, and the electric wave radiated by each wire in transmission can be counteracted by the electric wave emitted by the other wire, thereby effectively reducing the degree of signal interference.
Example two
As shown in fig. 3, this embodiment provides a method for testing an image time synchronization controller, where the apparatus for testing an image time synchronization controller according to the first embodiment is applied to test a plurality of image time synchronization controllers 4, and in a transmission process of an image signal, an exchange 3 determines a working state of each transmission interface of each image time synchronization controller 4 in sequence according to whether the image signal is transmitted normally, where the image signal is an image signal sent by an image collector to a first image time synchronization controller 4. The method comprises the following steps:
the test presupposes that each port of the switch 3 can normally transmit signals. The upper computer 7 can read the state of each port of the switch 3 to judge whether the transmission interface of the image time synchronization controller 4 connected with the port can normally transmit.
S100: the exchanger 3 sequentially sends and receives image signals to each image time synchronization controller 4 according to the working state of each transmission interface of each image time synchronization controller 4; the switch 3 feeds back the state of each port to the upper computer 7, and the upper computer 7 can locate the position of the fault.
Specifically, when the transmission of the image signal between the port of the switch 3 and the transmission interface of the image time synchronization controller 4 connected correspondingly is interrupted, the switch 3 feeds back the state of the port to the upper computer 7, and the switch 3 transmits the image signal to the next-stage transmission interface.
Taking three image time synchronization controllers 4 as an example, the test process is specifically described:
the camera 1 sends an image signal to a first image time synchronization controller 4, and the image time synchronization controller 4 receives the image signal through a primary transmission input port LAN2, and feeds back the image signal to the switch 3 through a processor thereof and a primary transmission output port LAN1 in sequence to complete primary image signal transmission thereof; the switch 3 transmits the image signal to the secondary transmission input port LAN3 of the first image time synchronization controller 4, and then feeds back the image signal to the switch 3 via its processor and its secondary transmission output port LAN4 in order to complete the transmission of the secondary image signal, thereby completing the transmission of the image signal between the transmission interfaces of the first image time synchronization controller 4.
The switch 3 receives the image signal fed back to the switch 3 from the secondary transmission output port LAN4 of the first image time synchronization controller 4, and then transmits the image signal to the primary transmission input port LAN2 of the second image time synchronization controller 4, and feeds the image signal back to the switch 3 through the processor of the image time synchronization controller 4 and the primary transmission output port LAN1 in sequence, thereby completing the primary transmission of the second image time synchronization controller 4.
The switch 3 transmits the image signal to the secondary transmission input port LAN3 of the second image time synchronization controller 4, and feeds back the image signal to the switch 3 via the processor and the secondary transmission output port LAN4 in turn, thereby completing the secondary transmission of the second image time synchronization controller 4.
The switch 3 receives the image signal fed back to the switch 3 from the secondary transmission output port LAN4 of the second image time synchronization controller 4, and then transmits the image signal to the primary transmission input port LAN2 of the third image time synchronization controller 4, and feeds the image signal back to the switch 3 through the processor of the image time synchronization controller 4 and the primary transmission output port LAN1 in sequence, thereby completing the primary transmission of the third image time synchronization controller 4.
The switch 3 transmits the image signal to the secondary transmission input port LAN3 of the third image time synchronization controller 4, and feeds back the image signal to the switch 3 via the processor and the secondary transmission output port LAN4 in turn, thereby completing the secondary transmission of the third image time synchronization controller 4.
The switch 3 then sequentially sends and receives image signals to the fourth and fifth … … image time synchronization controllers 4. In the process of transmitting the image signal, if each port of the switch 3 and the transmission interface of the corresponding image time synchronization controller 4 can normally transmit the image signal, it indicates that each transmission interface of the image time synchronization controller 4 can normally transmit. In this way, the working state of the transmission interface of the image time synchronization controller 4 is judged.
S110: the exchanger 3 feeds back image signals fed back after sequentially passing through the plurality of image time synchronization controllers 4 to the upper computer 7.
That is, the image signals are sequentially transmitted in series between the plurality of image time synchronization controllers 4 in the above-described procedure, and when the image signals are transmitted to the last image time synchronization controller 4, the switch 3 feeds back the secondary transmission output port LAN4 of the last image time synchronization controller 4 to the upper computer 7.
The switch 3 finally feeds back the image signal transmitted from the secondary transmission output port LAN4 of the last image time synchronization controller 4 to the upper computer 7.
After the exchanger 3 sequentially sends and receives image signals to the next image time synchronization controller 4, the exchanger 3 feeds back the image signal of the last image time synchronization controller 4 to the upper computer 7 through secondary transmission thereof, so that a plurality of image time synchronization controllers 4 form a serial loop through the exchanger 3, the upper computer 7 receives the image signal of the last image time synchronization controller 4, and whether the same-level transmission interfaces of all the image time synchronization controllers 4 on the serial loop can normally transmit the image signal is tested.
And after the upper computer 7 receives the image signal of the last image time synchronization controller 4, a test result is produced, the test result is recorded in the upper computer 7, and the test result is displayed through the display 6 so as to be conveniently checked.
On the other hand, the switch 3 feeds back the status of each port to the upper computer 7, and the upper computer 7 can locate the position where the fault occurs.
Specifically, the upper computer 7 reads the state of each port in real time, when a transmission interface of a certain image time synchronization controller 4 fails, the transmission of image signals between the port of the switch 3 and the transmission interface is interrupted, the port of the switch 3 cannot transmit the image signals, the switch 3 feeds back the transmission interruption state of the port to the upper computer 7, and the upper computer 7 can position the position of the port, so that the transmission interface of the corresponding image time synchronization controller 4 is determined, and the transmission interface of the image time synchronization controller 4 with the failure is found out. While fault records are generated for review.
Moreover, in order to avoid influencing other image time synchronization controllers 4 on the serial circuit, after the upper computer 7 locates the fault image time synchronization controller 4, the upper computer 7 can automatically reset the function of the switch 3, so that the image signal can skip the fault image time synchronization controller 4, and the switch 3 can transmit the image signal to the next-stage transmission interface so as to continue to test each image time synchronization controller 4.
Further, taking the three image time synchronization controllers 4 as an example, how to perform the test when a fault occurs is described:
during the test, it is assumed that the first-stage transmission input port LAN2 of the first image time synchronization controller 4 has failed:
the primary transmission input port LAN2 of the first image time synchronization controller 4 cannot transmit the image signal to the primary transmission output port LAN1 of the first image time synchronization controller 4, and the switch 3 cannot receive the image signal, but the port of the switch 3 displays that the primary transmission output port LAN1 of the first image time synchronization controller 4 is normally connected to the port, but does not transmit the image signal between the two, which indicates that the primary transmission input port LAN2 of the first image time synchronization controller 4 is faulty, and at this time, manual intervention is required to directly connect the camera 1 to the switch 3, and the switch 3 directly receives the image signal sent by the camera 1, and then transmits the image signal to the next transmission interface, that is, the secondary transmission input port LAN3 of the first image time synchronization controller 4, and sequentially transmits the image signal.
Assume that the primary transport output port LAN1 of the first image time synchronization controller 4 fails: after the image signal sent by the camera 1 is received by the primary transmission input port LAN2 of the first image time synchronization controller 4, the processor causes the primary transmission output port LAN1 of the first image time synchronization controller 4 not to receive the image signal, and thus not to transmit the image signal to the switch 3, at this time, the port of the switch 3 is interrupted in transmission with the primary transmission output port LAN1 of the first image time synchronization controller 4, the switch 3 feeds back the interrupted state of the port transmission to the upper computer 7, the upper computer 7 positions that the failure occurs in the primary transmission output port LAN1 of the first image time synchronization controller 4, at this time, the camera 1 needs to be directly connected with the switch 3 by manual intervention, the switch 3 directly receives the image signal sent by the camera 1, and then transmits the image signal to the next-stage transmission interface, that is, the image signal is transmitted to the secondary transmission input port LAN3 of the first image time synchronization controller 4, the image signals are sequentially transferred.
Assume that the second-level transmission input port LAN3 of the first image time synchronization controller 4 fails: the port of the switch 3 and the secondary transmission input port LAN3 of the first image time synchronization controller 4 are interrupted in transmission, the switch 3 feeds back the state of the port to the host computer 7, the host computer 7 locates that the secondary transmission input port LAN3 of the first image time synchronization controller 4 is faulty, and automatically skips the faulty transmission interface through the Vlan function of the switch 3, skips the secondary transmission output port LAN4 at the same level as the secondary transmission input port LAN3, and transmits the faulty transmission interface to the next transmission interface, that is, the switch 3 transmits the image signal to the primary transmission input port LAN2 of the second image time synchronization controller 4.
Assume that the secondary transport output port LAN4 of the first image time synchronization controller 4 fails: the port of the switch 3 and the secondary transmission output port LAN4 of the first image time synchronization controller 4 are interrupted in transmission, the switch 3 feeds back the state of the port to the upper computer 7, the upper computer 7 locates that the secondary transmission output port LAN4 of the first image time synchronization controller 4 is faulty, and the fault transmission interface is automatically skipped through the Vlan function of the switch 3 and transmitted to the next transmission interface, that is, the switch 3 transmits the image signal to the primary transmission LAN input port 2 of the second image time synchronization controller 4.
Assume that the primary transmission input port LAN2 of the second image time synchronization controller 4 fails: the port of the switch 3 and the primary transmission input port LAN2 of the second image time synchronization controller 4 are interrupted in transmission, the switch 3 feeds back the state of the port to the host computer 7, the host computer 7 locates that the primary transmission input port LAN2 of the second image time synchronization controller 4 is faulty, and automatically skips the faulty transmission interface through the Vlan function of the switch 3, skips the primary transmission output port LAN1 at the same level as the primary transmission input port LAN2, and transmits the faulty transmission interface to the next transmission interface, that is, the switch 3 transmits the image signal to the secondary transmission input port LAN3 of the second image time synchronization controller 4.
Assume that the primary transport output port LAN1 of the second image time synchronization controller 4 fails: the port of the switch 3 and the primary transmission output port LAN1 of the second image time synchronization controller 4 are interrupted, the switch 3 feeds back the port status to the upper computer 7, and the upper computer 7 locates that the primary transmission output port LAN1 of the second image time synchronization controller 4 is faulty, and through the Vlan function of the switch 3, the faulty transmission interface is automatically skipped and the image signal is transmitted to the next transmission interface, that is, the switch 3 transmits the image signal to the secondary transmission LAN input port 3 of the second image time synchronization controller 4.
And so on.
The image time synchronization controller 4 is also provided with a plurality of 485 interfaces, and the 485 interfaces are also required to be tested. Specifically, the upper computer 7 sends signals to the plurality of 485 interfaces of each image time synchronization controller 4 respectively, each 485 interface receives the signals and then feeds the signals back to the processor, and the processor feeds the signals back to the upper computer 7, so that the upper computer 7 receives each 485 interface of each image time synchronization controller 4, and after a closed loop is formed, the working state of the 485 interfaces of the image time synchronization controllers 4 is detected through the upper computer 7.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. The image time synchronization controller testing tool is characterized by being used for testing a plurality of image time synchronization controllers, wherein a processor, a primary transmission input port, a primary transmission output port, a secondary transmission input port and a secondary transmission output port are arranged in each image time synchronization controller, and the primary transmission input port, the primary transmission output port, the secondary transmission input port and the secondary transmission output port are respectively and electrically connected with the processor;
the image time synchronization controller testing tool comprises a power supply, an image collector, a switch, an upper computer and a high and low temperature testing box, wherein the power supply is electrically connected with the plurality of image time synchronization controllers respectively and used for supplying power to the plurality of image time synchronization controllers respectively; the plurality of image time synchronization controllers are positioned in the high and low temperature test box;
the image collector is electrically connected with a primary transmission input port of a first image time synchronization controller and used for sending image signals to the first image time synchronization controller, and the first image time synchronization controller receives the image signals through the primary transmission input port and feeds the image signals back to the switch through the processor and the primary transmission output port in sequence;
the switch is provided with a plurality of ports, a first primary transmission output port of the image time synchronization controller, a first secondary transmission input port of the image time synchronization controller, a first secondary transmission output port of the image time synchronization controller are respectively and electrically connected with the ports of the switch in a one-to-one correspondence manner, a plurality of subsequent primary transmission input ports of the image time synchronization controller, a plurality of primary transmission output ports of the image time synchronization controller, a plurality of secondary transmission input ports of the image time synchronization controller and a plurality of secondary transmission output ports of the image time synchronization controller are also electrically connected with the ports of the switch in a one-to-one correspondence manner, and image signals sent by the image collector sequentially pass through the primary transmission input port of the image time synchronization controller, the processor of the first image time synchronization controller, A first-level transmission output port of the first image time synchronization controller, the switch, a second-level transmission input port of the first image time synchronization controller, a processor of the first image time synchronization controller, and a second-level transmission output port of the first image time synchronization controller are fed back to the switch, according to the transmission mode of the image signals, the exchanger transmits the image signals back to the exchanger through a primary transmission input port of a plurality of subsequent image time synchronization controllers, a processor of the plurality of image time synchronization controllers, a primary transmission output port of the plurality of image time synchronization controllers, a secondary transmission input port of the plurality of image time synchronization controllers, a processor of the plurality of image time synchronization controllers and a secondary transmission output port of the plurality of image time synchronization controllers in sequence;
the upper computer is electrically connected with the switch and receives image signals fed back after sequentially passing through the plurality of image time synchronization controllers through the switch; and the upper computer also receives a plurality of working states of a plurality of ports corresponding to the image time synchronization controller, which are monitored and sent by the switch.
2. The image time synchronization controller testing tool according to claim 1, wherein a plurality of 485 interfaces are further arranged on the image time synchronization controller, the upper computer is electrically connected with the processor and the plurality of 485 interfaces respectively, the plurality of 485 interfaces are electrically connected with the processor respectively, the upper computer sends signals to the plurality of 485 interfaces respectively, the plurality of 485 interfaces feed the signals back to the processor respectively, and the processor feeds the plurality of signals back to the upper computer.
3. The image time synchronization controller testing tool according to claim 2, wherein a conversion interface is arranged between the upper computer and the plurality of 485 interfaces.
4. The image time synchronization controller testing tool according to claim 2 or 3, wherein the upper computer is electrically connected with the plurality of 485 interfaces through twisted pairs.
5. The image time synchronization controller test tool of claim 1, wherein the switch is a three-layer network management switch.
6. The image time synchronization controller testing tool according to claim 1, further comprising a display and a keyboard and mouse, wherein the display and the keyboard and mouse are electrically connected with the upper computer respectively, the display is used for displaying information derived by the upper computer, and the keyboard and mouse are used for operating the upper computer.
7. An image time synchronization controller testing method is characterized in that the image time synchronization controller testing tool according to any one of claims 1 to 6 is applied to test a plurality of image time synchronization controllers, and the method comprises the following steps:
the exchanger sequentially sends and receives image signals to each image time synchronization controller according to the working state of each transmission interface of each image time synchronization controller; the switch feeds back the state of each port to the upper computer;
the exchanger feeds back image signals fed back after sequentially passing through the plurality of image time synchronization controllers to the upper computer.
8. The image time synchronization controller testing method according to claim 7, wherein the switch sequentially transmits and receives image signals to and from each of the image time synchronization controllers according to an operating state of each transmission interface of each image time synchronization controller; the switch feeds back the state of each port to the upper computer and comprises:
when the port of the switch is interrupted with the image signal transmission of the transmission interface of the image time synchronization controller, the switch feeds back the state of the port to the upper computer, and the switch transmits the image signal to the next transmission interface.
9. The image time synchronization controller testing method of claim 7, further comprising:
the upper computer respectively sends signals to a plurality of 485 interfaces of each image time synchronization controller;
and receiving signals fed back by the processors through a plurality of 485 interfaces of each image time synchronization controller.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000224568A (en) * | 1999-02-02 | 2000-08-11 | Matsushita Electric Ind Co Ltd | Monitoring system |
| CN102879278A (en) * | 2012-09-14 | 2013-01-16 | 清华大学 | High-low temperature dynamic cold-hot circulation thermodynamic test system |
| CN103188506A (en) * | 2011-12-28 | 2013-07-03 | 三星电子株式会社 | Display apparatus, image processing system, display method and imaging processing thereof |
| CN104616627A (en) * | 2013-11-01 | 2015-05-13 | 联咏科技股份有限公司 | Display driving device and display driving method |
| CN104836573A (en) * | 2015-04-30 | 2015-08-12 | 北京空间机电研究所 | Synchronized clock system for ultra-large area array CMOS camera multipath high-speed signals |
| CN104952421A (en) * | 2015-07-13 | 2015-09-30 | 武汉精测电子技术股份有限公司 | Method and system for generating MIPI (mobile industry processor interface) signals for MIPI module detection |
| WO2016031181A1 (en) * | 2014-08-29 | 2016-03-03 | Canon Kabushiki Kaisha | Inspection apparatus and inspection method for detecting foreign substances using terahertz radiation |
| CN105516542A (en) * | 2014-09-26 | 2016-04-20 | 北京同步科技有限公司 | Multichannel video synchronization system based on hardware encoders and synchronization method thereof |
| CN109249899A (en) * | 2018-09-29 | 2019-01-22 | 长春理工大学 | A kind of automotive electronics anti-theft monitoring device and method based on MOST bus |
-
2020
- 2020-08-03 CN CN202010764912.1A patent/CN111736576B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000224568A (en) * | 1999-02-02 | 2000-08-11 | Matsushita Electric Ind Co Ltd | Monitoring system |
| CN103188506A (en) * | 2011-12-28 | 2013-07-03 | 三星电子株式会社 | Display apparatus, image processing system, display method and imaging processing thereof |
| CN102879278A (en) * | 2012-09-14 | 2013-01-16 | 清华大学 | High-low temperature dynamic cold-hot circulation thermodynamic test system |
| CN104616627A (en) * | 2013-11-01 | 2015-05-13 | 联咏科技股份有限公司 | Display driving device and display driving method |
| WO2016031181A1 (en) * | 2014-08-29 | 2016-03-03 | Canon Kabushiki Kaisha | Inspection apparatus and inspection method for detecting foreign substances using terahertz radiation |
| CN105516542A (en) * | 2014-09-26 | 2016-04-20 | 北京同步科技有限公司 | Multichannel video synchronization system based on hardware encoders and synchronization method thereof |
| CN104836573A (en) * | 2015-04-30 | 2015-08-12 | 北京空间机电研究所 | Synchronized clock system for ultra-large area array CMOS camera multipath high-speed signals |
| CN104952421A (en) * | 2015-07-13 | 2015-09-30 | 武汉精测电子技术股份有限公司 | Method and system for generating MIPI (mobile industry processor interface) signals for MIPI module detection |
| CN109249899A (en) * | 2018-09-29 | 2019-01-22 | 长春理工大学 | A kind of automotive electronics anti-theft monitoring device and method based on MOST bus |
Non-Patent Citations (2)
| Title |
|---|
| 徐磊 等: "基于FPGA的遥感高速图像数传系统设计", 《电子测量技术》 * |
| 王翼 等: "基于OPENMV与nRF24L01的远程同步图像采集系统设计", 《电子测量技术》 * |
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