CN104952421A - Method and system for generating MIPI (mobile industry processor interface) signals for MIPI module detection - Google Patents
Method and system for generating MIPI (mobile industry processor interface) signals for MIPI module detection Download PDFInfo
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Abstract
The invention discloses a method and a system for generating MIPI (mobile industry processor interface) signals for MIPI module detection. RGB image data are acquired through link video signals and then MIPI signals are acquired through the RGB image data. To be specific, the method comprises steps as follows: before the RGB signals are converted into the MIPI signals, the RGB image data converted from the video signals are cached; a local RGB image pixel clock is acquired according to required image timing sequence parameters displayed by an MIPI module; a stable local image timing sequence is generated under the control of the RGB image pixel clock according to the image timing sequence parameters, and image synchronization signals meeting the MIPI module detection requirement are generated; under the control of the image synchronization signals, MIPI conversion is performed on the cached RGB image data, and the MIPI signals meeting the MIPI module detection requirement are acquired. The system for generating MIPI signals for MIPI module detection can be realized on one FPGA (field programmable gate array) chip and has the characteristics of easiness in implementation, lower cost, convenience in operation, work stability, high reliability and the like.
Description
Technical field
The invention belongs to signal processing technology field, more specifically, relate to the method and system of the MIPI signal that a kind of generation detects for MIPI module.
Background technology
Mobile Industry Processor Interface (Mobile Industry Processor Interface, MIPI) display technique and MIPI liquid crystal display module have been used in various portable mobile product widely; In the research and development and production run of MIPI liquid crystal display module, need to carry out multinomial test to the MIPI liquid crystal display module of output.
In prior art, use more independently image signal source to produce the original test image of different resolution, and be connected to MIPI conversion equipment through cable, by low-voltage differential signal (Low-Voltage Differential Signaling, LVDS) signal converts MIPI signal to, to test the module of different qualities; Because image signal source is of low quality, precision and degree of stability poor, and production environment electromagnetic interference (EMI) is comparatively large, and connection cable is longer causes signal distortion and decay, make the MIPI jitter produced through conversion, the picture of module displays has the problems such as flicker, skew, snow or bright line; Because the MIPI signal source for testing is unstable, therefore, when the picture of MIPI liquid crystal display module display occurs abnormal, the exception caused because signal source is abnormal cannot be judged, or due to the exception that the fault of MIPI liquid crystal display module causes, cause the test accuracy of MIPI liquid crystal display module not high.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides the method and system of the MIPI signal that a kind of generation detects for MIPI module, its object is to the time sequence information at this locality regeneration MIPI module, data according to receiving regenerate rgb video signal in this locality, and carry out MIPI conversion, form stable MIPI signal, solve prior art point MIPI screen unstable, the problem of display flicker, bright line, snow.
For achieving the above object, according to one aspect of the present invention, provide the method for the MIPI signal that a kind of generation detects for MIPI module, comprise the following steps:
(1) recovery shaping is carried out to vision signal, to adjust its transmission electrical specification; This vision signal comprises link transmission clock and link serially-transmitted data;
(2) link transmission clock and link serially-transmitted data are calibrated, eliminate clock and the relative delay between data-signal, make transmission data and clock alignment;
According to transfer clock by the demodulation respectively of the LVDS signal of each link, carry out serioparallel exchange, serially-transmitted data operates through serioparallel exchange, is demodulated to parallel video data;
(3) transmit VESA (Video Electronics Standards Association) agreement, JEIDA (Japan Electronic Industry Development Association) agreement and 6bit, 8bit, 10bit color range according to LVDS to decode, each link signal is reduced into RGB image; And by the RGB image integration of each link together, form complete rgb image data, RGB synchronizing signal, rgb pixel clock;
(4) the image time sequence parameter needed for MIPI module displays, converts the MIPI image of whole screen form or the image of split screen form to by rgb signal,
(5) conversion of MIPI signal is carried out to the MIPI image of whole screen form or the image of split screen form, changed into the MIPI signal of different channels number.
It is put especially and is, before rgb signal converts MIPI signal to, by the rgb image data buffer memory received; Image time sequence parameter again needed for MIPI module displays obtains local RGB image pixel clock; Then, according to image time sequence parameter, under RGB image pixel clock, produce stable local image sequential, formed thus and meet MIPI module testing requirement
Picture synchronization signal; Under this picture synchronization signal controls, the rgb image data of buffer memory is carried out MIPI conversion, obtain the MIPI signal meeting MIPI module testing requirement;
Because RGB picture signal may be subject to the impacts such as the asynchronous and stability of image signal source of delay own is lower of external disturbance, transmission cable in transmitting procedure, there is shake, timing variations or postpone larger in the rgb image data causing local reception to be arrived; If by local reception to rgb image data be directly changed into MIPI signal and send into module, the problems such as film flicker, picture moving, fuzzy pictures may be there is in the image that module shows; And the rgb image data received is cached to local regeneration by the present invention, and then change, the shake of removal of images data and delay, realize sequential alignment, be provided for the MIPI signal quality that MIPI module detects;
Wherein, image time sequence parameter comprises: row crop, row back porch, row effectively, row pulsewidth, frame crop, frame back porch, frame effectively, frame pulsewidth and display brush frequently;
Wherein, RGB image pixel clock is local clock, has clock frequency and stablizes, reliably and not by the advantage of external disturbance.
Preferably, when rgb image data starts buffer memory, judge whether current RGB picture frame is complete frame according to local image sequential, if so, then by current RGB picture frame from the first row first data stored in buffer memory; If not, then abandon current RGB picture frame, receive new RGB picture frame; By described new RGB picture frame from the first row first data stored in buffer memory;
And whether have data stored in buffer memory when each RGB picture frame starts according to local image time-series rules, when have data stored in time, the rgb image data starting to take out in buffer memory when the first row first pixel sequential of RGB picture frame arrives; Due to synchronous with sense data stored in data, the rgb image data exported is made to be the view data of stable localization.
Preferably, to the method that link transmission clock, link serially-transmitted data are calibrated in above-mentioned steps (2), specific as follows: to adopt the clock of 4 ~ 8 times of frequency domain signal transfer rates to carry out the edge transition of data detection signal and clock signal, obtain the time delay of data-signal and clock signal, and according to time delay, reverse time delay adjustment is done to data-signal and clock signal, synchronous each other to make between clock and each data-signal;
Then obtain first bit of parallel byte, with transfer clock and the data of aliging, according to transfer clock, serially-transmitted data is operated through serioparallel exchange, be demodulated to parallel data;
Wherein, reverse time delay adjustment is by controlling High Speed I/O Delay Element, and the time delay of the signal of adjustment clock and each link makes between clock and each data-signal synchronous; Reverse time delay adjustment action, solve because of vision signal transmitting procedure due to length of cable, material, transport property volume difference and cause the clock received, relative delay between each data-signal.
Preferably, the rgb signal produced in this locality according to MIPI signal transfer rate, carries out the operation of frequency division frequency multiplication to RGB image pixel clock, obtains synchronous MIPI change over clock before converting the conversion of MIPI signal to, and MIPI conversion is carried out according to above-mentioned MIPI change over clock;
Wherein, MIPI change over clock comprises the byte group packet clock of MIPI operation and exports the string signal clock of MIPI.
Preferably, after the step of rgb signal conversion MIPI signal, also comprise the step that the MIPI signal got is calibrated;
MIPI signal comprises MIPI clock signal and each channel MIPI data-signal of stringization; Calibrating the phase place between MIPI clock signal and each Channel Data Signal, making MIPI signal when outputting to the web member of MIPI module, the center alignment of clock and each Channel Data Signal, meets MIPI DPHY agreement; Thus ensure that the MIPI signal that MIPI module receives is stablized errorless; The display bright line avoiding not aliging and cause because of the clock of MIPI signal source, data, dodge the problems such as line; Wherein, MIPI DPHY agreement is one of MIPI agreement, and D-PHY provides DSI (series display interface) and CSI (serial utilizing camera interface) definition on a physical layer.
Preferably, between MIPI signal output part and MIPI module receiving end, mutual time delay between the clock signal of the MIPI signal adopting the adjustment of controlled time delay assembly to export and data-signal, make the edge of MIPI clock signal in the centre of data-signal transmission UI, between each MIPI data-signal, keep Complete Synchronization.
Preferably, after the step of rgb signal conversion MIPI signal, in the transmitting procedure of MIPI Signal transmissions to MIPI module, also comprise compensation of delay and signal fine setting;
Concrete, compensation of delay is the circuit of first original circuit by the non-time delay of comparison and time delay, obtain relative time delay value, adopt Reverse Turning Control time delay assembly according to the circuit of described relative time delay value compensation delay, the delay time error that adaptive adjustment causes because of working temperature, environmental change;
Signal finely tunes high speed (the high speed comprised MIPI signal, HS) state and low-power consumption (low power, LP) electrical specification of state is arranged, comprise level magnitude, drive intensity, pre-emphasis, rising edge negative edge, differential signal zero value adjusts, the clock of the MIPI signal that MIPI module is received and data-signal Complete Synchronization.
For realizing object of the present invention, according to another aspect of the present invention, provide the system of the MIPI signal that a kind of generation detects for MIPI module, comprise MIPI control module, video data cache module, local RGB generation module, local video clock generating module, local RGB synchronizing signal generation module and MIPI modular converter;
Wherein, the input end of MIPI control module as the control signal interface of described system, for receiving exterior arrangement; The input end of video data cache module is for receiving the rgb image data converted to through LVDS signal;
Wherein, the first input end of local RGB generation module connects the output terminal of described video data cache module; Second input end connects the output terminal of described local RGB synchronizing signal generation module; 3rd input end connects the first output terminal of described local video clock generating module, receives RGB image clock;
Wherein, the first input end of local video clock generating module connects the 4th output terminal of described MIPI control module, receives MIPI changeover control signal; Second input end connects the 3rd output terminal of MIPI control module, receives MIPI module image sequential;
Wherein, the first input end of local RGB synchronizing signal generation module also connects the 3rd output terminal of MIPI control module, receives MIPI module image sequential; Second input end also connects the first output terminal of local video clock generating module, receives RGB image clock;
Wherein, the first input end of MIPI modular converter connects the output terminal of local RGB generation module, receives the local rgb signal regenerated after buffer memory; Second input end connects the second output terminal of local video clock generating module, receives MIPI change over clock; 3rd input end connects the 4th output terminal of MIPI control module, receives MIPI changeover control signal;
Wherein, video data cache module is used for the rgb image data that buffer memory receives; Local video clock generating module is used for according to configuration synthetic image pixel clock; Image pixel clock is the local clock produced in local video clock generating module, and clock frequency surely, is not subject to external disturbance;
Wherein, local RGB synchronizing signal generation module is for generating local image sequential; Local RGB generation module according to the rgb image data of described local image sequential and video data cache module buffer memory, at this locality regeneration rgb signal; MIPI modular converter generates the MIPI signal meeting MIPI module displays demand according to local rgb signal.
Preferably, above-mentioned generation is used for the system of the MIPI signal that MIPI module detects, also comprise the converting unit of LVDS signal to rgb image data, the input end of this unit is as the LVDS interface of system, for connecting LVDS signal source, receive the transmit clock signal on each link and transmission of data signals; Output terminal as rgb image data delivery outlet, for connecting described video data cache module;
This unit for adjusting LVDS Signal transmissions electrical specification, and is calibrated the clock of LVDS signal and data, and by the demodulation respectively of the LVDS signal of each link, carries out serioparallel exchange, convert rgb image data to after being demodulated to parallel data.
Preferably, above-mentioned generation is used for the system of the MIPI signal that MIPI module detects, and its LVDS signal comprises video input module, transmission demodulation module, transfer clock data calibration module and video conversion module to rgb image data converting unit;
Wherein, the first input end of video input module as the clock interface of system, for receiving the transmit clock signal on each link, the second input end as the data-interface of system, for receiving the transmission of data signals on each link; 3rd input end connects the first output terminal of MIPI control module, receiver, video input control signal;
Wherein, the first input end of transmission demodulation module connects the first output terminal of video input module, receiver transfer clock; Second input end connects the second output terminal of video input module, receiver transmission data; 3rd input end connects the output terminal of described transfer clock data calibration module; First output terminal connects the input end of transfer clock data calibration module;
Wherein, the first input end of video conversion module connects the second output terminal of transmission demodulation module, receives image clock; Second input end connects the 3rd output terminal of transmission demodulation module, receives view data; 3rd input end connects the second output terminal of MIPI control module, receiver, video changeover control signal; Output terminal is as the delivery outlet of LVDS signal to rgb image data converting unit;
Wherein, video input module carries out recovery shaping to the LVDS signal received, and adjusts its transmission electrical specification; By described transfer clock data calibration module, link transmission clock and link serially-transmitted data are calibrated, eliminate clock and the relative delay between data-signal, make transmission data and clock alignment; Described transmission demodulation module by the demodulation respectively of the LVDS signal of each link according to transfer clock, carries out serioparallel exchange, is demodulated to parallel data; Described video conversion module, according to described parallel data, obtains rgb image data.
Preferably, above-mentioned generation is used for the system of the MIPI signal that MIPI module detects, and also comprises MIPI clock data calibration module and MIPI output module;
Wherein, the first input end of MIPI clock data calibration module connects the first output terminal stating MIPI modular converter, receives MIPI clock signal; Second input end connects the second output terminal of MIPI modular converter, receives MIPI data-signal; 3rd input end connects the 5th output terminal of MIPI control module, receives MIPI transmission delay adjustment signal;
Wherein, the first input end of MIPI output module connects the first output terminal of MIPI clock data calibration module, receives MIPI output clock; Second input end connects the second output terminal of MIPI clock data calibration module, receives MIPI and exports data; 3rd input end connects the 6th output terminal of MIPI control module, receives MIPI and exports control signal; The output terminal of described MIPI output module, as the output interface of system, for connecting MIPI module to be measured;
MIPI clock data calibration module, for calibrating the phase place between MIPI clock and each Channel Data Signal, makes to ensure when outputting to web member that clock and each data-signal can accomplish the center alignment of clock and each Channel Data Signal according to MIPI DPHY agreement; The MIPI signal of MIPI output module then for exporting MIPI clock data calibration module carries out the adjustment of electrical specification, transport property and impedance operator, and the MIPI signal received to make module termination has optimum signal quality.
Said system all can adopt fpga chip to realize, and has easy realization, cost is low, work stability and reliability is high, easy and simple to handle feature.
In general, the above technical scheme conceived by the present invention compared with prior art, can obtain following beneficial effect:
(1) because picture signal may be subject to the reasons such as the asynchronous and stability of image signal source of delay own is lower of external disturbance, transmission cable in transmitting procedure, the view data shake or the image timing variations that receive can be caused or postpone larger; By the method regenerated after first cache image signal source provided by the invention, avoid when being directly changed into MIPI signal by the image signal source received and being sent into module displays, display image occurs that film flicker, picture moving, fuzzy pictures etc. can not stablize the problem of display;
(2) MIPI signal creating method provided by the invention and system, carries out input adjustment and calibration to link video transfer signal, makes data receiver correct, avoids demodulation mistake;
(3) MIPI signal creating method provided by the invention and system, by the time sequence information regenerating MIPI module in this locality, again converts the link video data of input to reliable and stable rgb video signal, and then carries out MIPI conversion; Make to export MIPI signaling point screen stable, non-jitter, flicker free, without snow.
(4) MIPI signal creating method provided by the invention and system, after MIPI converts, adjustment exports time delay, the electrical specification of MIPI signal, guarantees the transmitting of MIPI signal.
Accompanying drawing explanation
Fig. 1 is the block diagram of the system of the MIPI signal that a kind of generation provided by embodiment 1 detects for MIPI module;
Fig. 2 is the process flow diagram of the method for the MIPI signal that generation provided by the invention detects for MIPI module;
In all of the figs, identical Reference numeral is used for representing identical element or structure:
1-MIPI control module, 2-video input module, 3-transmit demodulation module, 4-transfer clock data calibration module, 5-video conversion module, 6-video data cache module, the local RGB generation module of 7-, 8-local video clock generating module, 9-local RGB synchronizing signal generation module, 10-MIPI modular converter, 11-MIPI clock data calibration module, 12-MIPI output module.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each embodiment of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
As shown in Figure 1, the system of the MIPI signal that a kind of generation that embodiment 1 provides detects for MIPI module, comprises MIPI control module 1, video input module 2, transmission demodulation module 3, transfer clock data calibration module 4, video conversion module 5, video data cache module 6, local RGB generation module 7, local video clock generating module 8, local RGB synchronizing signal generation module 9, MIPI modular converter 10, MIPI clock data calibration module 11 and MIPI output module 12;
Wherein, video input module 2, transmission demodulation module 3, video conversion module 5, video data cache module 6, local RGB generation module 7, MIPI modular converter 10, MIPI clock data calibration module 11 and MIPI output module 12 are connected successively;
And transmit demodulation module 3 and also connect transfer clock data calibration module 4; Video input module, video conversion module 5, local video clock generating module 9, local RGB synchronizing signal generation module 8, MIPI modular converter 10, MIPI clock data calibration module 11 are all connected with MIPI control module 1 with MIPI output module 12, and each module receives all kinds of control signals from MIPI control module 1 respectively;
And local RGB generation module 7 is also connected with local RGB synchronizing signal generation module 9; Local RGB synchronizing signal generation module 9 is also connected with local video clock generating module 8 with MIPI modular converter 19.
Shown in Fig. 2, it is the process flow diagram of the method for the MIPI signal that generation that embodiment 1 provides detects for MIPI module; The converting system of the MIPI signal that a kind of generation provided below in conjunction with embodiment 1 detects for MIPI module, concrete elaboration provided by the inventionly a kind ofly produces the process being used for the MIPI signal that MIPI module detects:
(1) according to MIPI module displays parameter requirements configuration video input controling parameters, transmission termination matching properties, transmission termination equalization characteristic, signal transmission decision level, signal transmission benchmark, Video Quality Metric parameter, MIPI module displays image sequential, MIPI conversion parameter and MIPI output parameter is comprised;
Wherein, Video Quality Metric parameter comprises Propagation solution coding mode, view data bit wide, chain way; MIPI module displays image sequential comprises row, the pulsewidth of field, crop, back porch and effective value; MIPI conversion parameter comprises MIPI transmission time sequence, MIPI transfer rate, the MIPI number of channel and MIPI mode of operation; MIPI output parameter comprises output pre-emphasis, output voltage values, output driving intensity and exports termination impedance;
(2) by MIPI control module 1, above-mentioned parameter is configured to each module: video input controling parameters is configured to video input module 2, Video Quality Metric parameter configuration is to video conversion module 5, MIPI module displays image sequential is configured to local RGB synchronizing signal generation module 9 and local video clock generating module 8, MIPI conversion parameter is configured to local video clock generating module 8 and MIPI modular converter 10, MIPI output parameter is configured to MIPI output module 12; Startup video input module 2 receives the video transfer signal from image signal source;
(3) video input module 2 is according to the configuration of MIPI control module 1, the characteristic of input transmission termination matching, input uniform, signal transmission decision level is adjusted, video transfer signal is received, avoid vision signal to be subject to when transmitting distortion that extraneous electromagnetic interference (EMI) and vision signal cause via cable long-distance transmissions and decay with accurate, stable;
According to the signal transmission benchmark that MIPI control module 1 configures, carry out to the received signal recovering and shaping, to reach best transmission electrical specification, make subsequent module can receive data, electrically all correctly stable signal;
(4) transmit demodulation module 3 link transmission clock, link serially-transmitted data are sent into transfer clock data calibration module 4 and calibrated; Vision signal is when transmitting, and because of the difference of each length of cable, material, transport property, causing receiving between clock, each data-signal all has relative delay, calibrates to eliminate this delay; The time delayed difference value of each signal by the edge of 4 ~ 8 times of frequency domain each signals of detection clock comparison of transfer clock, and is fed back to transmission demodulation module 3 by transfer clock data calibration module 4; Transmission demodulation module 3 does reverse time delay adjustment according to time delayed difference value to each signal, makes it keep synchronous input;
Transfer clock data calibration module 4 controls transfer demodulation module 3 aligns transfer clock and data, namely the bit0 of parallel byte is found out, transmit demodulation module 3 afterwards according to transfer clock, serially-transmitted data to be operated through serioparallel exchange again, export to be demodulated to parallel data;
Transfer clock data calibration module 4 has the function of monitoring in real time, once monitor delay or serioparallel exchange deviation, then controls transfer demodulation module 3 readjusts demodulation operation, to make all reliably to produce data under various circumstances; The drift that transmission line postpones and inside modules circuit devcie occurs can be caused with the interference or high/low temperature change that compensate the external world;
(5) video conversion module 5 converts the data of input to rgb image data according to the Video Quality Metric parameter that MIPI control module 1 configures and sends into video data cache module 6;
(6) view data is cached in video data cache module 6, then generates the image sequential needed for MIPI module displays according to the configuration of MIPI control module 1, comprise row crop, row back porch, capable effective, row pulsewidth; Frame crop, frame back porch, frame effectively, frame pulsewidth and display brush frequently; The image time sequence information of module 8 needed for the MIPI module displays received from MIPI control module 1 obtains image pixel clock frequency, and produces image pixel clock and send into local RGB synchronizing signal generation module 9 and local RGB generation module 7; Because image pixel clock is the local clock produced in local video clock generating module 8, thus have clock frequency can stablize, reliable, unchanged, be not subject to the advantage of external disturbance;
Because picture signal may be subject to the reason such as the asynchronous and stability of image signal source of delay own is lower of external disturbance, transmission cable in transmitting procedure, the view data shake that can cause receiving or image timing variations or postpone larger, if when being directly changed into MIPI signal like this and sending into module displays, then show image and there will be the problem that film flicker, picture moving, fuzzy pictures etc. can not stablize display; This step is slowly deposited view data and is regenerated, be then to obtain stable MIPI signal;
(7) local RGB synchronizing signal generation module 9 is according to image time sequence parameter, and RGB image pixel clock, produce stable local image sequential, thus form the new picture synchronization signal meeting MIPI display requirement, comprise field sync signal VSYNC, line synchronizing signal HSYNC and valid data gating signal DE; And above-mentioned picture synchronization signal is sent into module 7; The view data that institute's buffer memory is come in is coupled to this synchronizing signal and outputs to module MIPI modular converter 10 together and carry out MIPI conversion by module 7 under above-mentioned picture synchronization signal controls, and what it is such that view data can be reliable and stable meets the requirement of MIPI module displays;
(8) the MIPI signal transfer rate that upper strata configures by MIPI control module 1 sends into local video clock generating module 8, module 8 pairs of image pixel clocks carry out through frequency division and frequency multiplication, produce synchronous MIPI change over clock and send into MIPI modular converter 10 to carry out MIPI conversion operations; In MIPI modular converter 10 transfer process, MIPI control module 1 carries out MIPI sequential, transmission, group bag, data channel assignment manipulation by MIPI changeover control signal to it;
Wherein, MIPI change over clock comprises the byte group packet clock of MIPI operation and exports the string signal clock of MIPI;
(9) the MIPI signal after conversion is given MIPI clock data calibration module 11 by MIPI modular converter 10; Phase place between module 11 calibration MIPI clock and each Channel Data Signal, making to ensure when outputting to web member that clock and each data-signal can accomplish the center alignment of clock and each Channel Data Signal according to MIPI DPHY agreement, receiving correct data display to make MIPI module; Avoid the problem such as display bright line, sudden strain of a muscle line caused because clock, data are not alignd; Wherein, the MIPI signal after conversion comprises MIPI clock signal and each MIPI data channel signal of stringization;
In transmitting procedure, MIPI modular converter 10 1 aspect automatically adjusts and compensates because of working temperature, environmental change and the delay time error that causes; On the other hand, according to the transport property of connection cable, produce transmission delay signal by MIPI control module 1 and module MIPI clock data calibration module 11 is finely tuned, thus guarantee the complete matching at module end MIPI signal;
(10) MIPI output module 12 carries out the adjustment of electrical specification, transport property and impedance operator by the output control signal of MIPI control module 1 to the MIPI signal from MIPI clock data calibration module 11, the MIPI signal received to make module termination has optimum signal quality, then outputs to MIPI module to be measured.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. generate the method being used for the MIPI signal that MIPI module detects, obtain rgb image data by link vision signal, obtain MIPI signal according to rgb image data;
It is characterized in that, before obtaining MIPI signal by rgb image data, by the rgb image data buffer memory converted to by link vision signal; And the image time sequence parameter needed for MIPI module displays obtains local RGB image pixel clock;
According to described image time sequence parameter, under RGB image pixel clock, produce local image sequential, form the picture synchronization signal meeting MIPI module testing requirement; Under described picture synchronization signal controls, the rgb image data of buffer memory is carried out MIPI conversion, obtain the MIPI signal meeting MIPI module testing requirement.
2. the method for claim 1, it is characterized in that, when rgb image data starts buffer memory, judge whether current RGB picture frame is complete frame according to local image sequential, if so, then by current RGB picture frame from the first row first data stored in buffer memory; If not, then abandon current RGB picture frame, receive new RGB picture frame; By described new RGB picture frame from the first row first data stored in buffer memory;
And whether have data stored in buffer memory when each RGB picture frame starts according to local image time-series rules, when have data stored in time, the rgb image data starting to take out in buffer memory when the first row first pixel sequential of RGB picture frame arrives; Due to synchronous with sense data stored in data, the rgb image data exported is made to be the view data of stable localization.
3. method as claimed in claim 1 or 2, is characterized in that, before link vision signal converts rgb image data to, first calibrates the link transmission clock of link vision signal, link serially-transmitted data, specific as follows:
(1) clock of 4 ~ 8 times of frequency domain signal transfer rates is adopted to carry out the edge transition of data detection signal and clock signal, obtain the time delay of data-signal and clock signal, and according to described time delay, reverse time delay adjustment is done to data-signal and clock signal, to make to keep synchronous between clock and each data-signal;
(2) first bit of parallel byte is obtained, with transfer clock and the data of aliging;
(3) according to transfer clock, serially-transmitted data is operated through serioparallel exchange, be demodulated to parallel data; Described reverse time delay adjustment eliminates the relative delay of link vision signal in transmitting procedure.
4. method as claimed in claim 1 or 2, is characterized in that, according to MIPI signal transfer rate, carry out frequency division process of frequency multiplication, obtain synchronous MIPI change over clock to local RGB image pixel clock; The transfer process obtaining MIPI signal by rgb image data with described MIPI change over clock for reference clock.
5. the method as described in any one of Claims 1-4, is characterized in that, after converting rgb signal to MIPI signal, also comprises the step of calibrating the MIPI signal got, is specially:
Calibrate the phase place between MIPI clock signal and each channel MIPI data-signal, the clock of the MIPI signal that MIPI module is received and the center alignment of each Channel Data Signal, mate with MIPI DPHY agreement.
6. method as claimed in claim 5, it is characterized in that, between MIPI signal output part and MIPI module receiving end, mutual time delay between the clock signal of the MIPI signal adopting the adjustment of controlled time delay assembly to export and data-signal, make the edge of MIPI clock signal in the centre of data-signal transmission UI, between each MIPI data-signal, keep Complete Synchronization.
7. method as claimed in claim 6, it is characterized in that, in MIPI signals transmission, by the first original circuit of the non-time delay of comparison and the circuit of time delay, obtain relative time delay value, adopt Reverse Turning Control time delay assembly according to the circuit of described relative time delay value compensation delay, adaptive adjustment is because of working temperature, environmental change and the delay time error that causes.
8. one kind generates the system being used for the MIPI signal that MIPI module detects, it is characterized in that, comprise MIPI control module, video data cache module, local RGB generation module, local video clock generating module, local RGB synchronizing signal generation module and MIPI modular converter;
The input end of described MIPI control module as the control signal interface of described system, for receiving exterior arrangement; The input end of described video data cache module is for receiving the rgb image data converted to through LVDS signal;
The first input end of described local RGB generation module connects the output terminal of described video data cache module; Second input end connects the output terminal of described local RGB synchronizing signal generation module; 3rd input end connects the first output terminal of described local video clock generating module, receives RGB image clock;
The first input end of described local video clock generating module connects the 4th output terminal of described MIPI control module, receives MIPI changeover control signal; Second input end connects the 3rd output terminal of MIPI control module, receives MIPI module image sequential;
The first input end of described local RGB synchronizing signal generation module also connects the 3rd output terminal of MIPI control module, receives MIPI module image sequential; Second input end also connects the first output terminal of local video clock generating module, receives RGB image clock;
The first input end of described MIPI modular converter connects the output terminal of local RGB generation module, receives the local rgb signal regenerated after buffer memory; Second input end connects the second output terminal of described local video clock generating module, receives MIPI change over clock; 3rd input end connects the 4th output terminal of MIPI control module, receives MIPI changeover control signal;
Described video data cache module is used for the rgb image data that buffer memory receives; Described local video clock generating module is used for according to configuration synthetic image pixel clock; Described image pixel clock is the local clock produced in local video clock generating module, and clock frequency surely, is not subject to external disturbance;
Described local RGB synchronizing signal generation module is for generating local image sequential; Described local RGB generation module according to the rgb image data of described local image sequential and video data cache module buffer memory, at this locality regeneration rgb signal; Described MIPI modular converter generates MIPI signal according to local rgb signal.
9. the system generating the MIPI signal being used for the detection of MIPI module as claimed in claim 8, it is characterized in that, also comprise the converting unit of LVDS signal to rgb image data, described LVDS signal to the input end of rgb image data converting unit as the LVDS interface of described system, for connecting LVDS signal source, receive the transmit clock signal on each link and transmission of data signals; Output terminal as rgb image data delivery outlet, for connecting described video data cache module;
Described LVDS signal is to the converting unit of rgb image data, for adjusting LVDS Signal transmissions electrical specification, and the clock of LVDS signal and data are calibrated, and by the demodulation respectively of the LVDS signal of each link, carry out serioparallel exchange, after being demodulated to parallel data, convert rgb image data to.
10. the system generating the MIPI signal being used for the detection of MIPI module as claimed in claim 9, it is characterized in that, described LVDS signal comprises video input module, transmission demodulation module, transfer clock data calibration module and video conversion module to the converting unit of rgb image data;
The first input end of described video input module as the clock interface of described system, for receiving the transmit clock signal on each link, the second input end as the data-interface of described system, for receiving the transmission of data signals on each link; 3rd input end connects the first output terminal of MIPI control module, receiver, video input control signal;
The first input end of described transmission demodulation module connects the first output terminal of video input module, receiver transfer clock; Second input end connects the second output terminal of video input module, receiver transmission data; 3rd input end connects the output terminal of described transfer clock data calibration module; First output terminal connects the input end of transfer clock data calibration module;
The first input end of described video conversion module connects the second output terminal of transmission demodulation module, receives image clock; Second input end connects the 3rd output terminal of transmission demodulation module, receives view data; 3rd input end connects the second output terminal of described MIPI control module, receiver, video changeover control signal; Output terminal is as the delivery outlet of LVDS signal to rgb image data converting unit;
Described video input module carries out recovery shaping to the LVDS signal received, and adjusts its transmission electrical specification; By described transfer clock data calibration module, link transmission clock and link serially-transmitted data are calibrated, eliminate clock and the relative delay between data-signal, make transmission data and clock alignment; Described transmission demodulation module by the demodulation respectively of the LVDS signal of each link according to transfer clock, carries out serioparallel exchange, is demodulated to parallel data; Described video conversion module, according to described parallel data, obtains rgb image data.
11. generations as described in any one of claim 8 to 10 are used for the system of the MIPI signal that MIPI module detects, and it is characterized in that, also comprise MIPI clock data calibration module and MIPI output module;
The first input end of described MIPI clock data calibration module connects the first output terminal of described MIPI modular converter, receives MIPI clock signal; Second input end connects the second output terminal of described MIPI modular converter, receives MIPI data-signal; 3rd input end connects the 5th output terminal of MIPI control module, receives MIPI transmission delay adjustment signal;
The first input end of described MIPI output module connects the first output terminal of described MIPI clock data calibration module, receives MIPI output clock; Second input end connects the second output terminal of described MIPI clock data calibration module, receives MIPI and exports data; 3rd input end connects the 6th output terminal of MIPI control module, receives MIPI and exports control signal; The output terminal of described MIPI output module, as the output interface of described system, for connecting MIPI module to be measured;
Described MIPI clock data calibration module, for calibrating the phase place between MIPI clock and each Channel Data Signal, makes to ensure when outputting to web member that clock and each data-signal can accomplish the center alignment of clock and each Channel Data Signal according to MIPI DPHY agreement;
The MIPI signal of described MIPI output module then for exporting MIPI clock data calibration module carries out the adjustment of electrical specification, transport property and impedance operator.
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