CN109286839B

CN109286839B - eDP interface driving method and FPGA main control chip

Info

Publication number: CN109286839B
Application number: CN201811150113.4A
Authority: CN
Inventors: 黄明军; 刘家家; 刘辉; 安亮; 陈靓
Original assignee: Sonoscape Medical Corp
Current assignee: Sonoscape Medical Corp
Priority date: 2018-09-29
Filing date: 2018-09-29
Publication date: 2021-04-16
Anticipated expiration: 2038-09-29
Also published as: CN109286839A

Abstract

The invention provides an eDP interface driving method and an FPGA main control chip, wherein the FPGA main control chip is connected with an eDP screen; an eDP interface driving module is integrated on the FPGA main control chip; the eDP interface driving module comprises an eDP configuration module and an eDP sending module; the method comprises the following steps: acquiring video source data and screen parameters of an eDP screen; configuring a DP ip core of the FPGA main control chip according to the screen parameters and the video source parameters by using an eDP configuration module; and driving the eDP screen by using the eDP sending module through the configured DP ip core. The eDP interface driving method has the advantages that the eDP interface is directly driven by the FPGA main control chip, so that the design is simple, the stability is higher, the universality is higher, the eDP interface driving performance is improved, and the requirements of eDP interface driving can be better met.

Description

eDP interface driving method and FPGA main control chip

Technical Field

The invention relates to the technical field of electronic information, in particular to an eDP interface driving method and an FPGA main control chip.

Background

With the development of scientific technology, the resolution of the display screen of the electronic device is higher and higher, so that the traditional low-voltage differential signaling LVDS interface is more and more difficult to meet the requirements thereof, and the embedded display interface eDP based on the DisplayPort architecture and the protocol is brought forward. eDP (Embedded display interface) is a fully digital interface based on a DisplayPORT architecture and protocol, and can use a simpler connector and fewer pins to transmit high-resolution signals, and can realize simultaneous transmission of multiple data, so that the transmission rate is much higher than that of an LVDS (Low Voltage differential signaling) interface.

The existing eDP interface driving scheme mainly includes two kinds: firstly, an eDP interface is directly driven through an X86 mainboard; and the other is to indirectly drive the eDP interface by means of a special eDP interface driving chip. However, the first solution is only applicable to products based on the X86 architecture, and the applicable scenario is fixed and single, and cannot well meet the eDP interface driving requirements of the non-X86 architecture; the quality of the special eDP interface driving chip adopted by the scheme two is poor, the design complexity of the eDP interface driven by the special eDP interface driving chip and the main control chip is high, and the stability of the eDP interface driving is difficult to guarantee. Therefore, the existing eDP interface driving scheme has poor universality or complex design and poor stability, and cannot well meet the requirements of eDP interface driving.

Therefore, an eDP interface driving scheme with simple design, stronger stability and higher universality is urgently needed.

Disclosure of Invention

In view of the above, the present invention provides an eDP interface driving method and apparatus, so as to solve the technical problem that the existing eDP interface driving scheme has poor universality or complex design and poor stability, and cannot well meet the requirements of the existing eDP interface driving.

In order to achieve the purpose, the invention provides the following technical scheme:

an eDP interface driving method is applied to an FPGA main control chip, and the FPGA main control chip is connected with an eDP screen; an eDP interface driving module is integrated on the FPGA main control chip; the eDP interface driving module includes: the eDP configuration module and the eDP sending module; the method comprises the following steps:

acquiring video source data and screen parameters of the eDP screen; the video source data comprises at least video source parameters;

configuring a display interface intellectual property core DP ip core of the FPGA main control chip by using the eDP configuration module according to the screen parameters and the video source parameters;

and driving the eDP screen by using the eDP sending module through the configured DP ip core.

Preferably, the screen parameter acquiring process includes:

performing initial training configuration on the DP ip core by using the eDP configuration module, and starting the initial training of the DP ip core;

and after the initial training of the DP ip core is completed, acquiring the screen parameters of the eDP screen by using the DP ip core.

Preferably, the configuring, by using the eDP configuration module, the display interface intellectual property core DP ip core of the FPGA main control chip according to the screen parameter and the video source parameter includes:

performing clock training configuration on the DP ip core by using the eDP configuration module according to the screen parameters, and starting clock training of the DP ip core;

utilizing the eDP configuration module to perform channel training configuration on the DP ip core according to the screen parameters after the clock training of the DP ip core is completed, and starting the channel training of the DP ip core;

and utilizing the eDP configuration module to perform video information configuration on the DP ip core according to the video source parameters after the channel training of the DP ip core is completed.

Preferably, a state monitoring module is further integrated on the FPGA main control chip; the state monitoring module is connected with an upper computer; the method further comprises the following steps:

acquiring real-time state information of the eDP interface driving module by using the state monitoring module;

and uploading the real-time state information of the eDP interface driving module to the upper computer by using the state monitoring module.

Preferably, a signal receiving module and a signal conversion module are further integrated on the FPGA main control chip; the video source data further comprises video data; the video data acquisition process comprises the following steps:

receiving LVDS video data by using the signal receiving module;

converting the LVDS video data into RGB data by using the signal conversion module;

and acquiring the RGB data by using the eDP interface driving module.

Preferably, a color temperature gamma correction module and a dithering algorithm module are further integrated on the FPGA main control chip; after the converting the LVDS video data into RGB data by the signal conversion module, the method further includes:

correcting the RGB data by using the color temperature gamma correction module to obtain corrected RGB data;

carrying out dithering processing on the corrected RGB data by using the dithering algorithm module to obtain processed RBG data;

correspondingly, the acquiring the RGB data by using the eDP interface driving module includes: and acquiring the processed RBG data by using the eDP interface driving module.

An FPGA main control chip is characterized in that the FPGA main control chip is connected with an eDP screen and is used for acquiring video source data and screen parameters of the eDP screen, wherein the video source data at least comprises video source parameters; the FPGA main control chip comprises: an eDP interface driving module;

the eDP interface driving module is integrated on the FPGA main control chip; the eDP interface driving module includes: the eDP configuration module and the eDP sending module;

the eDP configuration module is used for configuring a DP ip core of the FPGA main control chip according to the screen parameters and the video source parameters acquired by the FPGA main control chip;

the eDP sending module is connected with the eDP configuration module and used for driving the eDP screen through the configured DP ip core.

Preferably, the eDP configuration module includes:

the initialization training module is used for carrying out initialization training configuration on the DP ip core and starting the initialization training of the DP ip core;

and the screen parameter acquisition module is used for acquiring the screen parameters of the eDP screen by using the DP ip core after the initial training of the DP ip core is completed.

Preferably, the eDP configuration module includes:

the clock training module is used for carrying out clock training configuration on the DP ip core according to the screen parameters and starting clock training of the DP ip core;

the channel training module is used for carrying out channel training configuration on the DP ip core according to the screen parameters after the clock training of the DP ip core is finished, and starting the channel training of the DP ip core;

and the point screen configuration module is used for configuring the video information of the DP ip core according to the video source parameters after the channel training of the DP ip core is finished.

Preferably, a state monitoring module is further integrated on the FPGA main control chip; the state monitoring module is connected with an upper computer; the state monitoring module includes:

the state acquisition module is used for acquiring real-time state information of the eDP interface driving module;

and the state uploading module is used for uploading the real-time state information of the eDP interface driving module to the upper computer.

Preferably, a signal receiving module and a signal conversion module are further integrated on the FPGA main control chip;

the signal receiving module is used for receiving LVDS video data;

the signal conversion module is used for converting the LVDS video data into RGB data;

and the eDP interface driving module is used for acquiring the RGB data.

Preferably, a color temperature gamma correction module and a dithering algorithm module are further integrated on the FPGA main control chip;

the color temperature gamma correction module is used for correcting the RGB data after the LVDS video data is converted into the RGB data by the signal conversion module to obtain corrected RGB data;

the dithering algorithm module is used for dithering the corrected RGB data to obtain processed RBG data;

and the eDP interface driving module is used for acquiring the processed RBG data.

According to the technical scheme, the eDP interface driving method and the FPGA main control chip provided by the invention have the advantages that the eDP interface driving module is integrated on the FPGA main control chip, the FPGA main control chip is adopted to directly drive the eDP interface, a special eDP interface driving chip is not required to be adopted to carry out combined driving with the main control chip, and the X86 architecture is not required to be adopted, so that the design is simplified, the cost is reduced, and the universality of the scheme is improved; besides, the DP ip core is a hard core embedded in the FPGA, and the stability of the drive of the eDP interface can be effectively ensured by virtue of the high quality of the DP ip core; and the eDP configuration module of the eDP interface driving module automatically configures the DP ip core according to the screen parameters automatically acquired by the FPGA main control chip, and can support intelligent adaptation and intelligent driving of different eDP screens, so that the driving effect of the eDP interface is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a flowchart of an eDP interface driving method according to an embodiment of the present invention;

fig. 2 is a flowchart of an eDP interface driving method according to a second embodiment of the present invention;

fig. 3 is a flowchart of an eDP interface driving method according to a third embodiment of the present invention;

fig. 4 is a schematic structural diagram of an FPGA main control chip according to a fourth embodiment of the present invention;

fig. 5 is a schematic structural diagram of an FPGA main control chip according to the fifth embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The eDP interface driving method provided by the embodiment of the invention is applied to an FPGA main control chip, and the FPGA main control chip is connected with an eDP screen; an eDP interface driving module (eDP _ TX _ TOP module) is integrated on the FPGA main control chip; the eDP interface driving module includes: an eDP configuration module (eDP _ TX _ CFG module) and an eDP transmission module (eDP _ TX module).

Example one

Referring to fig. 1, fig. 1 is a flowchart illustrating an eDP interface driving method according to an embodiment of the present invention.

As shown in fig. 1, the method includes:

s101: and acquiring video source data and screen parameters of the eDP screen.

The video source data comprises at least video source parameters, but may of course also comprise video data.

After the FPGA main control chip acquires the video data, the video data can be processed by data format conversion, data caching, algorithm realization and the like. And the FPGA main control chip can acquire the screen parameters of the eDP screen through the communication connection with the eDP screen.

In one example, the FPGA main control chip configures an AUX channel register to enable normal communication between a Display Port Intellectual property Core (DP ip Core) of the FPGA and an eDP screen, so as to automatically obtain screen parameters of the eDP screen.

That is to say, the FPAG master chip can automatically acquire the screen parameters of different eDP screens without manually configuring the relevant screen parameters into the FPAG master chip.

S102: and configuring the DP ip core of the FPGA main control chip by using the eDP configuration module according to the screen parameters and the video source parameters.

The eDP configuration module is mainly used for automatically configuring the DP ip core of the FPGA. For example, the DP ip core is subjected to initialization training configuration, clock training configuration, channel training configuration, video information configuration, and reading of corresponding status.

The eDP configuration module configures the DP ip core differently according to different screen parameters and/or different video sources. That is to say, to different eDP screens, the eDP configuration module can carry out different configurations to the DP ip core of FPGA according to different screen parameters, thereby realizing intelligent adaptation and intelligent drive for different eDP screens.

Different eDP screens may refer to that at least one of screen parameters in link bandwidth of the screen, channel number of the screen, voltage swing of the screen, and pre-emphasis value configuration is different, or may refer to that other parameters of the screen are different.

S103: and driving the eDP screen by using the eDP sending module through the configured DP ip core.

In one example, the DP ip core is preset in the eDP sending module, and the eDP sending module instantiates the DP ip core.

The eDP interface driving method provided by the embodiment is applied to an FPGA (field programmable gate array) main control chip, an eDP interface driving module is integrated on the FPGA main control chip, the FPGA main control chip is used for directly driving an eDP interface, a special eDP interface driving chip is not required to be used for carrying out combined driving with the main control chip, and an X86 architecture is not required, so that the design is simplified, the cost is reduced, and the universality of the scheme is improved; moreover, the DP ip core is a hard core embedded in the FPGA, and the stability of the drive of the eDP interface can be effectively ensured by virtue of the high quality of the DP ip core; the eDP configuration module of the eDP interface driving module automatically configures the DP ip core according to the screen parameters automatically acquired by the FPGA main control chip, so that intelligent adaptation and intelligent driving of different eDP screens can be supported, the eDP interface driving effect is improved, and the eDP interface driving requirement is better met.

Example two

Referring to fig. 2, fig. 2 is a flowchart of an eDP interface driving method according to a second embodiment of the present invention.

As shown in fig. 2, the method includes:

s201: video source data is acquired.

The video source data at least comprises video source parameters and video data.

S202: and performing initial training configuration on the DP ip core by using the eDP configuration module, and starting the initial training of the DP ip core.

The initialization training of the DP ip core is a process that the DP ip core must go through, and the initialization training process mainly includes:

a1, resetting the PHY (physical layer interface) of the DP ip core, namely setting the PHY _ RESET register (PHY RESET register) to 1;

a2, turning off the TRANSMITTER signal of DP ip core, setting the TransMITTER _ ENABLE register to 0;

a3, setting AUX communication speed of DP ip core, configuring AUX _ CLOCK _ DIVIDER register (AUX CLOCK frequency dividing register);

the value of the configuration required for the AUX _ CLOCK _ divder register may be calculated according to the AUX communication rate requirement in the DP protocol of the VESA (Video Electronics Standards Association) standard, and written into the AUX _ CLOCK _ divder register.

a4, stopping the PHY RESET of the DP ip core, and setting the PHY _ RESET register to be 0;

a5, checking the PHY state of the DP ip core, reading a PHY _ STATUS (PHY state) register, and if the PHY state indicates that the training is finished, executing a step a 6; otherwise, performing step a 1;

a6, turns on the Transmitter signal of DP ip core, and registers TRANSMITTER _ ENABLE with 1.

After step a6 is completed, the DP ip core initialization training is completed and the DP ip core starts to work normally.

S203: and after the initial training of the DP ip core is completed, acquiring the screen parameters of the eDP screen by using the DP ip core.

After the DP ip core of the FPGA starts to work normally, normal communication can be carried out with the eDP screen, reading and writing control is carried out on a user interface of the DP ip core, and screen parameters of the eDP screen can be automatically acquired. Specifically, the register of the eDP screen may be read through the AUX channel of the DP ip core to obtain the screen parameter of the eDP screen.

S204: and performing clock training configuration on the DP ip core by using the eDP configuration module according to the screen parameters, and starting clock training of the DP ip core.

Since there is no clock path between the DP ip core and the eDP screen, only clock information can be embedded in the sampled data. The purpose of clock training is to enable the eDP screen to normally recover the clock information of the sampled data by sending a specific code. Wherein, the clock training process mainly comprises the following steps:

b1, reading a lane _ count parameter and a line _ bw parameter of the eDP screen;

b2, configuring a lane _ count register and a line _ bw register of the DP ip core according to the read lane _ count parameter and the read line _ bw parameter;

b3, configuring a PHY _ CLOCK register (PHY CLOCK register) of the DP ip core according to the line _ bw parameter;

b4, configuring an eDP screen training register, and starting clock training of an eDP screen end;

b5, configuring a DP ip core training register, and starting the clock training of the DP ip core;

b6, reading a clock training state register of the DP ip core, and if the clock training state indicates that the clock training is successful, finishing the clock training; otherwise, performing step b 7;

b7, adjusting voltage swing and pre-emphasis. And reading a relevant register of the eDP screen to obtain a voltage swing amplitude value and a pre-emphasis value of the eDP screen, configuring the voltage swing amplitude value and the pre-emphasis value into a voltage swing register and a pre-emphasis register of the DP ip core, and executing the clock training process again until the clock training is successful through continuous adjustment.

S205: and utilizing the eDP configuration module to perform channel training configuration on the DP ip core according to the screen parameters after the clock training of the DP ip core is completed, and starting the channel training of the DP ip core.

The channel training is used for finding the starting point of the sampling data and ensuring the correctness of the sampling data. Wherein, the channel training process mainly comprises:

c1, configuring an eDP screen channel training register and starting channel training of an eDP screen end.

c2, configuring a DP ip core channel training register, and starting the channel training of the DP ip core;

c3, reading a channel training status register of the DP ip core, and finishing the channel training if the channel training status register indicates that the channel training is successful; otherwise, performing step c 4;

c4, adjusting voltage swing and pre-emphasis. And reading a relevant register of the eDP screen to obtain a voltage swing amplitude value and a pre-emphasis value of the eDP screen, configuring the voltage swing amplitude value and the pre-emphasis value into a voltage swing register and a pre-emphasis register of the DP ip core, and executing a channel training process again until channel training is successful through continuous adjustment.

S206: and utilizing the eDP configuration module to perform video information configuration on the DP ip core according to the video source parameters after the channel training of the DP ip core is completed.

Wherein, the video source parameters may include:

total field width, effective field width, field sync width, shoulder-after-field width and shoulder-before-field width. Wherein, taking the line number as the unit, the total field width is the field effective width + the field sync width + the field back shoulder width + the field front shoulder width.

Total row width, effective row width, synchronous row width, shoulder back width and shoulder front width. The total line width is the effective line width + the synchronous line width + the back shoulder width + the front shoulder width.

Wherein, the video source bandwidth is the video clock frequency × bpp, and bpp is the number of bits per pixel.

According to the video source information, a field total width register, a field effective width register, a field synchronous width register, a field back shoulder width register, a line total width register, a line effective width register, a line synchronous width register and a line back shoulder width register of the DP ip core can be correspondingly configured.

S207: and driving the eDP screen by using the eDP sending module through the configured DP ip core.

And the eDP sending module outputs eDP interface information through the configured DP ip core and drives an eDP screen.

According to the eDP interface driving method provided by the embodiment, the eDP configuration module is used for carrying out initial training configuration on the DP ip core of the FPGA, after video source parameters and screen parameters of an eDP screen are obtained, clock training and channel training are carried out on the DP ip core according to the obtained screen parameters, video information configuration is carried out on the DP ip core according to the obtained video source parameters, and finally the eDP sending module is used for driving the eDP screen through the configured DP ip core, so that automatic acquisition of the screen parameters of different eDP screens is realized, intelligent adaptation and intelligent driving of different eDP screens can be supported, the eDP interface driving effect is improved, and the eDP interface driving requirements are further met.

EXAMPLE III

Referring to fig. 3, fig. 3 is a flowchart of an eDP interface driving method according to a third embodiment of the present invention.

In this embodiment, the input interface of the FPGA main control chip is an LVDS interface, and correspondingly, the FPGA main control chip further integrates: a signal receiving module (LVDS _ RX module) and a signal converting module (LVDS _ RGB module).

As shown in fig. 3, the method includes:

s301: and receiving the LVDS video data by using the signal receiving module.

The signal receiving module calls the LVDS ip core of the FPGA, and configures the LVDS ip core according to the LVDS interface time sequence to realize the correct receiving of the LVDS signals. Specifically, LVDS ip may be selected as the reception type and configured according to the JEIDA standard.

S302: and converting the LVDS video data into RGB data by using the signal conversion module.

The signal conversion module converts the video data transmitted by the LVDS interface into an RGB format according to the LVDS interface time sequence.

S303: and acquiring the RGB data by using the eDP interface driving module.

In one example, the FPGA main control chip may further integrate: a color temperature gamma correction module (COL _ TEM _ REVISE module) and a dithering algorithm module (DITHER9to6 module). Accordingly, after step S302, the method may further include:

d1, correcting the RGB data by the color temperature gamma correction module to obtain corrected RGB data.

The color temperature gamma correction module stores the color temperature gamma correction parameter table in the local Ram in advance, corrects the input RGB data and outputs the corrected RGB data.

d2, carrying out dithering processing on the corrected RGB data by using the dithering algorithm module to obtain processed RBG data.

The DITHER9to6 module is used for realizing a dithering algorithm, and the purpose of the dithering algorithm is to realize the display effect of 8bits color depth on an eDP screen with 6bits color depth.

Correspondingly, step S303 specifically includes: and acquiring the processed RBG data by using the eDP interface driving module.

S304: acquiring screen parameters and video source parameters of the eDP screen;

s305: configuring a DP ip core of the FPGA main control chip by using the eDP configuration module according to the screen parameters and the video source parameters;

s306: and driving the eDP screen by using the eDP sending module through the configured DP ip core.

The specific implementation process of steps S304 to S306 can refer to the specific contents of steps S101 to S103 or steps S203 to S207 in the foregoing embodiment, and will not be described herein again.

In one example, the FPGA master chip further integrates thereon: a status monitoring module (eDP _ MNT module); and the state monitoring module is connected with an upper computer. Correspondingly, the method further comprises the following steps:

e1, acquiring the real-time state information of the eDP interface driving module by using the state monitoring module.

e2, uploading the real-time state information of the eDP interface driving module to the upper computer by using the state monitoring module.

The state monitoring module can also be used for acquiring real-time state information of each module such as the signal receiving module, the signal conversion module, the color temperature gamma correction module, the dithering algorithm module and the like and uploading the real-time state information to the upper computer.

The state monitoring module is connected with the upper computer through a Serial Peripheral Interface (SPI) bus, the upper computer can acquire relevant states of the modules through the SPI bus and give out corresponding operation instructions, for example, when a certain training fails due to external interference and other factors and finally the eDP screen is not bright, the upper computer can issue a training command to the FPGA again after inquiring state information of the training failure, and the eDP screen is lightened. Therefore, the state monitoring module can enable the eDP interface driving scheme to be more stable.

In an example, the FPGA main control chip may further include a screen hot plug detection signal channel in addition to the eDP video signal channel and the AUX channel.

The eDP interface driving method provided by this embodiment includes receiving LVDS video data by a signal receiving module, converting the LVDS video data into RGB data by a signal converting module, correcting the RGB data by a color temperature gamma correction module, dithering the corrected RGB data by a dithering algorithm module, acquiring the processed RBG data by an eDP interface driving module, configuring a DP ip core of an FPGA by an eDP configuration module according to screen parameters and video source parameters, and driving the eDP screen by the configured DP ip core, so that not only can intelligent adaptation and driving of different eDP screens be supported, but also the eDP screen with a 6-bit color depth can achieve an effect of 8-bit color depth.

The embodiment of the invention also provides an FPGA main control chip, which can be used for implementing the eDP interface driving method provided by the embodiment of the invention, and the technical content of the FPGA main control chip described below can be correspondingly referred to the technical content of the eDP interface driving method described above.

Example four

Referring to fig. 4, fig. 4 is a schematic structural diagram of an FPGA main control chip according to a fourth embodiment of the present invention.

As shown in fig. 4, the FPGA main control chip 10 is connected to an eDP screen 20, and is configured to acquire video source data and screen parameters of the eDP screen 20, where the video source data at least includes video source parameters; the FPGA main control chip comprises: the eDP interface driving module 110;

the eDP interface driving module 110 is integrated on the FPGA main control chip 10; the eDP interface driving module 110 includes: an eDP configuration module 111 and an eDP sending module 112;

the eDP configuration module 111 is configured to configure a DP ip core of the FPGA main control chip 10 according to the screen parameter and the video source parameter acquired by the FPGA main control chip 10;

the eDP sending module 112 is connected to the eDP configuring module 111, and is configured to drive the eDP screen 20 through the configured DP ip core.

The FPGA main control chip provided in this embodiment is integrated with an eDP interface driving module, and the FPGA main control chip is used to directly drive the eDP interface, and does not need to use a dedicated eDP interface driving chip to perform joint driving with the main control chip, and does not depend on an X86 architecture, so that the design is simplified, the cost is reduced, and the universality of the scheme is improved; moreover, the DP ip core is a hard core embedded in the FPGA, and the stability of the drive of the eDP interface can be effectively ensured by virtue of the high quality of the DP ip core; the eDP configuration module of the eDP interface driving module automatically configures the DP ip core according to the screen parameters automatically acquired by the FPGA main control chip, so that intelligent adaptation and intelligent driving of different eDP screens can be supported, the eDP interface driving effect is improved, and the eDP interface driving requirement is better met.

EXAMPLE five

Referring to fig. 5, fig. 5 is a schematic diagram of a structure of an FPGA main control chip according to a fifth embodiment of the present invention.

As shown in fig. 5, the FPGA main control chip 10 of the present embodiment is integrated with a signal receiving module 120, a signal converting module 130, a color temperature gamma correction module 140, a dithering algorithm module 150, and a status monitoring module 160 in addition to the eDP interface driving module 110.

The eDP configuration module 111 may include:

and the initialization training module is used for performing initialization training configuration on the DP ip core and starting the initialization training of the DP ip core.

And the clock training module is used for carrying out clock training configuration on the DP ip core according to the screen parameters and starting the clock training of the DP ip core.

And the channel training module is used for carrying out channel training configuration on the DP ip core according to the screen parameters after the clock training of the DP ip core is finished, and starting the channel training of the DP ip core.

In one example, the status monitoring module 160 is connected to the upper computer 30; the condition monitoring module 160 may include:

a state obtaining module, configured to obtain real-time state information of the eDP interface driving module 110;

and the state uploading module is used for uploading the real-time state information of the eDP interface driving module 110 to the upper computer 30.

In one example, the signal receiving module 120 is connected to the video source 40; the signal receiving module 120 is configured to receive LVDS video data sent by the video source 40.

The signal conversion module 130 is configured to convert the LVDS video data into RGB data.

Correspondingly, the eDP interface driving module 110 is configured to obtain the RGB data.

In an example, the color temperature gamma correction module 140 is configured to correct the RGB data after the LVDS video data is converted into the RGB data by the signal conversion module, so as to obtain corrected RGB data.

The dithering algorithm module 150 is configured to dither the corrected RGB data to obtain processed RBG data.

In this example, the eDP interface driving module 110 is specifically configured to acquire the processed RBG data.

The FPGA main control chip provided by the embodiment utilizes the eDP configuration module to perform initial training configuration on the DP ip core of the FPGA, performs clock training and channel training on the DP ip core according to the acquired screen parameters after acquiring the video source parameters and the screen parameters of the eDP screen, performs video information configuration on the DP ip core according to the acquired video source parameters, and finally utilizes the eDP sending module to drive the eDP screen through the configured DP ip core, thereby realizing automatic acquisition of the screen parameters of different eDP screens, supporting intelligent adaptation and driving of different eDP screens, improving the drive effect of the eDP interface, and further meeting the drive requirements of the eDP interface.

And moreover, the LVDS video data is received by the signal receiving module, the LVDS video data is converted into RGB data by the signal conversion module, the RGB data is corrected by the color temperature gamma correction module, the corrected RGB data is subjected to jitter processing by the jitter algorithm module, the processed RBG data is acquired by the eDP interface driving module, the DP ip core of the FPGA is configured by the eDP configuration module according to screen parameters and video source parameters, and the eDP transmitting module is used for driving the eDP screen through the configured DP ip core, so that intelligent adaptation and driving of different eDP screens can be supported, and the eDP screen with the color depth of 6bits can achieve the effect of the color depth of 8 bits.

Finally, it is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

Through the above description of the embodiments, it is clear to those skilled in the art that the present application can be implemented in the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. With this understanding in mind, the technical solutions of the present application may be embodied in whole or in part in the form of a software product, which may be stored in a storage medium such as a ROM/RAM, a magnetic disk, an optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments of the present application.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, the specific embodiments and the application range may be changed. In view of the above, the description should not be taken as limiting the application.

Claims

1. The eDP interface driving method is characterized by being applied to an FPGA main control chip, wherein the FPGA main control chip is connected with an eDP screen; an eDP interface driving module is integrated on the FPGA main control chip; the eDP interface driving module includes: the eDP configuration module and the eDP sending module; the method comprises the following steps:

driving the eDP screen by using the eDP sending module through the configured DP ip core;

configuring a display interface intellectual property core DP ip core of the FPGA main control chip according to the screen parameters and the video source parameters by using the eDP configuration module, wherein the method comprises the steps of performing clock training configuration on the DP ip core according to the screen parameters by using the eDP configuration module, and starting clock training of the DP ip core;

2. The method of claim 1, wherein the screen parameter obtaining process comprises:

3. The method of claim 1, wherein a status monitoring module is further integrated on the FPGA master chip; the state monitoring module is connected with an upper computer; the method further comprises the following steps:

4. The method of claim 1, wherein a signal receiving module and a signal conversion module are further integrated on the FPGA master control chip; the video source data further comprises video data; the video data acquisition process comprises the following steps:

receiving LVDS video data by using the signal receiving module;

and acquiring the RGB data by using the eDP interface driving module.

5. The method of claim 4, wherein a color temperature gamma correction module and a dithering algorithm module are further integrated on the FPGA main control chip; after the converting the LVDS video data into RGB data by the signal conversion module, the method further includes:

6. An FPGA main control chip is characterized in that the FPGA main control chip is connected with an eDP screen and is used for acquiring video source data and screen parameters of the eDP screen, wherein the video source data at least comprises video source parameters; the FPGA main control chip comprises: an eDP interface driving module;

the eDP sending module is connected with the eDP configuration module and used for driving the eDP screen through the configured DP ip core;

wherein the eDP configuration module comprises:

7. The FPGA master control chip of claim 6, wherein the eDP configuration module comprises:

8. The FPGA main control chip of claim 6, wherein a status monitoring module is further integrated on the FPGA main control chip; the state monitoring module is connected with an upper computer; the state monitoring module includes:

9. The FPGA main control chip of claim 6, wherein a signal receiving module and a signal conversion module are further integrated on the FPGA main control chip;

the signal receiving module is used for receiving LVDS video data;

and the eDP interface driving module is used for acquiring the RGB data.

10. The FPGA master control chip of claim 9, further integrated with a color temperature gamma correction module and a dithering algorithm module;