CN105703767B - A kind of single loop clock data recovery circuit of high energy efficiency low jitter - Google Patents
A kind of single loop clock data recovery circuit of high energy efficiency low jitter Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The invention discloses a kind of single loop clock data recovery circuits of high energy efficiency low jitter, including：With 1:1/N rate Bang Bang phase discriminators, voltage current adapter, loop filter and the multi-phase clock generator of N tap device function；Wherein, the quadrature clock signal that orthogonal voltage-controlled vibrator generates in the multi-phase clock generator, by (N+2) phase recovered clock signal needed for the synthesis of cascade digit phase interpolation device, then 1/N rates Bang Bang phase discriminators receive input data and clock signal, it detects phase relation between the two and generates lead-lag voltage signal, and recover the parallel 1/N rate data signals in the roads N, then lead-lag voltage signal is converted into current signal by voltage current adapter, the electric current controls output clock frequency and the phase relation of multi-phase clock generator to reduce frequency departure and then reach the PGC demodulation of clock and data recovery loop after loop filter filters.The present invention effectively improves the jitter performance of clock and data recovery loop.
Description
Technical field
The present invention relates to serial communication and technical field of integrated circuits more particularly to a kind of single loops of high energy efficiency low jitter
Clock data recovery circuit.
Background technology
High-frequency clock data restore the comprising modules that (CDR) circuit is crucial in optical electrical communication system, such as in synchronizable optical
The receiver end of the high speeds serial communication systems such as fibre web (SONET), passive optical network (PON) and ten thousand mbit ethernets (10GbE), when
The main target of clock data recovery circuit is exactly to recover clock signal simultaneously from input data in a manner of high energy efficiency low jitter
The data received when resetting using this recovered clock, this is very challenging and significance a task, especially
It is the continuous rising (it is even higher to have reached 10Gbps) with message transmission rate.
The structure of clock data recovery circuit based on phaselocked loop (PLL) as shown in Figure 1, the structure by frequency tracking loop
Road (Frequency Tracking Loop) and phased lock loop (Phase Locking Loop) are constituted, and work as clock data
When restoring circuit starts, lock detector (Lock Detector) controls multiplexer (MUX) activation first with mirror by selection
The frequency lock loop of frequency phase discriminator (Phase/Frequency Detector), the oscillation frequency of adjustment voltage controlled oscillator (VCO)
Rate；When the output frequency of voltage controlled oscillator is equal to M times external reference clock (Ref_Clk) frequency, frequency lock loop is disconnected
It opens, the phased lock loop with phase discriminator (Phase Detector) is started to work, and the output for adjusting voltage controlled oscillator is continued
Frequency until with input data PGC demodulation, then pass through data decision (Data Decision) circuit retimed data.The knot
Two loops of structure can share charge pump (Charge Pump), loop filter (Loop Filter) and voltage controlled oscillator, pass through
Lock detector completes loop switching, however may interfere with the control voltage of voltage controlled oscillator in this way and cause between loop
Metastable state is converted, so as to cause the losing lock of entire clock and data recovery loop；In addition, for port spacing and number critical constraints
Application (such as headend), using outside provide low noise crystal oscillator as refer to clock can increase it is additional
Cost and design difficulty；Importantly, external reference clock signal can by encapsulation or printed circuit board (PCB) be coupled to it is low
In the input data of the amplitude of oscillation, and then deteriorate the jitter performance of traditional clock data recovery circuit based on phase-locked loop structures.
The structure of clock data recovery circuit based on phase interpolator (PI) is as shown in Fig. 2, the structure also needs two
A loop, different from based on phase-locked loop structures, frequency lock loop orthogonal voltage-controlled vibrator (Quadrature herein
VCO voltage controlled oscillator) is replaced, the quadrature clock signal needed for phased lock loop is generated；And phased lock loop is filtered with number
Wave device (Digital LF) and digital analog converter (DAC) replace charge pump and filter, with phase interpolator (Phase
Interpolator voltage controlled oscillator) is replaced, ensures the stability and quick lock in of clock data recovery circuit.The structure can be with
Avoid the problem that shake peak value, but the precision of digital analog converter, the linearity of phase interpolator and loop delay are all by direct shadow
Ring the jitter performance of the clock data recovery circuit based on phase interpolator structure；Importantly, based on phase interpolator
Frequency lock loop needs to work always in structure, thus brings prodigious power consumption to entire clock data recovery circuit and makes an uproar
Sound source, and on chip between two loops transmission with input data the same frequency quadrature clock signal (reach 10GHz or
Higher) it is difficult to ensure that phase interpolator receives the frequency stability and phase orthogonality of clock, and then influence phased lock loop
Normal locking and traditional clock data recovery circuit based on phase interpolator structure jitter performance.
As to rise to 10Gbps even higher for input data rate, inserted to reduce phase discriminator, voltage controlled oscillator or phase
It is worth the working frequency of device, and then reduces required multi-phase clock frequency, the structure quilt of the clock data recovery circuit of 1/N rates
It is widely used, as shown in Figure 3.This configuration avoids the accessible highest frequency limitations of on piece clock, save significantly on
The power consumption of 1/N rate architectures；But the clock data recovery circuit of tradition 1/N rate architectures needs to provide 2N multi-phase clock to 1/
The phase discriminator of N rates goes sampling input data, this undoubtedly increases additional power consumption and design complexities, it is often more important that, mistake
It is easy to cause phase deviation between the multi-phase clock of more number, and then influences the clock and data recovery of entire 1/N rate architectures
The jitter performance of circuit.
Invention content
Technical problems based on background technology, the present invention propose a kind of single loop clock number of high energy efficiency low jitter
According to restoring circuit.
A kind of single loop clock data recovery circuit of high energy efficiency low jitter proposed by the present invention, including：Phase discriminator, electricity
Piezo-electric stream transformer, loop filter and multi-phase clock generator, wherein phase discriminator includes 1:N tap device function module；
The first input end of phase discriminator accesses input data, and output end is connect with voltage-current converter, electric piezo-electric
Stream transformer output end is connect with loop filter input terminal, the input of the output end and multi-phase clock generator of loop filter
End connection, the output end of multi-phase clock generator and the second input terminal of phase discriminator connect；
Phase discriminator receives the M clock signals of input data and multi-phase clock generator output, and according between the two
Phase relation generates leading voltage signal and lagging voltage signal, M=N+2；Voltage-current converter is according to leading voltage signal
Current signal is generated with lagging voltage signal, loop filter is filtered current signal and generates control voltage signal；It is more
Phase clock generator constantly reduces the frequency between the M clock signals of output and input data under the adjustment of control voltage signal
Rate deviation and phase difference, until M clock signals and the phase alignment of input data reach loop-locking state；
The recovered clock signal of the clock recovery circuitry is the M phases that multi-phase clock generator exports under loop-locking state
Clock signal.
Preferably, phase discriminator uses 1/N rate Bang-Bang phase discriminators.
Preferably, phase discriminator includes：N number of data sampler, an edge sampler and two XOR gates；The phase discriminator
It is preset with N phase datas sampling clock, edge sampling clock and synchronised clock, and the frequency of N phase data sampling clocks, edge sample
The frequency of clock and the frequency of synchronised clock are equal to the 1/N of input data frequency；
The input terminal of N number of data sampler and the input terminal of edge sampler are all connected with the first input of the phase discriminator
End, N number of data sampler respectively sample input data under the control of N phase data sampling clocks, and edge sampler exists
The edge of input data is sampled under edge sampling clock control；
N number of data sampler corresponds to a synchronizer respectively, and the output end of data sampler connects corresponding synchronizer
Input terminal, N number of synchronizer under the control of synchronised clock to being reset respectively to the input data sampled signal of input when simultaneously
1/N rate recovery data-signals are generated, the 1/N rate recovery data-signals of N number of microsyn output end output are mutually parallel；It adopts at edge
There are one synchronizer, the synchronizers to be carried out again to the data edge sampled signal of input under synchronised clock control for the connection of sample device
Timing simultaneously exports recovery edge signal；
Two input terminals of one XOR gate are respectively connected to a 1/N rate recoveries data-signal and restore edge signal,
Then the leading voltage signal for including phase information between data sampling clock and input data is generated；Another XOR gate
Two input terminals are respectively connected to another 1/N rate recoveries data-signal and restore edge signal, then generate and are adopted comprising data
The lagging voltage signal of phase information between sample clock and input data.
Preferably, N=4.
Preferably, multi-phase clock generator is made of cascade orthogonal voltage-controlled vibrator and digital phase interpolator.
In the present invention, the quadrature clock signal of orthogonal voltage-controlled vibrator generation, process are cascade in multi-phase clock generator
M phase recovered clock signals needed for the synthesis of digit phase interpolation device, then 1/N rates Bang-Bang phase discriminators, which receive, inputs number
According to M clock signals, detect phase relation between the two and generate lead-lag voltage signal, and it is parallel to recover the roads N
1/N rate data signals, then lead-lag voltage signal current signal is converted by voltage-current converter, the electric current
Output clock frequency and the phase relation of multi-phase clock generator are controlled after loop filter filters to reduce frequency departure
And then reach the PGC demodulation of clock and data recovery loop.M=N+2.
The present invention proposes a kind of clock data recovery circuit framework with compact 1/N rate Bang-Bang phase discriminators,
While reducing the modules working frequencies such as Bang-Bang phase discriminators, orthogonal voltage-controlled vibrator and digital phase interpolator, no
Circuit entire area burden and design complexities are only alleviated, and are effectively reduced needed for the sampling of Bang-Bang phase discriminators
Multi-phase clock number and overall power consumption；The present invention using no reference clock single loop clock data recovery circuit structure,
Loop jitter performance deleterious effects caused by external reference clock couples input data are not only eliminated, and are avoided bicyclic
Switching controls the interference of voltage and to the influence of loop stability to voltage controlled oscillator between road；In addition, orthogonal voltage controlled oscillation
Device and digital phase interpolator grade are associated in the design of the multi-phase clock generator in the same clock and data recovery loop, eliminate biography
System double loop structure is used for generating extra power consumption and noise source caused by the phase-locked loop of multi-phase clock, not only greatly simplifies
The structure of entire clock data recovery circuit, and the efficiency of clock data recovery circuit is effectively increased, while effectively changing
It has been apt to the jitter performance of clock and data recovery loop.
Description of the drawings
Fig. 1 is the structural schematic diagram of the clock data recovery circuit based on phase-locked loop pll；
Fig. 2 is the structural schematic diagram of the clock data recovery circuit based on phase interpolator PI；
Fig. 3 is the structural schematic diagram of 1/N rate clock data recovery circuits；
Fig. 4 is a kind of structural representation of the single loop clock data recovery circuit of high energy efficiency low jitter provided by the invention
Figure；
Fig. 5 is a kind of knot of the single loop clock data recovery circuit of the high energy efficiency low jitter provided in the embodiment of the present invention
Structure schematic diagram；
Fig. 6 is that the one kind provided in the embodiment of the present invention carries 1:1/4 rate Bang-Bang of 4 coupler DEMUX functions
The structural schematic diagram of phase discriminator QR-BBPD；
Fig. 7 is the structural schematic diagram of the multi-phase clock generator MPG provided in the embodiment of the present invention a kind of；
Fig. 8 is a kind of single loop clock data recovery circuit output of the high energy efficiency low jitter provided in the embodiment of the present invention
6 phase recovered clock signal waveforms；
Fig. 9 is a kind of single loop clock data recovery circuit output of the high energy efficiency low jitter provided in the embodiment of the present invention
The phase noise curve graph of recovered clock signal；
Figure 10 is that a kind of single loop clock data recovery circuit of the high energy efficiency low jitter provided in the embodiment of the present invention is defeated
The recovered clock eye pattern gone out；
Figure 11 is that a kind of single loop clock data recovery circuit of the high energy efficiency low jitter provided in the embodiment of the present invention is defeated
The recovery data eye gone out.
Specific implementation mode
Reference Fig. 4, a kind of single loop clock data recovery circuit of high energy efficiency low jitter proposed by the present invention, including：Mirror
Phase device, voltage-current converter, loop filter and multi-phase clock generator.Wherein, phase discriminator phase discriminator uses 1/N rates
Bang-Bang phase discriminators comprising 1:N tap device function module.
The first input end of phase discriminator accesses input data DATA, and output end is connect with voltage-current converter, electricity
Piezo-electric stream transformer output end is connect with loop filter input terminal, the output end and multi-phase clock generator of loop filter
Input terminal connection, the second input terminal of the output end of multi-phase clock generator and phase discriminator connects.
Phase discriminator receives the M clock signals of input data and multi-phase clock generator output, and according between the two
Phase relation generates leading voltage signal UP and lagging voltage signal DN, M=N+2.
Phase discriminator includes：N number of data sampler, an edge sampler and two XOR gates.It is preset in the phase discriminator
There are N phase datas sampling clock, edge sampling clock and synchronised clock, and the frequency of N phase data sampling clocks, edge sampling clock
Frequency and the frequency of synchronised clock be equal to the 1/N of input data DATA frequencies.
The input terminal of N number of data sampler and the input terminal of edge sampler are all connected with the first input of the phase discriminator
End, N number of data sampler carry out sampling generation input data to input data under the control of N phase data sampling clocks respectively and adopt
Sample signal, edge sampler carry out sampling to the edge of input data under the control of edge sampling clock and generate data edge sampling
Signal.
N number of data sampler corresponds to a synchronizer respectively, and the output end of data sampler connects corresponding synchronizer
Input terminal, N number of synchronizer under the control of synchronised clock to being reset respectively to the input data sampled signal of input when simultaneously
1/N rate recovery data-signals are generated, the 1/N rate recovery data-signals of N number of microsyn output end output are mutually parallel.It adopts at edge
There are one synchronizer, the synchronizers to be carried out again to the data edge sampled signal of input under synchronised clock control for the connection of sample device
Timing simultaneously exports recovery edge signal.
Two input terminals of one of XOR gate are respectively connected to a 1/N rate recoveries data-signal and restore edge letter
Number, then generate the leading voltage signal UP for including phase information between data sampling clock and input data DATA；It is another
Two input terminals of a XOR gate are respectively connected to another 1/N rate recoveries data-signal and restore edge signal, then generate
Including between data sampling clock and input data DATA phase information lagging voltage signal DN.
Voltage-current converter generates current signal I according to leading voltage signal UP and lagging voltage signal DNVIC, loop
Filter is to current signal IVICIt is filtered and generates control voltage signal VCTRL.Multi-phase clock generator is in control voltage letter
Number VCTRLAdjustment under constantly reduce frequency departure and phase difference between the M clock signals of output and input data DATA,
Until M clock signals and the phase alignment of input data reach loop-locking state, recovered clock signal at this time is more
The clock signal that phase clock generator is recovered from input data, and recovery data-signal at this time is 1/N rates Bang-
Bang phase discriminators synchronize the parallel 1/N rate data signals in the roads N recovered by (N+2) phase recovered clock signal sampling.That is,
The recovered clock signal RE_CIK of clock recovery circuitry is the M phase clocks letter that multi-phase clock generator exports under loop-locking state
Number.
In present embodiment, multi-phase clock generator is by cascade orthogonal voltage-controlled vibrator and digital phase interpolator group
At, wherein output of the input terminal of orthogonal voltage-controlled vibrator as the input terminal linkloop filter of multi-phase clock generator
End is to access control voltage signal VCTRL.Orthogonal voltage-controlled vibrator is in control voltage signal VCTRLAdjustment under, constantly reduce output
Clock and input data Data between frequency departure.The input terminal of digit phase interpolation device connects with orthogonal voltage-controlled vibrator
It connects, output end connects the second input terminal of phase discriminator as the output end of multi-phase clock generator, voltage-controlled is shaken according to orthogonal
The signal synthesis M clock signals of device input are swung, and in control voltage signal VCTRLEffect is lower to reduce M clock signals and input
Phase difference between data Data.
The present invention is further explained below in conjunction with a specific embodiment.
With reference to Fig. 5, in a kind of single loop clock data recovery circuit of high energy efficiency low jitter provided in this embodiment, phase demodulation
Device is using with 1:The 1/4 rate Bang-Bang phase discriminators of 4 couplers (DEMUX, Demultiplexer) function module
(QR-BBPD,Quarter-Rate Bang-Bang Phase Detector)。
With 1:When 1/4 rate Bang-Bang phase discriminators of 4 coupler function modules receive input data Data and multiphase
6 phase recovered clock signal Re_Clk of clock generator output, and generated and surpassed according to the testing result of phase relation between the two
Preceding voltage signal UP and lagging voltage signal DN.
Lead-lag voltage signal Up/Dn is converted into corresponding current signal IVIC by voltage-current converter VIC；Ring
Path filter LF receives the transformed current signal IVIC of lead-lag voltage, generates multi-phase clock generator MPG's after filtering
Control voltage signal VCTRL；Multi-phase clock generator MPG constantly reduces output under the adjustment of control voltage signal VCTRL
Frequency departure and phase difference between 6 phase recovered clock signal Re_Clk and input data Data.Clock signal Re_ when recovered
The phase alignment of Clk and input data Data reach loop-locking state, and recovered clock signal Re_Clk at this time is multiphase
The clock signal that clock generator MPG is recovered from input data Data, and recovery data-signal Re_Data at this time is
1/4 rate Bang-Bang phase discriminators QR-BBPD is parallel by 4 tunnels that 6 phase recovered clock signal Re_Clk sample-synchronous recover
1/4 rate data signal.
Fig. 6, which is shown, provided in this embodiment carries 1:1/4 rate Bang-Bang phase discriminators of 4 coupler function modules
The structural schematic diagram of QR-BBPD.
The phase discriminator utilizes 4 data samplers (sampler 1, sampler 2, sampler 4 and sampler 5) and 4 phase datas
Sampling clock Re_Clk0, Re_Clk90, Re_Clk180 and Re_Clk270 sample input data Data, and utilize one
Edge sampler (sampler 3) and edge sampling clock Re_Clk135 sample input data edge, then utilize 5 synchronizations
Device (synchronizer 1, synchronizer 2, synchronizer 3, synchronizer 4 and synchronizer 5) and a synchronised clock Re_Clk315 are come when resetting
4 tunnel input data sampled signals and data edge sampled signal, wherein input data sampled signal are the input data after sampling,
Data edge sampled signal is the input data edge after sampling.Phase discriminator recovers 4 tunnels simultaneously according to input data sampled signal
1/4 capable rate recovery data-signal Re_Data0, Re_Data1, Re_Data2 and Re_Data3, and adopted according to data edge
Sample signal, which recovers, restores edge signal Re_Edge0, wherein two-way restore data-signal Re_Data1 and Re_Data2 respectively and
Restore edge signal Re_Edge0 to generate by XOR gate XOR_1 and XOR_2 to include sampling clock Re_Clk and input data
The leading voltage signal UP of phase information and lagging voltage signal DN between Data, wherein all 6 phase clock Re_Clk0, Re_
The frequency of Clk90, Re_Clk135, Re_Clk180, Re_Clk270 and Re_Clk315 are equal to input data Data frequencies
1/4。
Fig. 7 show the structural schematic diagram of multi-phase clock generator MPG provided in this embodiment.Multi-phase clock generator
MPG is by cascade orthogonal voltage-controlled vibrator (QVCO, Quadrature Voltage-Controlled Oscillator) sum number
Word phase interpolator (DPI, Digital Phase Interpolator) forms, in control voltage signal VCTRLAdjustment under,
Constantly reduce the frequency between the orthogonal clock (Ip, Qp, In and Qn) and input data Data of orthogonal voltage-controlled vibrator QVCO outputs
Rate deviation and 6 clock signal (Re_Clk0, Re_Clk90, Re_Clk135, Re_ of digit phase interpolation device DPI synthesis
Clk180, Re_Clk270 and Re_Clk315) phase difference between input data Data.
Advantageous effect in order to further illustrate the present invention, when to the single loop of high energy efficiency low jitter provided in this embodiment
Clock data recovery circuit has carried out simulating, verifying.Input data Data is the pseudo-random sequence of 10.3125Gbps in embodiment, is imitated
A length of 10us when true, whole clock data recovery circuit loop are locked in about 2.3us or so, the recovered clock signal of 1/4 rate
Re_Clk0, Re_Clk90, Re_Clk135, Re_Clk180, Re_Clk270 and Re_Clk315 frequency be 2.578125GHz, 1/
Recovery data-signal Re_Data0, Re_Data1, Re_Data2 and Re_Data3 data transfer rate of 4 rates is 2.578125Gbps.
Fig. 8 show the 6 phase recovered clock signal waveforms that multi-phase clock generator MPG is exported in the present embodiment, orthogonal
The 6 phase recovered clocks that the multi-phase clock generator MPG of voltage controlled oscillator QVCO and digital phase interpolator DPI cascade compositions is provided
Signal Re_Clk0, Re_Clk90, Re_Clk135, Re_Clk180, Re_Clk270 and Re_Clk315 are in output frequency
The average phase error of the vicinity 2.578125GHz is 0.015 °, illustrates the extensive of the clock data recovery circuit output of the present invention
There is accurate phase relation between multiple clock signal.
Fig. 9 show a kind of single loop clock data recovery circuit output of the high energy efficiency low jitter provided in the present embodiment
The phase noise curve graph of recovered clock signal, orthogonal voltage-controlled vibrator QVCO and digital phase interpolator DPI cascade compositions
Phase noises of the recovered clock signal Re_Clk that multi-phase clock generator MPG is provided at 1MHz frequencies is -118dBC/Hz,
Illustrate that the recovered clock signal of the clock data recovery circuit output of the present invention has good noiseproof feature.
Figure 10 show a kind of single loop clock and data recovery electricity of the high energy efficiency low jitter provided in the embodiment of the present invention
The recovered clock eye pattern of road output, in the case where inputting 231-1 pseudo-random sequence data, 1/4 rate that recovers when
Clock has the Peak Jitter of 1.14ps, and it is fine to illustrate that the recovered clock signal of the clock data recovery circuit output of the present invention has
Jitter performance.
Figure 11 show a kind of single loop clock and data recovery electricity of the high energy efficiency low jitter provided in the embodiment of the present invention
The recovery data eye of road output, in the case where inputting 231-1 pseudo-random sequence data, the number of 1/4 rate recovered
According to the Peak Jitter with 1.21ps, illustrate that the recovery data-signal of the clock data recovery circuit output of the present invention equally has
The advantages of low jitter；In addition, the clock data recovery circuit in the embodiment of the present invention consumes altogether under 1.1V supply voltages
4.8mW, wherein multi-phase clock generator MPG consume 3.4mW, and circuit entirety efficiency is 0.47pJ/b, illustrates the clock of the present invention
Data recovery circuit has very high efficiency under high data rate applications.
It is apparent to those skilled in the art that for convenience and simplicity of description, only with above-mentioned each function
The division progress of module, can be as needed and by above-mentioned function distribution by different function moulds for example, in practical application
Block is completed, i.e., the internal structure of device is divided into different function modules, to complete all or part of work(described above
Energy.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Any one skilled in the art in the technical scope disclosed by the present invention, according to the technique and scheme of the present invention and its
Inventive concept is subject to equivalent substitution or change, should be covered by the protection scope of the present invention.
Claims (4)
1. a kind of single loop clock data recovery circuit of high energy efficiency low jitter, which is characterized in that including：Phase discriminator, electric piezo-electric
Stream transformer, loop filter and multi-phase clock generator, wherein phase discriminator includes 1:N tap device function module；
The first input end access input data (DATA) of phase discriminator, output end is connect with voltage-current converter, voltage-
Current converter output end is connect with loop filter input terminal, the output end of loop filter and multi-phase clock generator it is defeated
Enter end connection, the output end of multi-phase clock generator and the second input terminal of phase discriminator connect；
Phase discriminator receives the M clock signals of input data and multi-phase clock generator output, and according to phase between the two
Relationship generates leading voltage signal (UP) and lagging voltage signal (DN), M=N+2；Voltage-current converter is according to leading voltage
Signal (UP) and lagging voltage signal (DN) generate current signal (IVIC), loop filter is to current signal (IVIC) be filtered
And generate control voltage signal (VCTRL)；Multi-phase clock generator is in control voltage signal (VCTRL) adjustment under constantly reduce it is defeated
Frequency departure and phase difference between the M clock signals gone out and input data (DATA), until M clock signals and input number
According to phase alignment reach loop-locking state；
The recovered clock signal (RE_CIK) of the clock recovery circuitry is that multi-phase clock generator exports under loop-locking state
M clock signals；
Phase discriminator includes：N number of data sampler, an edge sampler and two XOR gates；The phase discriminator is preset with the N numbers of phases
According to sampling clock, edge sampling clock and synchronised clock, and the frequency of N phase data sampling clocks, the frequency of edge sampling clock
The 1/N of input data frequency is equal to the frequency of synchronised clock；
The input terminal of N number of data sampler and the input terminal of edge sampler are all connected with the first input end of the phase discriminator, N number of
Data sampler respectively samples input data under the control of N phase data sampling clocks, and edge sampler is adopted at edge
The edge of input data is sampled under sample clock control；
N number of data sampler corresponds to a synchronizer respectively, and the output end of data sampler connects the input of corresponding synchronizer
End, when N number of synchronizer respectively resets the input data sampled signal of input under the control of synchronised clock and generates 1/N
The 1/N rate recovery data-signals of rate recovery data-signal, N number of microsyn output end output are mutually parallel；Edge sampler connects
It connects there are one synchronizer, which retimes simultaneously to the data edge sampled signal of input under synchronised clock control
Output restores edge signal；
Two input terminals of one XOR gate are respectively connected to a 1/N rate recoveries data-signal and restore edge signal, then
Generate the leading voltage signal (UP) for including phase information between data sampling clock and input data (Data)；Another is different
Or two input terminals of door are respectively connected to another 1/N rate recoveries data-signal and restore edge signal, then generation includes
The lagging voltage signal (DN) of phase information between data sampling clock and input data (Data).
2. the single loop clock data recovery circuit of high energy efficiency low jitter as described in claim 1, which is characterized in that phase discriminator
Using 1/N rate Bang-Bang phase discriminators.
3. the single loop clock data recovery circuit of high energy efficiency low jitter as described in claim 1, which is characterized in that N=4.
4. the single loop clock data recovery circuit of high energy efficiency low jitter as described in claim 1, which is characterized in that when multiphase
Clock generator is made of cascade orthogonal voltage-controlled vibrator and digital phase interpolator.
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