CN112181716B - Data recovery circuit based on delay phase-locked loop - Google Patents
Data recovery circuit based on delay phase-locked loop Download PDFInfo
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- 238000001514 detection method Methods 0.000 claims abstract description 59
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1446—Point-in-time backing up or restoration of persistent data
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
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Abstract
The application discloses a data recovery circuit based on a delay phase-locked loop, which comprises a main loop and a compensation branch; the main loop includes: a phase detector for detecting a phase difference between the data signal and the clock signal and outputting a corresponding detection result signal and down-sampling result signal; a charge pump connected to the phase detector; an accumulator connected to the charge pump; the phase interpolator is connected with the energy accumulator and is used for generating a clock adjusting signal corresponding to the voltage signal output by the energy accumulator to the phase detector so as to adjust the phase of the clock signal and enable the phase of the clock signal to be matched with the phase of the data signal; the input end of the compensation branch is connected with the phase detector, and the output end of the compensation branch is connected with the charge pump and is used for carrying out current compensation on the charge pump according to the down-sampling result signal. The application not only avoids the limitation of digital devices to circuit bandwidth, but also solves the problem of mismatch of the current mirror in the charge pump by utilizing the compensation branch, and effectively improves the high-frequency jitter tolerance of the data recovery circuit.
Description
Technical Field
The application relates to the technical field of data serial-parallel connection transmission, in particular to a data recovery circuit based on a delay phase-locked loop.
Background
The data recovery circuit based on bang-bang DLL (delayed lock loop, delay phase locked loop) has the characteristics of simple circuit, low power consumption, small area and the like, and is widely applied to a modern wired communication system. The Bang (also called binary) Phase Detector (PD) has simple and fast circuit and plays a role in high-speed data recovery circuit.
As shown in fig. 1, a data recovery circuit based on an analog bang-bang DLL is provided in the prior art, and mainly consists of a Phase Detector (PD), a Charge Pump (CP) and a Phase interpolator (Phase interpolator, PI). The biggest problem that it exists is the mismatch problem of the current mirror of charge pump, and when the current mirror mismatch can lead to the input high frequency shake, the sampling point of clock skew leads to adopting wrong data, increases the error rate.
As shown in fig. 2, another digital DLL data recovery circuit is also provided in the prior art, and compared with fig. 1, the digital DLL data recovery circuit replaces the charge pump and the capacitor C with a shift register (PHASE SHIFTER) and a digital-to-analog converter (digital to Analog converter, DAC), and the speed of the digital DLL is limited by the speed of the shift register and the DAC, so that the bandwidth cannot be increased, and the tracking performance of the high-frequency jitter is affected, although the problem of the mismatch of the current mirror of the charge pump can be fundamentally eliminated.
In view of this, it has been a great need for a person skilled in the art to provide a solution to the above-mentioned technical problems.
Disclosure of Invention
The application aims to provide a data recovery circuit based on a delay phase-locked loop, so that the problem of mismatch of a current mirror is solved, the error rate is reduced, and meanwhile, the range of the bandwidth which can be taken can be effectively expanded, and the tracking performance of the data recovery circuit on high-frequency jitter is improved.
In order to solve the technical problems, in a first aspect, the application discloses a delay locked loop-based data recovery circuit, which comprises a main loop and a compensation branch; the main loop includes:
a phase detector for detecting a phase difference between the data signal and the clock signal and outputting a corresponding detection result signal and down-sampling result signal; the downsampling result signal is generated by the downsampling process of the detection result signal;
a charge pump connected to the phase detector for generating and outputting a current signal corresponding to the detection result signal;
the energy accumulator is connected with the charge pump and is used for generating and outputting a voltage signal corresponding to the current signal;
A phase interpolator connected to the energy storage device, for generating and outputting a clock adjustment signal corresponding to the voltage signal to the phase detector, so as to adjust the phase of the clock signal, so that the clock signal is phase-matched with the data signal;
The input end of the compensation branch is connected with the phase detector, and the output end of the compensation branch is connected with the charge pump and is used for outputting corresponding compensation current according to the downsampling result signal so as to perform current compensation on the charge pump.
Optionally, the compensating branch comprises an accumulator, a digital-to-analog converter and a voltage-to-current converter which are sequentially connected;
the input end of the accumulator is connected with the phase detector; the output end of the voltage-current converter is connected with the charge pump.
Optionally, the charge pump comprises a first current source, a second current source, a first switch and a second switch;
the input end of the second current source is connected with a power supply; the output end of the second current source is connected with the first end of the second switch and the output end of the compensation branch; the second end of the second switch is connected with the first end of the first switch and is used as the output end of the charge pump; the second end of the first switch is connected with the input end of the first current source; the output end of the first current source is grounded;
The detection result signals comprise a first detection result signal and a second detection result signal; the first detection result signal is used for controlling the on-off of the first switch; the second detection result signal is used for controlling the on-off of the second switch.
Optionally, the phase detector includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first exclusive-or gate, a second exclusive-or gate, a first and gate, a second and gate, a frequency dividing circuit, and a downsampling circuit; the third D flip-flop is effective at low level, and the rest D flip-flops are effective at high level;
the input end of the first D trigger is connected with the input end of the third D trigger and is used as the input end of the phase detector; the output end of the first D trigger is respectively connected with the input end of the second D trigger and the first input end of the first exclusive-OR gate; the output end of the second D trigger is connected with the first input end of the second exclusive-OR gate;
The output end of the third D trigger is connected with the input end of the fourth D trigger; the output end of the fourth D trigger is respectively connected with the second input end of the first exclusive-OR gate and the second input end of the second exclusive-OR gate; the clock ends of the D triggers are connected with each other, serve as the clock end of the phase detector and are connected with the input end of the frequency dividing circuit;
the output end of the first exclusive-or gate is used for outputting the first detection result signal and is connected with the first input end of the first AND gate; the output end of the second exclusive-or gate is used for outputting the second detection result signal and is connected with the first input end of the second AND gate;
The output end of the frequency dividing circuit is respectively connected with the second input end of the first AND gate and the second input end of the second AND gate; the output end of the first AND gate is connected with the first input end of the downsampling circuit; the output end of the second AND gate is connected with the second input end of the downsampling circuit; the downsampling circuit is used for outputting a first downsampling result signal corresponding to the first detection result signal and a second downsampling result signal corresponding to the second detection result signal.
Optionally, the frequency dividing circuit is a frequency dividing circuit.
Optionally, the energy storage is a capacitor.
The data recovery circuit based on the delay phase-locked loop comprises a main loop and a compensation branch circuit; the main loop includes: a phase detector for detecting a phase difference between the data signal and the clock signal and outputting a corresponding detection result signal and down-sampling result signal; the downsampling result signal is generated by the downsampling process of the detection result signal; a charge pump connected to the phase detector for generating and outputting a current signal corresponding to the detection result signal; the energy accumulator is connected with the charge pump and is used for generating and outputting a voltage signal corresponding to the current signal; a phase interpolator connected to the energy storage device, for generating and outputting a clock adjustment signal corresponding to the voltage signal to the phase detector, so as to adjust the phase of the clock signal, so that the clock signal is phase-matched with the data signal; the input end of the compensation branch is connected with the phase detector, and the output end of the compensation branch is connected with the charge pump and is used for outputting corresponding compensation current according to the downsampling result signal so as to perform current compensation on the charge pump.
Therefore, the application utilizes analog devices such as a charge pump and the like to construct a main loop of the delay phase-locked loop, avoids the limitation of digital devices on circuit bandwidth, and can effectively improve the tracking performance of a data recovery circuit on high-frequency jitter; meanwhile, the application also provides a compensation branch circuit for carrying out current compensation on the charge pump, which can solve the problem of mismatch of a current mirror in the charge pump, further can avoid the occurrence of offset condition of sampling points of clock signals when high-frequency jitter is input, effectively reduces the error rate and improves the accuracy. Therefore, the application can effectively improve the high-frequency jitter tolerance of the data recovery circuit.
Drawings
In order to more clearly illustrate the technical solutions in the prior art and the embodiments of the present application, the following will briefly describe the drawings that need to be used in the description of the prior art and the embodiments of the present application. Of course, the following drawings related to embodiments of the present application are only a part of embodiments of the present application, and it will be obvious to those skilled in the art that other drawings can be obtained from the provided drawings without any inventive effort, and the obtained other drawings also fall within the scope of the present application.
FIG. 1 is a circuit diagram of a delay locked loop-based data recovery circuit in the prior art;
FIG. 2 is a circuit diagram of a delay locked loop-based data recovery circuit according to another prior art;
Fig. 3 is a circuit configuration diagram of a data recovery circuit based on a delay locked loop according to an embodiment of the present application;
FIG. 4 is a circuit diagram of a charge pump according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a sine jittered input signal according to an embodiment of the present application;
FIG. 6 is a circuit diagram of a phase detector according to an embodiment of the present application;
FIG. 7 is an eye diagram of a data recovery circuit before current compensation according to an embodiment of the present application;
Fig. 8 is an eye diagram of a data recovery circuit according to an embodiment of the present application after current compensation.
Detailed Description
The application aims at providing a data recovery circuit based on a delay phase-locked loop so as to effectively expand the range of the bandwidth to improve the tracking performance of the data recovery circuit on high-frequency jitter while solving the problem of mismatch of a current mirror and reducing the error rate.
In order to more clearly and completely describe the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Currently, the biggest problem in the data recovery circuit based on analog bang-bang DLL in the prior art is the mismatch problem of the current mirror of the charge pump, and when the mismatch of the current mirror can cause input high-frequency jitter, the sampling point of the clock shifts, so that error data is acquired, and the error rate is increased. In the prior art, the digital DLL data recovery circuit replaces a charge pump with a shift register and a digital-to-analog converter, and the problem of mismatch of a current mirror of the charge pump can be fundamentally eliminated, but the speed of the digital DLL is limited by the speeds of the shift register and the DAC, so that the bandwidth cannot be increased, and the tracking performance of high-frequency jitter is affected. In view of the above, the present application provides a delay locked loop-based data recovery circuit, which can effectively solve the above-mentioned problems.
Referring to fig. 3, the embodiment of the application discloses a data recovery circuit based on a delay locked loop, which comprises a main loop and a compensation branch; the main loop includes:
A Phase Detector (PD) 101 for detecting a Phase difference between the data signal and the clock signal and outputting a corresponding detection result signal and a down-sampling result signal; the down-sampling result signal is generated by the down-sampling processing of the detection result signal;
a Charge Pump (CP) 102 connected to the phase detector 101, for generating and outputting a current signal corresponding to the detection result signal;
An accumulator 103 connected to the charge pump 102 for generating and outputting a voltage signal corresponding to the current signal;
a phase interpolator (Phase interpolator, PI) 104 connected to the accumulator 103 for generating and outputting a clock adjustment signal corresponding to the voltage signal to the phase detector 101 so as to adjust the phase of the clock signal to match the phase of the clock signal with the phase of the data signal;
The input end of the compensation branch is connected with the phase detector 101, and the output end of the compensation branch is connected with the charge pump 102 and is used for outputting corresponding compensation current according to the down-sampling result signal so as to perform current compensation on the charge pump 102.
It should be noted that, in the data recovery circuit based on the delay locked loop, i.e. the DLL, provided by the embodiment of the present application, the analog device charge pump 102 is adopted in the main loop of the delay locked loop, and the limitation of the circuit bandwidth is effectively avoided by avoiding the use of the digital device (mainly the digital-to-analog converter 202), so that the tracking performance of the data recovery circuit on the high-frequency jitter can be effectively improved. In addition, in view of the fact that the charge pump 102 is used in the main loop, the data recovery circuit provided by the embodiment of the application is further provided with the compensation branch circuit, so that corresponding compensation current is provided to the charge pump 102 by the compensation branch circuit, the problem of mismatch of a current mirror in the charge pump 102 is solved, and the situation that sampling points of clock signals deviate when high-frequency jitter is input is avoided.
Specifically, the phase detector 101 detects a phase difference of the data signal and the clock signal, and the output detection result signal includes a first detection result signal dn and a second detection result signal up: if the clock signal is lagged, the first detection result signal dn is 0, and the second detection result signal up is 1; if the clock signal is advanced, the first detection result signal dn is 1 and the second detection result signal up is 0.
By using the charge pump 102 and the accumulator 103, a voltage signal lfv corresponding to the detection result signal can be output to the phase interpolator 104. Phase interpolator 104 converts voltage signal lfv to phase lead and lag information for the clock signal, outputting a clock adjustment signal to phase detector 101, thereby allowing the clock signal to follow and lock on the data signal. Wherein the clock adjustment signal comprises ci, cib, cq, cqb signals.
The output signal of the phase detector 101 comprises a down-sampling result signal in addition to the first detection result signal dn and the second detection result signal up described above. Specifically, the down-sampling result signal includes a first down-sampling result signal dn_down obtained after down-sampling the first detection result signal dn, and a second down-sampling result signal up_down obtained after down-sampling the second detection result signal up.
The data recovery circuit based on the delay phase-locked loop provided by the embodiment of the application comprises a main loop and a compensation branch; the main loop includes: a phase detector 101 for detecting a phase difference between the data signal and the clock signal and outputting a corresponding detection result signal and down-sampling result signal; the down-sampling result signal is generated by the down-sampling processing of the detection result signal; a charge pump 102 connected to the phase detector 101 for generating and outputting a current signal corresponding to the detection result signal; an accumulator 103 connected to the charge pump 102 for generating and outputting a voltage signal corresponding to the current signal; a phase interpolator 104 connected to the energy storage 103 for generating and outputting a clock adjustment signal corresponding to the voltage signal to the phase detector 101 so as to adjust the phase of the clock signal to match the phase of the clock signal with the phase of the data signal; the input end of the compensation branch is connected with the phase detector 101, and the output end of the compensation branch is connected with the charge pump 102 and is used for outputting corresponding compensation current according to the down-sampling result signal so as to perform current compensation on the charge pump 102.
Therefore, the application utilizes analog devices such as the charge pump 102 and the like to construct a main loop of the delay phase-locked loop, avoids the limitation of digital devices on circuit bandwidth, and can effectively improve the tracking performance of a data recovery circuit on high-frequency jitter; meanwhile, the application also provides a compensation branch circuit for carrying out current compensation on the charge pump 102, so that the problem of mismatch of a current mirror in the charge pump 102 can be solved, further, the occurrence of the offset condition of a clock signal sampling point can be avoided when high-frequency jitter is input, the error rate is effectively reduced, and the accuracy is improved. Therefore, the application can effectively improve the high-frequency jitter tolerance of the data recovery circuit.
Referring to fig. 4, an embodiment of the present application discloses a circuit structure of a charge pump 102, which includes a first current source Idn, a second current source Iup, a first switch S1, and a second switch S2;
The input end of the second current source Iup is connected with a power supply; the output end of the second current source Iup is connected with the first end of the second switch S2 and the output end of the compensation branch; the second end of the second switch S2 is connected to the first end of the first switch S1 and is used as the output end of the charge pump 102; the second end of the first switch S1 is connected with the input end of the first current source Idn; the output end of the first current source Idn is grounded;
The detection result signals comprise a first detection result signal dn and a second detection result signal up; the first detection result signal dn is used for controlling the on-off of the first switch S1; the second detection result signal up is used for controlling the on-off of the second switch S2.
It should be noted that Ic in fig. 4 is the compensation current provided by the compensation branch.
Wherein the first current source Idn and the second current source Iup may be specifically mirrored current sources. Further, the energy storage 103 connected to the charge pump 102 may be specifically a capacitor C.
It will be readily appreciated that the capacitor C is used in conjunction with the charge pump 102 to output the voltage signal lfv: the current signal output by the charge pump 102 can charge and discharge the capacitor C. Specifically, when the first detection result signal dn is 1, the first switch S1 is closed, the second switch S2 is opened, and the capacitor C is discharged through the first current source Idn; when the second detection result signal up is 1, the second switch S2 is turned on, the first switch S1 is turned off, and the second current source Iup charges the capacitor C.
Based on the above, in the delay locked loop-based data recovery circuit provided by the embodiment of the present application, as a specific implementation manner, the compensation branch may include an Accumulator (ACC) 201, a digital-to-analog converter (DAC) 202, and a voltage-to-current converter (VtoI) 203 connected in sequence;
the input of the accumulator 201 is connected to the phase detector 101; the output of the voltage-to-current converter 203 is connected to the charge pump 102.
Specifically, in the case of the main loop, to maintain the voltage signal lfv at a fixed voltage value, the number of charges and discharges to the capacitor C in a certain period must be equal, that is, nup Iup and Ndn Idn are equal. Where Nup is the number of occurrences of the mirror current Iup and Ndn is the number of occurrences of the mirror current Idn.
The current mirror mismatch, i.e., iup and Idn, are not completely mirrored, and are not equal in size. Assuming iup=0.5 Idn, nup=2×ndn needs to be established to maintain voltage signal lfv unchanged in order to maintain equality. Nup and Ndn can be approximated as samples of the sine jitter if the input data has the sine jitter.
Referring to fig. 5, fig. 5 is a schematic diagram of a sine jitter input signal according to an embodiment of the present application. The increase in Nup increases the response time to input sine jitter, and if the input is high-frequency sine clock jitter, the response time is too long, which results in that the clock signal cannot track the data signal well, and increases the bit error rate. In the compensating branch, as long as Nup and Ndn are different, the value of the accumulator is continuously accumulated or reduced, the corresponding voltage is obtained through the digital-to-analog converter 202, and then the corresponding voltage is converted into the compensating current Ic through the voltage-to-current converter 203, so that ic+iup is equal to Idn. Therefore, nup is equal to Ndn through the main loop, so that the compensation branch and the main loop can work stably finally, current mismatch is guaranteed to be compensated, and the high-frequency jitter tolerance of the data recovery circuit is improved.
Referring to fig. 6, an embodiment of the present application discloses a circuit structure of a phase detector 101, mainly including a first D flip-flop DFF1, a second D flip-flop DFF2, a third D flip-flop DFF3, a fourth D flip-flop DFF4, a first exclusive-or gate xor1, a second exclusive-or gate xor2, a first and gate and1, a second and gate and2, a frequency dividing circuit, and a downsampling circuit (decimator); the third D flip-flop DFF3 is effective at low level, and the rest D flip-flops are effective at high level;
The input end of the first D flip-flop DFF1 is connected to the input end of the third D flip-flop DFF3 and serves as the input end of the phase detector 101; the output end of the first D trigger DFF1 is respectively connected with the input end of the second D trigger DFF2 and the first input end of the first exclusive-OR gate xor 1; the output end of the second D trigger DFF2 is connected with the first input end of the second exclusive-OR gate xor 2;
The output end of the third D trigger DFF3 is connected with the input end of the fourth D trigger DFF 4; the output end of the fourth D trigger DFF4 is respectively connected with the second input end of the first exclusive-OR gate xor1 and the second input end of the second exclusive-OR gate xor 2; the clock ends of the D triggers are connected with each other, serve as the clock end of the phase detector 101, and are connected with the input end of the frequency dividing circuit;
The output end of the first exclusive-OR gate xor1 is used for outputting a first detection result signal dn and is connected with the first input end of the first AND gate and 1; the output end of the second exclusive-or gate xor2 is used for outputting a second detection result signal up and is connected with the first input end of the second AND gate and 2;
The output end of the frequency dividing circuit is respectively connected with the second input end of the first AND gate and1 and the second input end of the second AND gate and 2; the output end of the first AND gate and1 is connected with the first input end of the downsampling circuit; the output end of the second AND gate and2 is connected with the second input end of the downsampling circuit; the downsampling circuit is configured to output a first downsampling result signal dn_down corresponding to the first detection result signal dn and a second downsampling result signal up_down corresponding to the second detection result signal up.
Wherein the phase detector 101 is a bang-bang based full-rate phase detector 101, and the first detection result signal dn and the second detection result signal up are reduced by decimator circuits to provide a moderate speed for the accumulator 201 and the digital-to-analog converter 202.
Further, the frequency dividing circuit may be specifically a frequency dividing circuit.
Referring to fig. 7 and 8, fig. 7 is an eye diagram of a data recovery circuit provided by an embodiment of the present application before current compensation is performed; fig. 8 is an eye diagram of the data recovery circuit after current compensation according to an embodiment of the present application.
The input data rate of the data signal is 5.94Gb/s, the input sine clock jitter is 1UI@10MHz, and the current mismatch condition is iup=0.5 Idn. It can be seen that, in fig. 7, due to the current mirror mismatch problem, the sampling point of the clock is not coincident with the center position of the data; in fig. 8, the sampling point of the clock is located at the center of the data, and the Iup current after compensation is increased, so that the bandwidth response is increased, and Peak-Peak Jitter is reduced from 72ps to 52ps before compensation. It can be seen that the present application can effectively improve the high frequency jitter tolerance of the bang-bang DLL based data recovery circuit.
In the application, each embodiment is described in a progressive manner, and each embodiment is mainly used for illustrating the difference from other embodiments, and the same similar parts among the embodiments are mutually referred. For the apparatus disclosed in the examples, since it corresponds to the method disclosed in the examples, the description is relatively simple, and the relevant points are referred to in the description of the method section.
It should also be noted that in this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The technical scheme provided by the application is described in detail. The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to facilitate an understanding of the method of the present application and its core ideas. It should be noted that it will be apparent to those skilled in the art that the present application may be modified and practiced without departing from the spirit of the present application.
Claims (5)
1. The data recovery circuit based on the delay phase-locked loop is characterized by comprising a main loop and a compensation branch; the main loop includes:
a phase detector for detecting a phase difference between the data signal and the clock signal and outputting a corresponding detection result signal and down-sampling result signal; the downsampling result signal is generated by the downsampling process of the detection result signal;
a charge pump connected to the phase detector for generating and outputting a current signal corresponding to the detection result signal;
the energy accumulator is connected with the charge pump and is used for generating and outputting a voltage signal corresponding to the current signal;
A phase interpolator connected to the energy storage device, for generating and outputting a clock adjustment signal corresponding to the voltage signal to the phase detector, so as to adjust the phase of the clock signal, so that the clock signal is phase-matched with the data signal;
The input end of the compensation branch is connected with the phase detector, and the output end of the compensation branch is connected with the charge pump and is used for outputting corresponding compensation current according to the downsampling result signal so as to perform current compensation on the charge pump;
the compensation branch circuit comprises an accumulator, a digital-to-analog converter and a voltage-current converter which are sequentially connected;
the input end of the accumulator is connected with the phase detector; the output end of the voltage-current converter is connected with the charge pump.
2. The delay locked loop based data recovery circuit of claim 1, wherein the charge pump comprises a first current source, a second current source, a first switch, a second switch;
the input end of the second current source is connected with a power supply; the output end of the second current source is connected with the first end of the second switch and the output end of the compensation branch; the second end of the second switch is connected with the first end of the first switch and is used as the output end of the charge pump; the second end of the first switch is connected with the input end of the first current source; the output end of the first current source is grounded;
The detection result signals comprise a first detection result signal and a second detection result signal; the first detection result signal is used for controlling the on-off of the first switch; the second detection result signal is used for controlling the on-off of the second switch.
3. The delay locked loop based data recovery circuit of claim 2, wherein the phase detector comprises a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, a first exclusive-or gate, a second exclusive-or gate, a first and gate, a second and gate, a frequency divider circuit, and a downsampling circuit; the third D flip-flop is effective at low level, and the rest D flip-flops are effective at high level;
the input end of the first D trigger is connected with the input end of the third D trigger and is used as the input end of the phase detector; the output end of the first D trigger is respectively connected with the input end of the second D trigger and the first input end of the first exclusive-OR gate; the output end of the second D trigger is connected with the first input end of the second exclusive-OR gate;
The output end of the third D trigger is connected with the input end of the fourth D trigger; the output end of the fourth D trigger is respectively connected with the second input end of the first exclusive-OR gate and the second input end of the second exclusive-OR gate; the clock ends of the D triggers are connected with each other, serve as the clock end of the phase detector and are connected with the input end of the frequency dividing circuit;
the output end of the first exclusive-or gate is used for outputting the first detection result signal and is connected with the first input end of the first AND gate; the output end of the second exclusive-or gate is used for outputting the second detection result signal and is connected with the first input end of the second AND gate;
The output end of the frequency dividing circuit is respectively connected with the second input end of the first AND gate and the second input end of the second AND gate; the output end of the first AND gate is connected with the first input end of the downsampling circuit; the output end of the second AND gate is connected with the second input end of the downsampling circuit; the downsampling circuit is used for outputting a first downsampling result signal corresponding to the first detection result signal and a second downsampling result signal corresponding to the second detection result signal.
4. A delay locked loop based data recovery circuit as claimed in claim 3, wherein the frequency dividing circuit is a divide-by-two circuit.
5. A delay locked loop based data recovery circuit as claimed in any one of claims 1 to 4, wherein the energy store is a capacitor.
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| KR20000008299A (en) * | 1998-07-11 | 2000-02-07 | 윤종용 | Up/down mismatch compensation circuit of phase locked loop circuit |
| CN101826869A (en) * | 2009-12-29 | 2010-09-08 | 国民技术股份有限公司 | Phaselocked loop circuit comprising double current source charge pump and double comparator reset circuit |
| CN103929174A (en) * | 2013-01-15 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Phase-locked loop circuit |
| CN105703767A (en) * | 2016-01-13 | 2016-06-22 | 中国科学技术大学先进技术研究院 | High-energy-efficiency low-jitter single loop clock data recovery circuit |
| CN109194327A (en) * | 2018-08-31 | 2019-01-11 | 重庆邮电大学 | A kind of charge pump circuit of the low mismatch ratio for delay phase-locked loop |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000008299A (en) * | 1998-07-11 | 2000-02-07 | 윤종용 | Up/down mismatch compensation circuit of phase locked loop circuit |
| CN101826869A (en) * | 2009-12-29 | 2010-09-08 | 国民技术股份有限公司 | Phaselocked loop circuit comprising double current source charge pump and double comparator reset circuit |
| CN103929174A (en) * | 2013-01-15 | 2014-07-16 | 中芯国际集成电路制造(上海)有限公司 | Phase-locked loop circuit |
| CN105703767A (en) * | 2016-01-13 | 2016-06-22 | 中国科学技术大学先进技术研究院 | High-energy-efficiency low-jitter single loop clock data recovery circuit |
| CN109194327A (en) * | 2018-08-31 | 2019-01-11 | 重庆邮电大学 | A kind of charge pump circuit of the low mismatch ratio for delay phase-locked loop |
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