CN111277263B - Clock data recovery circuit and serial interface circuit - Google Patents
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Abstract
A clock data recovery circuit, a serial interface circuit, the clock data recovery circuit comprising: the phase detector receives an external signal and a recovered clock signal from the first recovery sub-circuit to generate a phase difference signal and a data signal, the charge pump generates a voltage difference signal according to the phase difference signal, the first recovery sub-circuit generates the recovered clock signal according to the voltage difference signal, and the second recovery sub-circuit adjusts the phase of the data signal according to the voltage difference signal and outputs a recovered data signal; the phase detector, the charge pump and the first recovery subcircuit form a first branch, one of the phase detector, the charge pump and the second recovery subcircuit forms a second branch based on a delay phase-locked loop, and the other is based on a phase-locked loop. According to the scheme provided by the application, the generation of error code bits is reduced.
Description
Technical Field
The present disclosure relates to electronic technology, and more particularly, to a clock data recovery circuit and a serial interface circuit.
Background
At present, serial interfaces (SerDes) are adopted as high-speed interfaces for data transmission, and the reason is that the problems of data Skew (Skew), interference (Crosstalk) and the like in parallel interfaces can be well solved. In theory, the serial interface is easier to raise the upper speed limit, so long as the receiving end can better recover the clock and the data of the transmitting end. The circuit for realizing this function is clock data recovery (Clock and Data Recovery, CDR for short), so the quality of CDR design directly affects the performance of the interface, which is a very important ring of the whole SerDes interface.
The multiple SerDes interfaces typically employ a method of providing a CDR circuit separately for each lane, i.e., each lane (lane) recovers its own clock and data. The recovered data generally causes skew due to the layout of the individual lanes on the flat cable, etc. At this time, a De-skew circuit needs to be added at the back end to eliminate the data skew between each lane, and finally, a synchronization (sync) circuit is used to synchronize the clock signals of each lane. The specific signal flow is shown in fig. 1 a.
FIG. 1a shows the CDR module arrangement and architecture design currently used for multi-way SerDes high speed interface data transfer. Taking Gen3 PCIe of 2 lanes as an example, 101 in fig. 1a is a differential transmitter (Differential transmitter) of lane 0 at the transmitting end of chip a; 102 is a link between Lane 0 transceivers; 103 is a differential receiver (Differential receiver) of Lane 0 at the receiving end, which receives a single bit (bit) data_0 from the link; reference numeral 104 denotes a memory unit (illustrated as a register) for storing clock and data recovered by the CDR; 105 is shown as a flexible buffer, which is essentially a large FIFO (First Input First Output, first in first out), driven by the local clock at the receiving end; 106 is a link data skew delay circuit (lane data de-skew delay circuit) for eliminating skew caused by data transfers between PCIe lanes; reference numeral 107 denotes a CDR circuit, which includes a clock recovery circuit (Clock Recovery Circuit, abbreviated as CRC) and a data recovery circuit (Data Recovery Circuit, abbreviated as DRC), wherein the CRC is used to recover a clock embedded in a data stream transmitted from a transmitting end, and the DRC is used to recover the data of the transmitting end according to the recovered clock sampling data. The CDR directly extracts the clock signal from the received signal pulse and uses it to reconstruct the signal pulse. The sampling limit is reached when the clock is too far (too early or too late) from the sampling optimum (i.e., the eye opening angle maximum point, which coincides approximately with the middle point of the signal transition). Errors, i.e. eye cross errors, occur when the distance of the actual sampling point from the central sampling point exceeds the sampling limit (Lateral Eye Opening) 
The bit error can be used as a criterion that the sampling tolerance limit has been reached (even if it occurs sporadically in a small data stream, it marks a periodic phase error due to sinusoidal oscillation). The waveforms of the data and clock before and after the CDR circuit is recovered are shown in fig. 1b, and Error bits (Error-ed bits) due to phase errors can be clearly seen in fig. 1 b.
CDR circuits adopted by the conventional multipath high-speed SerDes interface are mainly divided into two types, one based on a phase-locked loop (Phase Locked Loop, PLL for short) and the other based on a delay-locked loop (Delay Locked Loop, DLL for short). Two major problems are faced in this case:
a) If a DLL circuit is adopted, jitter of a reference clock (Ref_Clk) is transferred along with the circuit, so that the jitter is difficult to eliminate;
b) If PLL circuits are used, it is difficult to avoid errors due to phase errors, which may cause data recovery errors in severe cases.
Disclosure of Invention
The application provides a clock data recovery circuit and a serial interface circuit, which can reduce jitter of a recovered data clock signal and reduce probability of error bit generation.
An embodiment of the present application provides a clock data recovery circuit, including: the phase detector comprises a first output end and a second output end, wherein the first output end of the phase detector is connected to the input end of the charge pump, the second output end of the phase detector is connected to the first input end of the second recovery sub-circuit, and the output end of the charge pump is connected to the input end of the first recovery sub-circuit and the second input end of the second recovery sub-circuit, and the phase detector comprises:
The phase discriminator is used for receiving an external signal and a recovered clock signal from the first recovery sub-circuit to generate a phase difference signal and a data signal, outputting the phase difference signal through the first output end and outputting the data signal through the second output end;
the charge pump is used for generating a voltage difference signal according to the phase difference signal and outputting the voltage difference signal to the first recovery sub-circuit and the second recovery sub-circuit;
the first recovery sub-circuit is used for generating the recovery clock signal according to the voltage difference signal and feeding back the recovery clock signal to the phase discriminator;
the second recovery sub-circuit is used for receiving the data signal output by the phase discriminator and the voltage difference signal output by the charge pump, adjusting the phase of the data signal according to the voltage difference signal and outputting a recovered data signal;
the phase detector, the charge pump and the first recovery subcircuit form a first branch, one of the phase detector, the charge pump and the second recovery subcircuit forms a second branch based on a delay phase-locked loop, and the other is based on a phase-locked loop.
In an embodiment, the first recovery sub-circuit includes: the input end of the first loop filter is connected to the output end of the charging pump, the output end of the first loop filter is connected to the input end of the first voltage-controlled oscillator, and the output end of the first voltage-controlled oscillator serves as the output end of the first recovery subcircuit.
In an embodiment, the second recovery sub-circuit includes: the second loop filter and the first synchronization sub-circuit, the first synchronization sub-circuit includes first input and second input, the second output of phase discriminator is connected to the first input of first synchronization sub-circuit, the input of second loop filter is connected to the output of charge pump, the output of second loop filter is connected to the second input of first synchronization sub-circuit, the second loop filter is used for filtering voltage difference signal, output second phase adjustment signal to first synchronization sub-circuit, first synchronization sub-circuit is used for delaying the data signal received from the phase discriminator according to the second phase adjustment signal, output data signal after recovering.
In an embodiment, the first synchronization sub-circuit is implemented based on at least one of: delay line, first-in first-out memory, shift register.
In an embodiment, the first recovery sub-circuit includes: the input end of the third loop filter is connected to the output end of the charging pump, the output end of the third loop filter is connected to the input end of the second synchronous subcircuit, the output end of the second synchronous subcircuit is used as the output end of the first recovery subcircuit, the third loop filter is used for filtering the voltage difference signal and outputting a first phase adjustment signal to the second synchronous subcircuit, and the second synchronous subcircuit is used for delaying the phase of the last outputted recovery clock signal according to the first phase adjustment signal and then outputting the recovery clock signal.
In an embodiment, the second recovery sub-circuit includes: the fourth loop filter, second voltage controlled oscillator and register unit, the register unit includes first input and second input, the second output of phase discriminator is connected to the first input of register unit, the input of fourth loop filter is connected to the output of charge pump, the output of fourth loop filter is connected to the input of second voltage controlled oscillator, the output of second voltage controlled oscillator is connected to the second input of register unit, wherein:
the fourth loop filter is configured to filter the voltage difference signal, and output the filtered voltage difference signal to the second voltage-controlled oscillator;
the second voltage-controlled oscillator is used for generating a clock signal according to the filtered voltage difference signal and outputting the clock signal to the register unit;
the register unit is used for delaying the data signal received from the phase discriminator according to the clock signal and outputting the recovered data signal.
In an embodiment, the second synchronization sub-circuit is implemented based on at least one of: delay line, first-in first-out memory, shift register.
At least one embodiment of the present invention provides a serial interface circuit, including the clock data recovery circuit.
Compared with the related art, the clock data recovery circuit is included in the present application, and the jitter and phase error of the recovered data clock Signal can be obviously reduced by the scheme provided by the present embodiment, so as to improve the data accuracy (Signal Integrity) of CDR recovery.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1a is a schematic diagram of a clock data recovery circuit in the related art;
FIG. 1b is a schematic diagram of the circuit signal shown in FIG. 1 a;
FIG. 2 is a schematic diagram of a delay locked loop circuit;
FIG. 3 is a schematic diagram of a phase locked loop circuit;
FIG. 4 is a schematic diagram of a clock data recovery circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a first recovery sub-circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a first recovery sub-circuit according to another embodiment of the present invention;
FIG. 7 is a schematic diagram of a clock data recovery circuit according to another embodiment of the present invention;
FIG. 8 is a schematic diagram of a second recovery sub-circuit according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a second recovery sub-circuit according to another embodiment of the present invention;
FIG. 10a is a schematic diagram of a clock data recovery circuit according to an embodiment of the present invention;
FIG. 10b is a signal diagram of the circuit shown in FIG. 10 a;
FIG. 11 is a schematic diagram of a clock data recovery circuit according to another embodiment of the present invention;
FIG. 12 is a schematic diagram of a clock data recovery circuit according to an embodiment of the present invention;
FIG. 13 is a schematic diagram of a clock data recovery circuit according to an embodiment of the present invention;
FIG. 14 is a schematic diagram of a clock data recovery circuit according to another embodiment of the present invention;
FIG. 15a is a schematic diagram of a clock data recovery circuit according to another embodiment of the present invention;
fig. 15b is a signal diagram of the circuit shown in fig. 15 a.
Detailed Description
The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
CDR circuits are largely divided into two architectures, PLL and DLL architectures. The DLL function module is shown in fig. 2, and includes: the phase detector 201, the charge pump 202, the loop filter 203 and the delay circuit 204 are sequentially connected, wherein the output of the delay circuit 204 is used as one input of the phase detector, and the phase detector 201 compares the input serial data with a clock fed back and transmits error information to the charge pump 202; the charge pump 202 automatically adjusts the phase of the locally generated signal to match the phase of the input; a loop filter 203, typically a low-pass filter, for filtering noise or impurity signals; the delay circuit 204 corrects the phase of the recovered clock based on feedback.
PLL functional module as shown in fig. 3, it can be found that the PLL is similar to the DLL in terms of functional module division, except for the correction unit, the PLL uses an analog voltage-controlled oscillator (Voltage Controlled Oscillator, VCO) 301, which is mainly used to adjust the recovered clock phase according to the voltage correction signal generated by the previous module.
In one embodiment of the present invention, the clock recovered from the serial signal at the receiving end uses a PLL architecture, and the recovered data uses a DLL architecture. Finally, the data is knocked out by the clock recovered by the former, so that error code bits caused by phase errors generated by the PLL architecture are avoided.
As shown in fig. 4, an embodiment of the present invention provides a clock data recovery circuit, including: at least one receiver 401, at least one phase detector 402, a phase difference generating sub-circuit 403, a charge pump 404 and a first recovery sub-circuit 405, wherein the receiver 401, the phase detector 402 are in one-to-one correspondence with links, the phase detector 402 is connected to its corresponding receiver 401, the phase detector 402 comprises a first output OP and a second output OD, the first output OP of the phase detector is connected to the phase difference generating sub-circuit 403, the output of the phase difference generating sub-circuit 403 is connected to the input of the charge pump 404, and the output of the charge pump 404 is connected to the first recovery sub-circuit 405, wherein:
the receiver 401 is configured to receive a corresponding link input signal, amplify the link input signal, and output the amplified link input signal to the phase detector 402;
the phase detector 402 is configured to generate a phase difference signal and a data signal according to the signal from the receiver 401 and the recovered clock signal from the first recovered subcircuit 405, output the phase difference signal through the first output terminal OP, and output the data signal through the second output terminal OD;
The phase difference generating sub-circuit 403 is configured to generate a final phase difference signal according to the phase difference signal input by each phase detector 402, and output the final phase difference signal to the charge pump 404;
the charge pump 404 is configured to generate a voltage difference signal according to the final phase difference signal, and output the voltage difference signal to the first recovery sub-circuit 405;
the first recovery sub-circuit 405 is configured to generate the recovery clock signal according to the voltage difference signal, and feed back the recovery clock signal to the phase detector 402.
According to the scheme provided by the embodiment, a plurality of phase difference signals are synthesized into one phase difference signal, only one clock is recovered, and the power consumption is greatly reduced due to the reduction of the clocks; under the condition that only one clock sampling data is recovered, the generation of skew between the Lane is avoided, and therefore the necessity of a de-skew circuit is avoided; in addition, compared with the implementation mode that each link in the related art needs one CDR, in the application, each link multiplexes the charge pump and the first recovery sub-circuit, so that the area of the logic circuit is greatly reduced, and the more signal channels at the receiving end, the more remarkable the effect.
In one embodiment, the phase difference generating sub-circuit 403 generates a final phase difference signal according to the phase difference signal input by each phase detector, including: the phase difference generating sub-circuit 403 weights and sums the phase difference signals input from the phase detectors 402, respectively, to obtain the final phase difference signal. The phase difference generating sub-circuit 403 is, for example, a function generator.
The function generator can be designed according to actual needs, and if the example is an N-way high-speed interface, then
Wherein, the liquid crystal display device comprises a liquid crystal display device,
for Link i-1 (Link) i-1 ) Phase difference, W i-1 Is Link i-1 The value of the Weight (Weight) parameter i=1, …, N may be determined according to the signal delay of the link, in general, the smaller the delay is, the smaller the Weight is, the value may be stored in a register, so as to be convenient to modify according to actual requirements, and it should be noted that the Weight parameter of each link may be fixed in another embodiment, which is only an example.
The first recovery sub-circuit 405 may be implemented using a loop filter, such as a low pass filter, and a voltage controlled oscillator, or using a loop filter and a synchronization sub-circuit. The voltage controlled oscillator may be an analog Voltage Controlled Oscillator (VCO) or a digital voltage controlled oscillator (Digital Control Oscillator, DCO for short). The synchronous sub-circuit is a sub-circuit for realizing signal Delay, and can be realized through a Delay Line (Delay Line), a FIFO memory or a Shift register (Shift register). A delay line is a series of voltage or current controlled buffers (buffers) in series forming a delay chain whose output signal is the phase delayed input signal.
In one embodiment, as shown in fig. 5, the first recovery sub-circuit 405 includes: a first loop filter 4051 and a first voltage controlled oscillator 4052, wherein an input terminal of the first loop filter 4051 is connected to an output terminal of the charge pump 404, an output terminal of the first loop filter 4051 is connected to an input terminal of the first voltage controlled oscillator 4052, and an output terminal of the first voltage controlled oscillator 4052 serves as an output terminal of the first recovery sub-circuit 405. The first loop filter 4051 filters the voltage difference signal from the charge pump 404 and outputs the filtered voltage difference signal to the first voltage controlled oscillator 4052, and the first voltage controlled oscillator 4052 generates a recovered clock signal based on the filtered voltage difference signal.
In one embodiment, as shown in fig. 6, the first recovery sub-circuit 405 includes: a third loop filter 4053 and a second synchronization sub-circuit 4054, wherein an input end of the third loop filter 4053 is connected to an output end of the charge pump 404, an output end of the third loop filter 4053 is connected to an input end of the second synchronization sub-circuit 4054, an output end of the second synchronization sub-circuit 4054 is used as an output end of the first recovery sub-circuit 405, the third loop filter 4053 is used for filtering the voltage difference signal, outputting a first phase adjustment signal, and the second synchronization sub-circuit 4054 is used for delaying a phase of a recovery clock signal outputted last time according to the first phase adjustment signal and outputting a recovery clock signal.
Wherein the second synchronization sub-circuit 4054 is implemented based on at least one of: delay line, first-in first-out memory, shift register.
Both the DLL and the PLL have advantages and disadvantages, wherein the DLL is characterized as follows:
a) The clock is easier to stabilize;
b) Jitter of the reference clock (Ref_Clk) is transferred along with the circuit, and is difficult to eliminate;
c) There is no phase error accumulation.
The PLL is characterized as follows:
a) It is harder to stabilize the clock;
b) Jitter of the reference clock is filtered out;
c) There is a phase error accumulation.
Therefore, in an embodiment of the present application, the Dual loop (Dual loop) mode is adopted, and the advantages of the two CDR circuits are combined to realize optimization. As shown in fig. 7, an embodiment of the present invention provides a clock data recovery circuit, and compared with the circuit shown in fig. 4, in this embodiment, the clock data recovery circuit further includes a second recovery sub-circuit 409, where the second recovery sub-circuit 409 is connected to the second output end OD of the phase detector 402 and the output end of the charge pump 404, and the second recovery sub-circuit 409 is configured to receive a data signal output by the phase detector 402 and a voltage difference signal output by the charge pump 404, adjust a phase of the data signal according to the voltage difference signal, and output a recovered data signal;
Wherein, a first branch circuit formed by the phase detector 402, the phase difference generating sub-circuit 403, the charge pump 404 and the first recovering sub-circuit 405, and a second branch circuit formed by the phase detector 402, the phase difference generating sub-circuit 403, the charge pump 404 and the second recovering sub-circuit 409 is implemented based on a delay phase-locked loop, and the other is implemented based on a phase-locked loop. Specifically, one of the first recovery sub-circuit 405 and the second recovery sub-circuit 409 uses a voltage-controlled oscillator to synchronize phases, and the other uses a synchronization sub-circuit to synchronize phases.
The scheme provided by the embodiment uses a dual-loop design, combines the advantages of the PLL and the DLL circuit, can obviously reduce jitter of the recovered data clock Signal, and improves the data accuracy (Signal Integrity) of CDR recovery.
In one embodiment, as shown in fig. 8, the second recovery sub-circuit 409 includes: the second loop filter 4091 and the first synchronization sub-circuit 4092, the first synchronization sub-circuit 4092 includes a first input terminal and a second input terminal, the second output terminal of the phase detector 402 is connected to the first input terminal of the first synchronization sub-circuit 4092, the input terminal of the second loop filter 4091 is connected to the output terminal of the charge pump 404, the output terminal of the second loop filter 4091 is connected to the second input terminal of the first synchronization sub-circuit 4092, the second loop filter 4091 is configured to filter the voltage difference signal to obtain a second phase adjustment signal, and output the second phase adjustment signal to the first synchronization sub-circuit 4092, and the first synchronization sub-circuit 4092 is configured to delay the data signal received from the phase detector 402 according to the second phase adjustment signal, and output the recovered data signal. Wherein the second loop filter 4091 is, for example, a low pass filter.
In an embodiment, the first synchronization sub-circuit 4092 is implemented based on at least one of: delay line, first-in first-out memory, shift register.
In one embodiment, as shown in fig. 9, the second recovery sub-circuit 409 includes: a fourth loop filter 4093, a second voltage controlled oscillator 4094 and a register unit 4095, said register unit 4095 comprising a first input and a second input, said second output of the phase detector 402 being connected to the first input of said register unit 4095, said input of the fourth loop filter 4093 being connected to the output of the charge pump 404, said output of the fourth loop filter 4093 being connected to the input of the second voltage controlled oscillator 4094, said output of the second voltage controlled oscillator 4094 being connected to the second input of the register unit 4095, wherein:
the fourth loop filter 4093 is configured to filter the voltage difference signal, and output the filtered voltage difference signal to the second voltage-controlled oscillator;
the second voltage controlled oscillator 4094 is configured to generate a clock signal according to the filtered voltage difference signal, and output the clock signal to the register unit 4095;
the register unit 4095 is configured to delay the data signal received from the phase detector 402 according to the clock signal, and output a recovered data signal. The register unit 4095 may include one or more registers.
The present application is further illustrated by one specific example below. Fig. 10a shows a Multi-channel dual-loop CDR circuit (Multi-lane Dual Loop CDR) according to an embodiment of the present invention, which is further provided with a function generator 403 (i.e. phase difference generating sub-circuit), a Low Pass Filter (LPF) 608, a set of delay units 609, but is further provided with N-1 sets of charge pumps 404, pll loop filter 605 and voltage controlled oscillator (606) compared to the conventional CDR circuit (fig. 1 a), wherein N represents the number of channels (i.e. the number of links). The second recovery sub-circuit is constituted by the low-pass filter 608 and the delay unit 609, while the loop filter 605 and the voltage-controlled oscillator 606 constitute the first recovery sub-circuit.
The basic operation principle of this embodiment is as follows, assuming that the CDR circuit is used for PCIe 3.0 of 4 lanes, i.e., n=4 (lane 0, lane1, lane2, lane 3). The single bit serial signals (in_a, in_b, in_c, in_d) are amplified by the differential receiver 401 and passed to the phase detector 402. Note that the signal amplified at this time includes not only effective information such as a data clock but also impurity signals such as noise. The phase detector 402 has two inputs: port a receives the serial data stream from the transmitting end and the clock information embedded therein, and port B receives the CDR recovered clock signal clk_rcv. There are two outputs, namely, a Data recovery (OD) and a Phase difference (OP) Output Phase. The phase detector 402 is operative to compare the phase of the input data clock signal with the phase of the feedback CLK RCV and to register data information samples in registers of the phase detector 402. The CDRs are then divided into Clock Recovery Circuits (CRCs) and Data Recovery Circuits (DRCs) based on the different properties of the OP-side and OD-side signals.
The signal from the OP terminal goes to the CRC circuit, part 407, which takes the PLL configuration. The phase detector of 4 lanes recognizes the phase difference of the data clock signals on the respective lanes and then outputs the phase difference to the function generator 403. The function generator 403 calculates the phase difference Φe closest to clk_rcv according to the weight of each path by a preset algorithm, and outputs the calculated phase difference Φe to the charge pump 404. Charge pump 404, upon receiving Φe, generates a voltage signal matching the Φe phase and outputs the voltage signal to loop filter 605. After the voltage passes through the loop filter 605, noise impurities are further reduced, a voltage difference signal Ve reflecting the phase difference Φe is obtained, and the voltage difference signal Ve is output to the voltage-controlled oscillator 606. The voltage difference signal Ve controls the voltage controlled oscillator 606 to adjust the phase difference between clk_rcv and the Receiver (Receiver), and finally recovers the clock signal clk_rcv embedded IN in_ A, IN _ B, IN _c and in_d. Compared with the traditional CDR circuit, the clock signal recovered by the embodiment of the invention is unique and optimal, so that a subsequent signal deviation eliminating (de-skew) circuit is omitted, the area is reduced, and the power consumption is saved.
The signal flowing from the OD terminal goes to the DRC circuit, which is illustrated as a DLL Loop. The voltage signal generated by charge pump 404 that matches the phase of Φe is provided as an input to low pass filter 608 (LPF). The low-pass filter 608 outputs a phase adjustment signal to the delay unit 609 after removing unnecessary Noise (Noise). The delay unit 609 adjusts the phase difference of the DRC recovered DATA data_rcv and the serial input signal according to the phase adjustment signal. The DLL of DRC circuit and the PLL of CRC circuit assist each other, combine the advantage of both, can adjust data and clock that is better than traditional CDR circuit, shake less. Delay cell 609 may include one or more delay lines.
As shown in fig. 10b, the data and clock signals recovered by the embodiment of the present invention can be seen that although the input signal data_0 of the link 0 and the input signal data_1 of the link 1 have skew, since only one clock is recovered after passing through the CDR circuit, the final recovered data and clock have no skew.
Fig. 11 is a schematic diagram of a clock data recovery circuit according to another embodiment of the present invention, in which a CRC circuit using a DLL structure and a DRC circuit using a PLL structure are used. In this embodiment, the loop filter 705 and the voltage controlled delay buffer 706 constitute a first restoration sub-circuit, and the low pass filter 708, the voltage controlled oscillator 709, and the register set 710 constitute a second restoration sub-circuit.
The differential receiver 701 recognizes and amplifies the serial signal sent from the transmitting end, and sends the serial signal to the phase detector 702, and the n-way phase detector 702 sends the phase signal converted by the serial signal as an input to the function generator 703. After the final phase difference Φe is obtained in the function generator 703, the final phase difference Φe is output to the charge pump 704, and the charge pump 704 generates a voltage difference signal reflecting the phase difference Φe according to the final phase difference Φe. In the CRC circuit of the DLL configuration 707, the loop filter 705 filters out unnecessary impurity signals in the voltage difference signal, and then outputs Ve0 to the voltage controlled buffer 706 (VCDL, i.e., voltage Controlled Delay Line, one of the delay lines) to recover the required clock.
Correspondingly, the voltage difference signal generated by the charge pump 704 is also sent to the DRC circuit of the PLL structure. The voltage difference signal generated by the charge pump 704 is filtered by a low pass filter 708 (LPF) to remove impurities, thereby generating a voltage difference signal Ve1. The voltage difference signal Ve1 controls the voltage controlled oscillator 709 to generate a clock signal to the register set 710, and the register set 710 outputs the recovered data signal according to the clock signal. It is noted that the register set 710 may also be implemented as a FIFO.
As shown in fig. 12, an embodiment of the present invention provides a clock data recovery circuit, including: the phase detector 401, the charge pump 404, the first recovery sub-circuit 405 and the second recovery sub-circuit 409, wherein the phase detector 402 includes a first output terminal and a second output terminal, the first output terminal of the phase detector 402 is connected to the input terminal of the charge pump 404, the second output terminal of the phase detector 402 is connected to the first input terminal of the second recovery sub-circuit 409, and the output terminal of the charge pump 404 is connected to the input terminal of the first recovery sub-circuit 405 and the second input terminal of the second recovery sub-circuit 409, wherein:
the phase detector 402 is configured to receive an external signal and a recovered clock signal from the first recovery sub-circuit 405 to generate a phase difference signal and a data signal, output the phase difference signal through the first output terminal, and output the data signal through the second output terminal;
The charge pump 404 is configured to generate a voltage difference signal according to the phase difference signal, and output the voltage difference signal to the first recovery sub-circuit 405 and the second recovery sub-circuit 409;
the first recovery sub-circuit 405 is configured to generate the recovery clock signal according to the voltage difference signal, and feed back the recovery clock signal to the phase detector 402;
the second recovery sub-circuit 409 is configured to receive the data signal output by the phase detector 402 and the voltage difference signal output by the charge pump 404, adjust the phase of the data signal according to the voltage difference signal, and output a recovered data signal;
wherein, a third branch formed by the phase detector 402, the charge pump 404 and the first recovery sub-circuit 405, and a fourth branch formed by the phase detector 402, the charge pump 404 and the second recovery sub-circuit 409 are implemented based on a delay phase-locked loop, and the other is implemented based on a phase-locked loop. Specifically, one of the first recovery sub-circuit 405 and the second recovery sub-circuit 409 uses a voltage-controlled oscillator to synchronize phases, and the other uses a synchronization sub-circuit to synchronize phases. The implementation of the first recovery sub-circuit 405 and the second recovery sub-circuit 409 is referred to the previous embodiments, and will not be repeated here. The synchronization subcircuit may be implemented using at least one of: delay line, first-in first-out memory, shift register.
The scheme provided by the embodiment uses a dual-loop design, combines the advantages of the PLL and the DLL circuit, can obviously reduce jitter of the recovered data clock Signal, and improves the data accuracy (Signal Integrity) of CDR recovery. Unlike the CDR with the conventional single loop structure, when recovering data, the CDR can accumulate phase differences to cause bit errors (data errors in severe cases), and the embodiment can better avoid bit errors by utilizing the characteristic that the DLL loop cannot accumulate phase differences.
As shown in fig. 13, in an embodiment of the present invention, the first recovery sub-circuit 405 is implemented using the circuit shown in fig. 5, and the second recovery sub-circuit 409 is implemented using the circuit shown in fig. 8. The first restoration sub-circuit 405 includes: a first loop filter 4051 and a first voltage controlled oscillator 4052, wherein an input terminal of the first loop filter 4051 is connected to an output terminal of the charge pump 404, an output terminal of the first loop filter 4051 is connected to an input terminal of the first voltage controlled oscillator 4052, and an output terminal of the first voltage controlled oscillator 4052 serves as an output terminal of the first recovery sub-circuit 405. The first loop filter 4051 filters the voltage difference signal from the charge pump 404 and outputs the filtered voltage difference signal to the first voltage controlled oscillator 4052, and the first voltage controlled oscillator 4052 generates a recovered clock signal based on the filtered voltage difference signal.
The second recovery sub-circuit 409 includes: the second loop filter 4091 and the first synchronization sub-circuit 4092, the first synchronization sub-circuit 4092 includes a first input terminal and a second input terminal, the second output terminal of the phase detector 402 is connected to the first input terminal of the first synchronization sub-circuit 4092, the input terminal of the second loop filter 4091 is connected to the output terminal of the charge pump 404, the output terminal of the second loop filter 4091 is connected to the second input terminal of the first synchronization sub-circuit 4092, the second loop filter 4091 is configured to filter the voltage difference signal to obtain a second phase adjustment signal, and output the second phase adjustment signal to the first synchronization sub-circuit 4092, and the first synchronization sub-circuit 4092 is configured to delay the data signal received from the phase detector 402 according to the second phase adjustment signal, and output the recovered data signal. Wherein the second loop filter is for example a low pass filter.
As shown in fig. 14, in an embodiment of the present invention, the first restoration sub-circuit 405 is implemented using the circuit shown in fig. 6, and the second restoration sub-circuit 409 is implemented using the circuit shown in fig. 9.
The first restoration sub-circuit 405 includes: a third loop filter 4053 and a second synchronization sub-circuit 4054, wherein an input end of the third loop filter 4053 is connected to an output end of the charge pump 404, an output end of the third loop filter 4053 is connected to an input end of the second synchronization sub-circuit 4054, an output end of the second synchronization sub-circuit 4054 is used as an output end of the first recovery sub-circuit 405, the third loop filter 4053 is used for filtering the voltage difference signal, outputting a first phase adjustment signal, and the second synchronization sub-circuit 4054 is used for delaying a phase of a recovery clock signal outputted last time according to the first phase adjustment signal and outputting a recovery clock signal.
The second recovery sub-circuit 409 includes: a fourth loop filter 4093, a second voltage controlled oscillator 4094 and a register unit 4095, said register unit 4095 comprising a first input and a second input, said second output of the phase detector 402 being connected to the first input of said register unit 4095, said input of the fourth loop filter 4093 being connected to the output of the charge pump 404, said output of the fourth loop filter 4093 being connected to the input of the second voltage controlled oscillator 4094, said output of the second voltage controlled oscillator 4094 being connected to the second input of the register unit 4095, wherein:
the fourth loop filter 4093 is configured to filter the voltage difference signal, and output the filtered voltage difference signal to the second voltage-controlled oscillator;
the second voltage controlled oscillator 4094 is configured to generate a clock signal according to the filtered voltage difference signal, and output the clock signal to the register unit 4095;
the register unit 4095 is configured to delay the data signal received from the phase detector 402 according to the clock signal, and output a recovered data signal. The register unit 4095 may include one or more registers.
An example is described below.
Fig. 15a shows a dual-loop CDR circuit according to an embodiment of the present invention, in which a loop filter 605 and a voltage-controlled oscillator 606 form a first recovery sub-circuit, and a low-pass filter (LPF) 608 and a voltage-controlled delay line 609 form a second recovery sub-circuit.
The basic working principle of this embodiment is as follows, assuming that the CDR circuit is for PCIe 3.0 of 1 lane. The single bit serial signal (in_a) is amplified by the differential receiver 401 and then transferred to the phase detector 402. Note that the signal amplified at this time includes not only effective information such as a data clock but also impurity signals such as noise. The phase detector 402 has two inputs: port a receives the serial data stream from the transmitting end and the clock information embedded therein, and port B receives the CDR recovered clock signal clk_rcv. There are two outputs, namely, a Data recovery (OD) and a Phase difference (OP) Output Phase. The phase detector 402 is operative to compare the phase of the input data clock signal with the phase of the feedback CLK RCV and to register data information samples in registers of the phase detector 402. The CDRs are then divided into Clock Recovery Circuits (CRCs) and Data Recovery Circuits (DRCs) based on the different properties of the OP-side and OD-side signals.
The signal flowing from the OP terminal is directed to a CRC circuit, part 406, which takes the form of a PLL. The phase detector recognizes the phase difference Φe of the data clock signals and outputs the phase difference Φe to the charge pump 404. The charge pump 404 generates a voltage signal matching the phase difference Φe, and outputs the voltage signal to the loop filter 605. After the voltage signal passes through the loop filter 605, noise impurities are further reduced, a voltage difference signal Ve is obtained, and the voltage difference signal Ve is output to the voltage-controlled oscillator 606. The voltage difference signal Ve may control the voltage controlled oscillator 606, adjust the phase difference between clk_rcv and the Receiver (Receiver), and eventually recover the clock signal clk_rcv embedded IN in_a.
The signal flowing from the OD terminal goes to the DRC circuit, which is illustrated as a DLL Loop. The voltage signal generated by charge pump 404 that matches the phase of Φe is provided as an input to low pass filter 608 (LPF). The low-pass filter 608 outputs a phase adjustment signal to a delay unit 609 (realized using a voltage-controlled delay line in the present embodiment) after removing unnecessary Noise (Noise). The delay unit 609 adjusts the phase difference of the DRC recovered DATA data_rcv and the serial input signal according to the phase adjustment signal. The DLL of DRC circuit and the PLL of CRC circuit assist each other, combine the advantage of both, can adjust data and clock that is better than traditional CDR circuit, shake less.
The data and clock signals recovered by the embodiment of the invention are shown in fig. 15b, and it can be seen that the CDR different from the conventional single loop structure can cause bit errors (the phenomenon of data errors can occur under severe conditions) due to accumulation of phase differences when recovering the data.
An embodiment of the present invention provides a serial interface circuit including a clock data recovery circuit as shown in fig. 12. For example, in one embodiment, the circuit shown in FIG. 8 may be used as a CDR circuit in the circuit shown in FIG. 1 a.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (7)
1. A clock data recovery circuit, comprising: the phase detector comprises a first output end and a second output end, wherein the first output end of the phase detector is connected to the input end of the charge pump, the second output end of the phase detector is connected to the first input end of the second recovery sub-circuit, and the output end of the charge pump is connected to the input end of the first recovery sub-circuit and the second input end of the second recovery sub-circuit, and the phase detector comprises:
the phase discriminator is used for receiving an external signal and a recovered clock signal from the first recovery sub-circuit to generate a phase difference signal and a data signal, outputting the phase difference signal through the first output end and outputting the data signal through the second output end;
the charge pump is used for generating a voltage difference signal according to the phase difference signal and outputting the voltage difference signal to the first recovery sub-circuit and the second recovery sub-circuit;
the first recovery sub-circuit is used for generating the recovery clock signal according to the voltage difference signal and feeding back the recovery clock signal to the phase discriminator;
The second recovery sub-circuit is used for receiving the data signal output by the phase discriminator and the voltage difference signal output by the charge pump, adjusting the phase of the data signal according to the voltage difference signal and outputting a recovered data signal;
wherein one of the first branch circuit formed by the phase detector, the charge pump and the first recovery sub-circuit is realized based on a delay phase-locked loop, the other is realized based on a phase-locked loop,
the second recovery sub-circuit includes: the second loop filter and the first synchronization sub-circuit, the first synchronization sub-circuit includes first input and second input, the second output of phase discriminator is connected to the first input of first synchronization sub-circuit, the input of second loop filter is connected to the output of charge pump, the output of second loop filter is connected to the second input of first synchronization sub-circuit, the second loop filter is used for filtering voltage difference signal, output phase adjustment signal to first synchronization sub-circuit, first synchronization sub-circuit is used for delaying the data signal received from the phase discriminator according to the phase adjustment signal, output data signal after the recovery.
2. The clock data recovery circuit of claim 1, wherein,
the first recovery sub-circuit includes: the input end of the first loop filter is connected to the output end of the charging pump, the output end of the first loop filter is connected to the input end of the first voltage-controlled oscillator, and the output end of the first voltage-controlled oscillator serves as the output end of the first recovery subcircuit.
3. The clock data recovery circuit of claim 1, wherein the first synchronization sub-circuit is implemented based on at least one of: delay line, first-in first-out memory, shift register.
4. The clock data recovery circuit of claim 1 or 2, wherein the first recovery sub-circuit comprises: the input end of the third loop filter is connected to the output end of the charging pump, the output end of the third loop filter is connected to the input end of the second synchronous subcircuit, the output end of the second synchronous subcircuit is used as the output end of the first recovery subcircuit, the third loop filter is used for filtering the voltage difference signal and outputting a first phase adjustment signal to the second synchronous subcircuit, and the second synchronous subcircuit is used for delaying the phase of the last outputted recovery clock signal according to the first phase adjustment signal and then outputting the recovery clock signal.
5. The clock data recovery circuit of claim 4, wherein the second recovery sub-circuit comprises: the fourth loop filter, second voltage controlled oscillator and register unit, the register unit includes first input and second input, the second output of phase discriminator is connected to the first input of register unit, the input of fourth loop filter is connected to the output of charge pump, the output of fourth loop filter is connected to the input of second voltage controlled oscillator, the output of second voltage controlled oscillator is connected to the second input of register unit, wherein:
the fourth loop filter is configured to filter the voltage difference signal, and output the filtered voltage difference signal to the second voltage-controlled oscillator;
the second voltage-controlled oscillator is used for generating a clock signal according to the filtered voltage difference signal and outputting the clock signal to the register unit;
the register unit is used for delaying the data signal received from the phase discriminator according to the clock signal and outputting the recovered data signal.
6. The clock data recovery circuit of claim 4, wherein the second synchronization sub-circuit is implemented based on at least one of: delay line, first-in first-out memory, shift register.
7. A serial interface circuit comprising a clock data recovery circuit as claimed in any one of claims 1 to 6.
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Denomination of invention: A clock data recovery circuit and serial interface circuit Granted publication date: 20230711 Pledgee: Huaxia Bank Co.,Ltd. Hefei high tech Zone sub branch Pledgor: HEFEI DATANG STORAGE TECHNOLOGY Co.,Ltd. Registration number: Y2024980009254 |