CN103414464A - Half-speed clock data recovery circuit based on phase selection interpolation type - Google Patents
Half-speed clock data recovery circuit based on phase selection interpolation type Download PDFInfo
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Abstract
The invention discloses a half-speed clock data recovery circuit based on a phase selection interpolation type. The half-speed clock data recovery circuit based on the phase selection interpolation type aims to solve the problem that at present a phase selection interpolation circuit generating a pair of adjustable orthometric clock signals in a current structure is too complex, and a novel combination method of the phase selection interpolation circuit is provided. The half-speed clock data recovery circuit based on the phase selection / interpolation type comprises a half-speed Bang-Bang type phase discriminator, a phase selector, a phase interpolator, a digital filter, a digital controller and an outer ring reference clock. The phase selection interpolation circuit is one set fewer in phase selection circuit than an original structure, the fact that the one pair of adjustable orthometric clock signals are generated is guaranteed, and the scale of the circuit is reduced at the same time, the area of a follow-up domain is further reduced, and power consumption of the whole circuit is lowered.
Description
Technical field
The invention belongs to the semiconductor integrated circuit design field, relate to the clock data recovery circuit for high-speed serial communication, specifically refer to a kind of clock data recovery circuit of half rate based on Selecting phasing/interpolation type.
Background technology
Clock data recovery circuit is the key modules that realizes high-speed serial communication.In a lot of transmission systems, data flow does not have associated clock signal, therefore clock data recovery circuit need to be from recovering clock signal the serial data received, and while by the data that the clock recovered will receive, resetting, the data of sampling Noise, thus data are introduced in transmitting procedure shake eliminated.
The traditional clock data recovery circuit of the half rate based on Selecting phasing/interpolation type structure as shown in Figure 1.This circuit is comprised of half rate Bang-Bang type phase discriminator, digital filter, digitial controller, phase selector, phase interpolator, controller and outer shroud reference clock.Its outer-loop reference clock provides Clk0 ° of 4 phase differential clocks, Clk180 °, Clk90 ° and Clk270 ° respectively to phase selector 1,3 and phase selector 2,4, and each phase selector carries out respectively 2 according to corresponding control signal C_PS1, C_PS2, C_PS3 and C_PS4 and selects 1 operation to generate 4 differential clock signal Clk_1, Clk_2, Clk_3 and Clk_4; Phase interpolator 1, phase interpolator 2 generate pair of orthogonal differential clock signal Clk_I and Clk_Q to the operation that Clk_1, Clk_2 and Clk_3, Clk_4 do phase-interpolation respectively according to control signal C_PI; The phase relation that half rate Bang-Bang phase discriminator is relatively inputted data and Clk_Q generates corresponding leading UP and hysteresis DN signal; Digital filter generates UP after to UP and DN signal filtering
FAnd DN
FSignal; Digitial controller receives UP
FAnd DN
FSignal generates control signal C_PS1, C_PS2, C_PS3, C_PS4 and the C_PI that controls four phase selectors and two phase interpolator.Whole clock and data recovery loop is as phase-locked loop, until the phase alignment of Clk_Q and input data namely reaches loop-locking, and data Re_Data1 and Re_Data2 after locking after half rate Bang-Bang phase discriminator, recovering the two-way tap.This traditional circuit structure, comparatively lengthy and jumbled in Selecting phasing/interpolation circuit part, in order to produce the pair of orthogonal clock signal, adopted a pair of identical circuit combination, namely two phase selectors add a phase interpolator, digitial controller need to produce four Selecting phasing control signals and a phase-interpolation control signal in addition, has increased the design difficulty of digitial controller.
Summary of the invention
Technical problem:The present invention is directed to the deficiencies in the prior art, propose a kind of based on Selecting phasing interpolation type clock data recovery circuit.
Technical scheme:The present invention, for solving the problems of the technologies described above, adopts following technical scheme:
Described half rate clock data recovery circuit comprises half rate Bang-Bang type phase discriminator, digital filter, digitial controller, phase selector, phase interpolator and outer shroud reference clock;
The 2 road differential clock signals that the phase place that described first-phase digit selector receives the output of outer shroud reference clock is respectively 0 ° and 180 °, under the first Selecting phasing control signal is controlled, carry out 2 and select operation generation the first differential clock signal CLK_1 of 1;
The 2 road differential clock signals that the phase place that described second-phase digit selector receives the output of outer shroud reference clock is respectively 90 ° and 270 °, under the second Selecting phasing control signal is controlled, carry out 2 and select operation generation the second differential clock signal CLK_2 of 1;
Described the first phase interpolator receives the first differential clock signal CLK_1 and the second differential clock signal CLK_2, under third phase position interpolation device control signal C_PI controls, the first differential clock signal and the second differential clock signal are done to phase-interpolation generation the first recovered clock signal CLK_I;
Described the second phase interpolator receives inversion signal and the first differential clock signal CLK_1 of the second differential clock signal CLK_2, under third phase position interpolation device control signal C_PI controls, inversion signal and first differential clock signal of the second differential clock signal are done to phase-interpolation generation the second recovered clock signal CLK_Q;
Described half rate Bang-Bang type phase discriminator receives the recovered clock signal of input data Data and phase interpolator output, and relatively the phase relation of the two generates the first anticipating signal and the second delay signal;
Described digital filter receives the first anticipating signal UP and the second delay signal DN of half rate Bang-Bang type phase discriminator output, generates and export anticipating signal UP after the first filtering
FWith delay signal DN after the second filtering
F
Described digitial controller, under sub-frequency clock signal is controlled, receives anticipating signal UP after the first filtering
FWith delay signal DN after the second filtering
FExport the first Selecting phasing control signal C_PS1, the second Selecting phasing control signal C_PS1 and third phase position interpolation device control signal C_PI, the above two control respectively first-phase digit selector, second-phase digit selector, and the third party controls the first phase interpolator and the second phase interpolator simultaneously;
Described half rate clock data recovery circuit is until the phase alignment of second clock signal and input data Data namely reaches loop-locking, simultaneously the data after recovering the two-way tap half rate Bang-Bang phase discriminator.
Beneficial effect:The present invention proposes a kind of clock data recovery circuit of half rate based on Selecting phasing/interpolation type.Compared to traditional circuit structure, the present invention simplifies more in Selecting phasing/interpolation circuit part, a pair of phase selector and a pair of phase interpolator have only been used, the control signal of digitial controller generation is also corresponding has in addition reduced two, reduce in a word the scale of integrated circuit, reduced the design difficulty of digitial controller.
The accompanying drawing explanation
Fig. 1 is the half rate clock data recovery circuit schematic diagram of tradition based on Selecting phasing/interpolation type.
Fig. 2 is the clock data recovery circuit of the half rate based on Selecting phasing/interpolation type schematic diagram of the present invention.
Fig. 3 is the circuit diagram of phase selector in the present invention.
Fig. 4 is the circuit diagram of phase interpolator in the present invention.
Fig. 5 is the variation schematic diagram with the phase-interpolation weight coefficient of current forms performance.
Fig. 6 is the eye pattern of data Re_Data1 after the tap of recovering after locking.
Fig. 7 is the eye pattern of data Re_Data2 after the tap of recovering after locking.
Embodiment
For the technological means that further illustrates advantage of the present invention place and specifically take, be described in further detail below in conjunction with the embodiment of accompanying drawing to a kind of clock data recovery circuit of half rate based on the Selecting phasing interpolation type of the present invention.
Half rate based on Selecting phasing interpolation type clock data recovery circuit of the present invention, described clock data recovery circuit comprise half rate Bang-Bang type phase discriminator, digital filter, digitial controller, phase selector, phase interpolator and outer shroud reference clock;
Described half rate Bang-Bang type phase discriminator receives clock signal C lk_I and the Clk_Q of input data and phase interpolator I, Q output, and the phase relation of relatively inputting data and Clk_Q generates the first anticipating signal UP and the second delay signal DN; The first anticipating signal UP and the second delay signal DN are input to digital filter;
Described digital filter receives the first anticipating signal UP and the second delay signal DN, anticipating signal UP after generation the first filtering
FWith delay signal DN after the second filtering
F
Anticipating signal UP after described digitial controller reception the first filtering
FWith delay signal DN after the second filtering
FExport the first Selecting phasing control signal C_PS1(1 bit digital control signal), the second Selecting phasing control signal C_PS2(1 bit digital control signal) and third phase position interpolation device control signal C_PI(15 bit digital control signal), the above two are control phase selector 1, phase selector 2 respectively, and the third party is control phase interpolation device I and phase interpolator Q simultaneously;
Described phase selector 1 as shown in Figure 3, receives 2 road differential signal Clk0 °, Clk180 ° of outer shroud reference clock output, under the first Selecting phasing control signal C_PS1 controls, carries out 2 and selects operation generation the first differential clock signal Clk_1 of 1;
Described phase selector 2 receives 2 road differential signal Clk90 °, Clk270 ° of outer shroud reference clock output, under the second Selecting phasing control signal C_PS2 controls, carries out 2 and selects operation generation the second differential clock signal Clk_2 of 1;
Described phase interpolator I as shown in Figure 4, receives the first differential clock signal Clk_1 and the second differential clock signal Clk_2, under control signal C_PI controls, Clk_1 and Clk_2 is done to phase-interpolation generation recovered clock signal Clk_I;
Described phase interpolator Q receives inversion signal and the first differential clock signal Clk_1 of the second differential clock signal Clk_2, under control signal C_PI controls, the inversion signal of Clk_2 and Clk_1 is done to phase-interpolation and generate recovered clock signal Clk_Q;
The method of above-mentioned generation pair of orthogonal clock signal C lk_I and Clk_Q is based on following formula:
V
out=αCLKI+βCLKQ，V
out,90=βCLKI-αCLKQ
Wherein α, β are generated by phase-interpolation control signal C_PI, and β be α complementary signal (be β=/ α) because in the present invention, phase interpolator I, Q are with being controlled by C_PI, so improve on the basis to top formula:
V
out=αCLKI+βCLKQ，V
out,90=α（-CLKQ）+βCLKI
The C_PI that is α, β representative remains unchanged, by reconfiguring of two interpolation input signals being realized to the generation of pair of orthogonal clock signal.The formula of above-mentioned improved is specially in the present invention:
Clk_I=αClk_1+βClk_2，Clk_Q=α（-Clk_2）+βClk_1
Described clock data recovery circuit is until the phase alignment of clock signal C lk_Q and input data namely reaches loop-locking, data Re_Data1 and the Re_Data2 after recovering the two-way tap half rate Bang-Bang phase discriminator simultaneously.
In Case Simulation process of the present invention, the input data are the pseudo random sequence of 2.5Gbps, and the emulation duration is 3us, and whole clock and data recovery loop is in about 1.2us left and right locking, and namely data are alignd with the clock signal C lk_Q edge of phase interpolator Q output.Figure 5 shows that two coefficients are complementary relationship, monotone increasing or minimizing before locking with the phase-interpolation weight coefficient of current forms performance.Fig. 6,7 eye patterns for the two-way tap data after locking, same quality is fine, and the correctness of integrated circuit is described.
In sum, feature extraction of the present invention a kind of combined method of novel Selecting phasing interpolation circuit, than original structure is few, used one group of phase option circuit, when guaranteeing to produce the pair of orthogonal clock signal, reduced the scale of circuit, and then reduced the area of follow-up domain, reduced the power consumption of integrated circuit.
For those skilled in the art, can be easy to other advantage and distortion of association according to above implementation of class.Therefore, the present invention is not limited to above-mentioned instantiation, and it carries out detailed, exemplary explanation as just example to a kind of form of the present invention.In the scope that does not deviate from aim of the present invention, those of ordinary skills replace resulting technical scheme according to above-mentioned instantiation by various being equal to, within all should being included in claim scope of the present invention and equivalency range thereof.
Claims (1)
1. clock data recovery circuit of the half rate based on the Selecting phasing interpolation type, it is characterized in that, described half rate clock data recovery circuit comprises half rate Bang-Bang type phase discriminator, digital filter, digitial controller, phase selector, phase interpolator and outer shroud reference clock;
The 2 road differential clock signals that the phase place that described first-phase digit selector receives the output of outer shroud reference clock is respectively 0 ° and 180 °, under the first Selecting phasing control signal is controlled, carry out 2 and select operation generation the first differential clock signal CLK_1 of 1;
The 2 road differential clock signals that the phase place that described second-phase digit selector receives the output of outer shroud reference clock is respectively 90 ° and 270 °, under the second Selecting phasing control signal is controlled, carry out 2 and select operation generation the second differential clock signal CLK_2 of 1;
Described the first phase interpolator receives the first differential clock signal CLK_1 and the second differential clock signal CLK_2, under third phase position interpolation device control signal C_PI controls, the first differential clock signal and the second differential clock signal are done to phase-interpolation generation the first recovered clock signal CLK_I;
Described the second phase interpolator receives inversion signal and the first differential clock signal CLK_1 of the second differential clock signal CLK_2, under third phase position interpolation device control signal C_PI controls, inversion signal and first differential clock signal of the second differential clock signal are done to phase-interpolation generation the second recovered clock signal CLK_Q;
Described half rate Bang-Bang type phase discriminator receives the recovered clock signal of input data Data and phase interpolator output, and relatively the phase relation of the two generates the first anticipating signal and the second delay signal;
Described digital filter receives the first anticipating signal UP and the second delay signal DN of half rate Bang-Bang type phase discriminator output, generates and export anticipating signal UP after the first filtering
FWith delay signal DN after the second filtering
F
Described digitial controller, under sub-frequency clock signal is controlled, receives anticipating signal UP after the first filtering
FWith delay signal DN after the second filtering
FExport the first Selecting phasing control signal C_PS1, the second Selecting phasing control signal C_PS1 and third phase position interpolation device control signal C_PI, the above two control respectively first-phase digit selector, second-phase digit selector, and the third party controls the first phase interpolator and the second phase interpolator simultaneously;
Described half rate clock data recovery circuit is until the phase alignment of second clock signal and input data Data namely reaches loop-locking, simultaneously the data after recovering the two-way tap half rate Bang-Bang phase discriminator.
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| CN106209094A (en) * | 2016-07-01 | 2016-12-07 | 中国电子科技集团公司第五十八研究所 | A kind of implementation method based on FPGA 50% dutycycle fractional frequency division |
| CN106656174A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | High-speed clock data recovery circuit of novel structure |
| CN106776426A (en) * | 2016-12-05 | 2017-05-31 | 清华大学 | A kind of emitter with timing alignment |
| CN109150171A (en) * | 2018-09-14 | 2019-01-04 | 南京邮电大学 | A kind of phase frequency detector and clock data recovery circuit of high speed low jitter |
| CN110233611A (en) * | 2019-06-18 | 2019-09-13 | 苏州兆凯电子有限公司 | A kind of cascade phase interpolation method, circuit and a kind of clock data recovery circuit |
| CN111010175A (en) * | 2019-12-11 | 2020-04-14 | 浙江大学 | High-linearity phase interpolator |
| CN115333513A (en) * | 2022-07-28 | 2022-11-11 | 灿芯半导体(苏州)有限公司 | Phase interpolation circuit with good linearity |
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Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106656174A (en) * | 2015-10-28 | 2017-05-10 | 北京华大九天软件有限公司 | High-speed clock data recovery circuit of novel structure |
| CN105703767A (en) * | 2016-01-13 | 2016-06-22 | 中国科学技术大学先进技术研究院 | High-energy-efficiency low-jitter single loop clock data recovery circuit |
| CN105703767B (en) * | 2016-01-13 | 2018-10-12 | 中国科学技术大学先进技术研究院 | A kind of single loop clock data recovery circuit of high energy efficiency low jitter |
| CN106209094B (en) * | 2016-07-01 | 2018-10-30 | 中国电子科技集团公司第五十八研究所 | A kind of implementation method based on 50% duty ratio fractional frequency divisions of FPGA |
| CN106209094A (en) * | 2016-07-01 | 2016-12-07 | 中国电子科技集团公司第五十八研究所 | A kind of implementation method based on FPGA 50% dutycycle fractional frequency division |
| CN106776426B (en) * | 2016-12-05 | 2020-10-27 | 清华大学 | Transmitter with time sequence calibration |
| CN106776426A (en) * | 2016-12-05 | 2017-05-31 | 清华大学 | A kind of emitter with timing alignment |
| CN109150171A (en) * | 2018-09-14 | 2019-01-04 | 南京邮电大学 | A kind of phase frequency detector and clock data recovery circuit of high speed low jitter |
| CN109150171B (en) * | 2018-09-14 | 2022-04-05 | 南京邮电大学 | High-speed low-jitter phase frequency detector and clock data recovery circuit |
| CN110233611A (en) * | 2019-06-18 | 2019-09-13 | 苏州兆凯电子有限公司 | A kind of cascade phase interpolation method, circuit and a kind of clock data recovery circuit |
| CN110233611B (en) * | 2019-06-18 | 2023-02-28 | 苏州兆凯电子有限公司 | Cascade phase interpolation method and circuit and clock data recovery circuit |
| CN111010175A (en) * | 2019-12-11 | 2020-04-14 | 浙江大学 | High-linearity phase interpolator |
| CN111010175B (en) * | 2019-12-11 | 2021-06-29 | 浙江大学 | High-linearity phase interpolator |
| CN115333513A (en) * | 2022-07-28 | 2022-11-11 | 灿芯半导体(苏州)有限公司 | Phase interpolation circuit with good linearity |
| CN115333513B (en) * | 2022-07-28 | 2023-09-01 | 灿芯半导体(苏州)有限公司 | Phase interpolation circuit with good linearity |
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