CN111010175A - High-linearity phase interpolator - Google Patents
High-linearity phase interpolator Download PDFInfo
- Publication number
- CN111010175A CN111010175A CN201911267006.4A CN201911267006A CN111010175A CN 111010175 A CN111010175 A CN 111010175A CN 201911267006 A CN201911267006 A CN 201911267006A CN 111010175 A CN111010175 A CN 111010175A
- Authority
- CN
- China
- Prior art keywords
- output
- phase interpolation
- interpolation unit
- phase
- selector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000295 complement effect Effects 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 11
- 101100112673 Rattus norvegicus Ccnd2 gene Proteins 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000011084 recovery Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
Landscapes
- Manipulation Of Pulses (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a high-linearity phase interpolator, which comprises: the phase interpolation unit group outputs clock signals under the action of the digital control unit, the clock signals are obtained by combining two paths of clocks with 45-degree phase difference according to a certain proportion, and the proportion is controlled by a control code of the digital control unit; the two paths of clocks with the phase difference of 45 degrees are output by two one-out-of-four selectors; the phase interpolation unit group comprises 9 phase interpolation units, 4 two-out-of-one selectors and 1 four-out-of-one selector. The invention innovatively improves the structure of the phase interpolation unit, can cut off a short-circuit path existing in the interpolation process of the inverter type interpolator by adopting the structure, has simpler circuit realization compared with the existing method of adding a logic gate, and can also carry out phase fine adjustment on an interpolation signal, thereby further improving the interpolation precision.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and more particularly, to a high-linearity phase interpolator and a control method thereof.
Background
Phase interpolators are widely used in clock data recovery circuits. Conventional phase interpolators can be classified into two types, a current-steering type and an inverter type: for the current steering type interpolator, the guarantee of the linearity depends on the relationship among the quality of an input signal, the phase difference and an output load, in order to obtain better interpolation linearity, the size of a circuit needs to be carefully adjusted, and the circuit always has a path from a power supply to the ground; the phase interpolator of the inverter type has the advantages that the design flow of a digital circuit can be introduced, the requirement on the quality of an input signal is not high, the phase interpolator is convenient to transplant among different processes, but the linearity is influenced by the influence of a short circuit path in the interpolation process.
Since the inverter type phase interpolator can be conveniently transplanted among different processes, and the overall power consumption of the circuit is not as high as that of the current steering type, the phase interpolator part in many high-speed circuits takes priority to the structure at present. However, in the conventional method, the influence of the short-circuit path is avoided by adding a logic gate and turning off the downlink path at the falling edge of the interpolation signal at the moment when the level logic is opposite, but the drawing of the back-end layout is inconvenient by using the standard cell logic gate.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, a high-linearity phase interpolator is provided.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a high linearity phase interpolator, comprising:
the phase interpolation unit group outputs clock signals under the action of the digital control unit, the clock signals are obtained by combining two paths of clocks with 45-degree phase difference according to a certain proportion, and the proportion is controlled by a control code of the digital control unit; the two paths of clocks with the phase difference of 45 degrees are output by 2 one-out-of-four selectors;
the phase interpolation unit group comprises 9 phase interpolation units, 4 two-out-of-one selectors and 1 four-out-of-one selector;
two clock input ports of the first phase interpolation unit are connected with a first clock input port of the phase interpolation unit group; a first clock input port of the second phase interpolation unit is connected with a first clock input port of the phase interpolation unit group, and the other clock input port of the second phase interpolation unit is connected with a second clock input port of the phase interpolation unit group; two clock input ports of the third phase interpolation unit are both connected with a second clock input port of the phase interpolation unit group; the first input end of the first alternative selector is connected with the output of the first phase interpolation unit, the second input end of the first alternative selector is connected with the output of the third phase interpolation unit, and the selection end of the first alternative selector is connected with the output control code of the digital control unit; the first input end of the second alternative selector is connected with the output of the second phase interpolation unit, the second input end of the second alternative selector is connected with a power ground, and the selection end of the second alternative selector is connected with the output control code of the digital control unit; two clock input ports of the fourth phase interpolation unit are both connected with the output of the first one-of-two selector, a first clock input port of the fifth phase interpolation unit is connected with the output of the first one-of-two selector, and the other clock input port of the fifth phase interpolation unit is connected with the output of the second one-of-two selector; two clock input ports of the sixth phase interpolation unit are both connected with the output of the second one-of-two selector; the first input end of the third alternative selector is connected with the output of the fourth phase interpolation unit, the second input end of the third alternative selector is connected with the output of the sixth phase interpolation unit, and the selection end of the third alternative selector is connected with the output control code of the digital control unit; the first input end of the fourth alternative selector is connected with the output of the fifth phase interpolation unit, the second input end of the fourth alternative selector is connected with a power ground, and the selection end of the fourth alternative selector is connected with the output control code of the digital control unit; two clock input ports of the seventh phase interpolation unit are both connected with the output of the third alternative selector; a first clock input port of the eighth phase interpolation unit is connected with the output of the third alternative selector, and the other clock input port of the eighth phase interpolation unit is connected with the output of the fourth alternative selector; two clock input ports of the ninth phase interpolation unit are both connected with the output of the fourth alternative selector; the first input end of the one-out-of-four selector is connected with the output of the seventh phase interpolation unit, the second input end of the one-out-of-four selector is connected with the output of the eighth phase interpolation unit, the third input end of the one-out-of-four selector is connected with the output of the ninth phase interpolation unit, the fourth input end of the one-out-of-four selector is connected with the power ground, the selection end of the one-out-of-four selector is connected with the output of the digital control unit to output.
In the above technical solution, further, an input port of one of the 2 one-out-of-four selectors is connected to four input clock signals, the phases of the four input clocks are respectively 0 °, 90 °, 180 °, 270 °, and the selection port is connected to an output port of the digital control unit, and an output port thereof is connected to a first clock input port of the phase interpolation unit group; the input port of another one-out-of-four selector is connected with four paths of input clock signals, the phases of the four paths of input clocks are 45 degrees, 135 degrees, 225 degrees and 315 degrees respectively, the selection port is connected with the output port of the digital control unit, and the output port of the selection port is connected with the second clock input port of the phase interpolation unit group. .
Furthermore, the digital control unit outputs three paths of output control codes according to the input signals late, early, wherein the first path of output control codes is 15 bits, and the second and third paths of output control codes are both 4 bits; and controlling the phase interpolation unit to generate an output clock signal by the three paths of output control codes, wherein the phase of the output clock signal is between the two selected paths of clocks.
Furthermore, the enable signals of the 9 phase interpolation units of the phase interpolation unit group, the selection ends of the 4 two-out-of-one selectors and the selection ends of the 1 four-out-of-one selectors are all connected with the first output code of the digital control unit, and the 4-bit input control codes of the 9 phase interpolation units are all connected with the second output control code of the digital control unit.
Furthermore, the phase interpolation unit is composed of four parts, including:
an inverter, the input end of which is connected with an enable signal;
the first branch circuit comprises two groups of branch circuits with short-circuit outputs, and one group of branch circuits comprises a first NMOS, a second NMOS and 1 PMOS which are sequentially connected in series; the grid of the second NMOS is connected with a first clock input port of the phase interpolation unit; the first NMOS grid is connected with a second clock input port of the phase interpolation unit;
the PMOS grid is in short circuit with the first NMOS grid; the other group of branches comprises a third NMOS, a fourth NMOS and 1 PMOS which are sequentially connected in series, and the grid electrode of the fourth NMOS is connected with the first clock input port of the phase interpolation unit; the grid of the third NMOS is connected with a second clock input port of the phase interpolation unit; the PMOS grid is in short circuit with the third NMOS grid;
the second branch circuit comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS and a second NMOS which are sequentially connected in series, and the grid electrode of the first NMOS is connected with an enabling signal; the grid of the second NMOS is connected with the output of the first branch circuit, and the drain of the second NMOS is connected with the output of the phase interpolation unit; the grid of the third PMOS is connected with the complementary signal of the enable signal, and the drain of the third PMOS is connected with the output of the phase interpolation unit; the grid of the second PMOS is connected with the output of the first branch circuit, and the grid of the first PMOS is in short circuit with the grid of the second PMOS;
the grid electrodes of the four PMOS tubes are connected with the output of the phase interpolation unit, the source electrodes of the four PMOS tubes are connected with the drain electrode of the first PMOS tube in the second branch, the drain electrodes of the four PMOS tubes are respectively connected with the input control code of the phase interpolation unit, and the bit width of the four PMOS tubes is 4 bits.
The invention has the advantages that:
the invention designs a high-linearity phase interpolator, the front end selects two adjacent clocks from 8 clock signals with phase difference of 45 degrees in sequence through 2 one-out-of-four selectors, and 1 phase interpolation unit group outputs clock signals converged by the two clocks according to a certain proportion under the action of different control codes.
In the invention, the number of the phase interpolation units is effectively reduced by changing the connection relation of each phase interpolation unit in the phase interpolation unit group, so that the structure of the phase interpolation unit group is simpler, and simultaneously, the load size and the circuit area of the output end are reduced.
The invention also innovatively improves the structure of the phase interpolation unit, and by adopting the structure, a short-circuit path existing in the interpolation process of the inverter type interpolator can be cut off, compared with the existing method for adding a logic gate, the circuit is simpler to realize, meanwhile, the phase fine adjustment can be carried out on an interpolation signal, and the interpolation precision is further improved.
Drawings
FIG. 1 is a circuit schematic of a conventional current-steering type phase interpolator;
FIG. 2 is a circuit schematic of a conventional inverter-type phase interpolator;
FIG. 3 is a schematic diagram of the short circuit path present in an inverter type structure;
FIG. 4 is a schematic diagram of a highly linear phase interpolator in accordance with the present invention;
FIG. 5 is a circuit diagram of the internal circuit of the phase interpolation unit group according to the present invention;
fig. 6 is a schematic circuit diagram of a single phase interpolation unit in the present invention.
Detailed Description
In order to make the technical solution of the present invention more comprehensible, the following detailed description is made with reference to the accompanying drawings.
The traditional phase interpolator is divided into a current rudder type phase interpolator and an inverter type phase interpolator, fig. 1 is the phase interpolator with the traditional current rudder type structure, in the structure of the current rudder type phase interpolator, 8 groups of interpolation unit groups are often connected in a mode of outputting short circuit, each group of interpolation unit is formed by connecting a plurality of same differential pair tubes in parallel, and by controlling different control codes, an output clock with two paths of clocks combined according to a certain proportion can be obtained at an output end; fig. 2 shows an inverter type phase interpolator, in which when one input clock is at a low level and one input clock is at a high level, there is a short-circuit path shown in fig. 3, which shunts a part of the charging current, resulting in a slow rise time of the previous segment of the output clock, and thus causing the phase of the output clock to deviate from an ideal position, thereby affecting linearity.
Fig. 4 is a schematic block diagram of a high linearity phase interpolator, which is composed of three parts, including 1 phase interpolation unit group, two 4-to-1 selection gates and a digital control unit, wherein the phase interpolation unit outputs clock signals under the action of the digital control unit, and the clock signals are obtained by combining two paths of clocks with a phase difference of 45 ° according to a certain proportion. The multi-path selector selects two paths of clocks with the phase difference of 45 degrees from the 8 paths of clocks and sends the two paths of clocks to the phase interpolation unit group, and the phase interpolation unit group generates output clocks of the two paths of clocks combined according to a certain proportion under the action of control codes sel 0-sel 15 and fsel 0-fsel 3 output by the digital control unit, so that the purpose of clock signal phase interpolation is achieved.
The multi-path selector is two 1-out-of-4 selectors, one selection gate port I0-I3 is connected with four paths of clock signals, the clock phases are respectively 0 degrees, 90 degrees, 180 degrees, 270 degrees, the selection port S0 and S1 are connected with the digital control units S0 and S1, the output Z0 is connected with vin1 of the interpolation module, the other selection gate port I0-I3 is connected with four paths of clock signals, the clock phases are respectively 45 degrees, 135 degrees, 225 degrees and 315 degrees, the selection port S2 and S3 are connected with the digital control units S2 and S3, and the output Z1 is connected with vin2 of the interpolation module.
As shown in fig. 5, the phase interpolation unit group includes 9 phase interpolation units, 4 two-out-of-one selectors, and 1 four-out-of-one selector, the input control codes en 0-en 8 of the phase interpolation unit group are connected to sel [14:6] of the digital control unit, the input control codes fsel 0-fsel 3 of the phase interpolation unit are connected to fsel 0-fsel 3 of the digital control unit, and the selector control codes sel 0-sel 4 are connected to sel [5:0] of the digital control unit.
Fig. 6 is a schematic diagram of a single interpolation unit, which is composed of 4 branches, including:
an NMOS and a PMOS are connected in series to form an inverter, the grid electrode of the inverter is connected with an enable signal en, and the drain electrode of the inverter outputs a complementary signal en _ n of the en;
a group of mirror image inverter branches, one group of branches is formed by connecting 2 NMOS and 1 PMOS in series, the grid of NM83 is connected with input vin1, the grid of NM0 is connected with input vin2, the grid of PM87 is connected with vin1, the other group of branches is formed by connecting 2 NMOS and 1 PMOS in series, the grid of NM82 is connected with input vin2, the grid of NM1 is connected with input vin1, the grid of PM86 is connected with vin2, and the two branches output short circuit xout _ m, the part adopts the structure, and can cut off the short circuit path phenomenon existing in the inverter type interpolator, because when vin1 is low level, the low level of vin1 cuts off the path on the vin2 side during the high level of vin2, so that only PMOS on branch of vin1 charges the output capacitor, and other paths to the ground do not exist, thereby avoiding the influence of the short circuit path on the linearity of the phase interpolator;
a branch with 2 NMOS and 3 PMOS connected in series, NM84, PM90, PM93 with grid connected to output xout _ m of the previous stage, NM86 with grid connected to enable signal en, drain connected to output xout of interpolator, PM92 with grid connected to complementary signal en _ n of enable signal, and drain connected to output xout of interpolator;
four same PMOS are connected in parallel, four gates are connected with the output xout of the interpolator unit, the source is connected with the drain of the front branch PM90 tube, the drains of the four PMOS tubes are respectively connected with control codes fsel 0-fsel 3, the structure of Schmidt trigger type is adopted, taking tube PM94 as an example, when the output level is switched from low to high, the gate voltage is 0, if the corresponding drain is grounded, namely signal fsel0, then a charging path from the power supply to the ground through PM94 exists, the shunting effect is achieved, namely the current for charging the output node xout by the power supply through PM90, PM92 and PM93 is reduced, so that the rise time of the output signal is increased, and because the four PMOS tubes are all small in size when the tube parameters are designed, the rise time increase can be small step, so that the fine adjustment of the phase of the output clock signal is realized, and the extra load can not be introduced into the output, meanwhile, the preceding stage circuit only processes the falling time of the output signal, and the branch circuit can adjust the rising time of the output signal, so that certain compensation is performed on the duty ratio of the signal. The specific adjustment process of the digital control logic is as follows: after the circuit is reset, the digital control logic sets the high 9 bits of interpolation control codes sel 0-sel 14, the low 6 bits of the interpolation controller, fine-tuning control codes fsel 0-fsel 3, selection control codes S0-S3 as 9 '1 ff, 6' b001000, 4 'hf and 4' h0 respectively, two one-out-of-four selectors select 0 degree clock and 45 degree clock respectively, the phase interpolator is applied in the clock data recovery circuit, the phase relation between the clock and the data provided by the preceding circuit is required to be advanced early or late, the digital control unit operates the interpolation control codes according to the relation between input late and early at each moment, if late is 1 and early is 0, the low 6 bits of the interpolation control codes are changed according to the relation of 6 'b 001001-6' b001010-6 'b 000000-6' b000001-6 'b 000010 until the level of late and early is changed, if the level of the interpolation control codes is 0, the level of 10006' b 10006-10006 'b 000010, the level of the interpolation control codes is changed according to the change of 10006' b10001, until the levels of late and early are interchanged; in the shifting process, if the polarities of late and early are reversed, the interpolation control code is changed into the value of the previous moment, the fine adjustment control code is shifted and zero-filled at the lower bit, and the circuit is considered to be locked until the polarities of late and early are reversed again; if in the above operation the levels of late and early are not interchanged all the time, when the boundary of each case is reached, the low 6 positions of sel0 to sel14 are set to 6 ' b001000, and the left shift operation is performed on the selection control code, i.e., if the current input clock is 0 ° and 45 °, the switching is performed to 45 ° and 90 °, and when the values of sel0 to sel15 are 16 ' h00ff, the sel0 to sel15 are set to 16 ' h0ff0, and the right shift operation is performed on the selection control code, i.e., if the current input clock is 0 ° and 45 °, the switching is performed to 0 ° and 315 °; and repeating the steps in sequence until the circuit is locked.
Claims (5)
1. A high linearity phase interpolator, comprising: the phase interpolation unit group outputs clock signals under the action of the digital control unit, the clock signals are obtained by combining two paths of clocks with 45-degree phase difference according to a certain proportion, and the proportion is controlled by a control code of the digital control unit; the two paths of clocks with the phase difference of 45 degrees are output by the 2 one-out-of-four selectors;
the phase interpolation unit group comprises 9 phase interpolation units, 4 two-out-of-one selectors and 1 four-out-of-one selector;
two clock input ports of the first phase interpolation unit are connected with a first clock input port of the phase interpolation unit group; a first clock input port of the second phase interpolation unit is connected with a first clock input port of the phase interpolation unit group, and the other clock input port of the second phase interpolation unit is connected with a second clock input port of the phase interpolation unit group; two clock input ports of the third phase interpolation unit are both connected with a second clock input port of the phase interpolation unit group; the first input end of the first alternative selector is connected with the output of the first phase interpolation unit, the second input end of the first alternative selector is connected with the output of the third phase interpolation unit, and the selection end of the first alternative selector is connected with the output control code of the digital control unit; the first input end of the second alternative selector is connected with the output of the second phase interpolation unit, the second input end of the second alternative selector is connected with a power ground, and the selection end of the second alternative selector is connected with the output control code of the digital control unit; two clock input ports of the fourth phase interpolation unit are both connected with the output of the first one-of-two selector, a first clock input port of the fifth phase interpolation unit is connected with the output of the first one-of-two selector, and the other clock input port of the fifth phase interpolation unit is connected with the output of the second one-of-two selector; two clock input ports of the sixth phase interpolation unit are both connected with the output of the second one-of-two selector; the first input end of the third alternative selector is connected with the output of the fourth phase interpolation unit, the second input end of the third alternative selector is connected with the output of the sixth phase interpolation unit, and the selection end of the third alternative selector is connected with the output control code of the digital control unit; the first input end of the fourth alternative selector is connected with the output of the fifth phase interpolation unit, the second input end of the fourth alternative selector is connected with a power ground, and the selection end of the fourth alternative selector is connected with the output control code of the digital control unit; two clock input ports of the seventh phase interpolation unit are both connected with the output of the third alternative selector; a first clock input port of the eighth phase interpolation unit is connected with the output of the third alternative selector, and the other clock input port of the eighth phase interpolation unit is connected with the output of the fourth alternative selector; two clock input ports of the ninth phase interpolation unit are both connected with the output of the fourth alternative selector; the first input end of the one-out-of-four selector is connected with the output of the seventh phase interpolation unit, the second input end of the one-out-of-four selector is connected with the output of the eighth phase interpolation unit, the third input end of the one-out-of-four selector is connected with the output of the ninth phase interpolation unit, the fourth input end of the one-out-of-four selector is connected with the power ground, the selection end of the one-out-of-four selector is connected with the output of the digital control unit to output.
2. A high linearity phase interpolator as claimed in claim 1, wherein the input port of one of said 2 four-out-of-one selectors is connected to four input clock signals, the four input clock signals have phases of 0 °, 90 °, 180 °, 270 °, the selection port is connected to the output port of the digital control unit, and the output port is connected to the first clock input port of the phase interpolation unit group; the input port of another one-out-of-four selector is connected with four paths of input clock signals, the phases of the four paths of input clocks are 45 degrees, 135 degrees, 225 degrees and 315 degrees respectively, the selection port is connected with the output port of the digital control unit, and the output port of the selection port is connected with the second clock input port of the phase interpolation unit group.
3. The high linearity phase interpolator of claim 1, wherein said digital control unit outputs three output control codes according to the input signal late, early, wherein the first output control code is 15 bits, and the second and third output control codes are 4 bits; and the three paths of output control codes control the phase interpolation unit to output the clock signals.
4. The high-linearity phase interpolator of claim 3, wherein the enable signals of 9 phase interpolation units of the phase interpolation unit group, the selection terminals of the 4 two-out-of-one selectors, and the selection terminals of the 1 four-out-of-one selector are all connected to the first output code of the digital control unit, and the 4-bit input control codes of the 9 phase interpolation units are all connected to the second output control code of the digital control unit.
5. A high linearity phase interpolator as claimed in claim 4, wherein said phase interpolation unit is formed of four parts, comprising:
an inverter, the input end of which is connected with an enable signal;
the first branch circuit comprises two groups of branch circuits with short-circuit outputs, and one group of branch circuits comprises a first NMOS, a second NMOS and 1 PMOS which are sequentially connected in series; the grid of the second NMOS is connected with a first clock input port of the phase interpolation unit; the first NMOS grid is connected with a second clock input port of the phase interpolation unit;
the PMOS grid is in short circuit with the first NMOS grid; the other group of branches comprises a third NMOS, a fourth NMOS and 1 PMOS which are sequentially connected in series, and the grid electrode of the fourth NMOS is connected with the first clock input port of the phase interpolation unit; the grid of the third NMOS is connected with a second clock input port of the phase interpolation unit; the PMOS grid is in short circuit with the third NMOS grid;
the second branch circuit comprises a first PMOS, a second PMOS, a third PMOS, a first NMOS and a second NMOS which are sequentially connected in series, and the grid electrode of the first NMOS is connected with an enabling signal; the grid of the second NMOS is connected with the output of the first branch circuit, and the drain of the second NMOS is connected with the output of the phase interpolation unit; the grid of the third PMOS is connected with the complementary signal of the enable signal, and the drain of the third PMOS is connected with the output of the phase interpolation unit; the grid of the second PMOS is connected with the output of the first branch circuit, and the grid of the first PMOS is in short circuit with the grid of the second PMOS;
the grid electrodes of the four PMOS tubes are connected with the output of the phase interpolation unit, the source electrodes of the four PMOS tubes are connected with the drain electrode of the first PMOS tube in the second branch, the drain electrodes of the four PMOS tubes are respectively connected with the input control code of the phase interpolation unit, and the bit width of the four PMOS tubes is 4 bits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911267006.4A CN111010175B (en) | 2019-12-11 | 2019-12-11 | High-linearity phase interpolator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911267006.4A CN111010175B (en) | 2019-12-11 | 2019-12-11 | High-linearity phase interpolator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111010175A true CN111010175A (en) | 2020-04-14 |
| CN111010175B CN111010175B (en) | 2021-06-29 |
Family
ID=70115793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911267006.4A Active CN111010175B (en) | 2019-12-11 | 2019-12-11 | High-linearity phase interpolator |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111010175B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900960A (en) * | 2020-07-17 | 2020-11-06 | 牛芯半导体(深圳)有限公司 | Phase interpolation system |
| CN112165315A (en) * | 2020-09-25 | 2021-01-01 | 北京智芯微电子科技有限公司 | Linear phase interpolator, linear phase interpolation chip and data clock recovery circuit |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1335677A (en) * | 2000-07-21 | 2002-02-13 | 日本电气株式会社 | Clock control method and electric circuit |
| US20080164928A1 (en) * | 2007-01-04 | 2008-07-10 | Micron Technology, Inc. | Phase interpolation apparatus, systems, and methods |
| US20090128198A1 (en) * | 2007-10-22 | 2009-05-21 | Stmicroelectronics S.A. | Digital frequency synthesizer |
| CN202713274U (en) * | 2012-06-29 | 2013-01-30 | 无锡思泰迪半导体有限公司 | Structure of high speed clock data recovery system |
| CN103414464A (en) * | 2013-08-08 | 2013-11-27 | 南京邮电大学 | Half-speed clock data recovery circuit based on phase selection interpolation type |
| CN103795404A (en) * | 2012-10-31 | 2014-05-14 | 中兴通讯股份有限公司 | Phase interpolator circuit and phase interpolation signal processing method |
| CN106656116A (en) * | 2016-12-27 | 2017-05-10 | 上海交通大学 | High-linearity phase interpolator |
| US10014868B1 (en) * | 2017-03-31 | 2018-07-03 | Xilinx, Inc. | Injection-locked phase interpolator |
| CN108923773A (en) * | 2018-06-27 | 2018-11-30 | 重庆湃芯入微科技有限公司 | A kind of low-power consumption adjustable type high linearity phase interpolator |
| CN109217850A (en) * | 2018-08-13 | 2019-01-15 | 上海奥令科电子科技有限公司 | A kind of digital control single-stage multi-clock phase interpolator of stable duty ratio |
| CN109981086A (en) * | 2018-12-29 | 2019-07-05 | 晶晨半导体(上海)股份有限公司 | A kind of phase interpolator |
-
2019
- 2019-12-11 CN CN201911267006.4A patent/CN111010175B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1335677A (en) * | 2000-07-21 | 2002-02-13 | 日本电气株式会社 | Clock control method and electric circuit |
| US20080164928A1 (en) * | 2007-01-04 | 2008-07-10 | Micron Technology, Inc. | Phase interpolation apparatus, systems, and methods |
| US20090128198A1 (en) * | 2007-10-22 | 2009-05-21 | Stmicroelectronics S.A. | Digital frequency synthesizer |
| CN202713274U (en) * | 2012-06-29 | 2013-01-30 | 无锡思泰迪半导体有限公司 | Structure of high speed clock data recovery system |
| CN103795404A (en) * | 2012-10-31 | 2014-05-14 | 中兴通讯股份有限公司 | Phase interpolator circuit and phase interpolation signal processing method |
| CN103414464A (en) * | 2013-08-08 | 2013-11-27 | 南京邮电大学 | Half-speed clock data recovery circuit based on phase selection interpolation type |
| CN106656116A (en) * | 2016-12-27 | 2017-05-10 | 上海交通大学 | High-linearity phase interpolator |
| US10014868B1 (en) * | 2017-03-31 | 2018-07-03 | Xilinx, Inc. | Injection-locked phase interpolator |
| CN108923773A (en) * | 2018-06-27 | 2018-11-30 | 重庆湃芯入微科技有限公司 | A kind of low-power consumption adjustable type high linearity phase interpolator |
| CN109217850A (en) * | 2018-08-13 | 2019-01-15 | 上海奥令科电子科技有限公司 | A kind of digital control single-stage multi-clock phase interpolator of stable duty ratio |
| CN109981086A (en) * | 2018-12-29 | 2019-07-05 | 晶晨半导体(上海)股份有限公司 | A kind of phase interpolator |
Non-Patent Citations (2)
| Title |
|---|
| SHIJIE HU等: "A 10Gbps CDR based on Phase Interpolator for Source", 《IEEE》 * |
| 李天一等: "一种500 Mbps至4 Gbps连续速率的多模式CDR电路", 《太赫兹科学与电子信息学报》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900960A (en) * | 2020-07-17 | 2020-11-06 | 牛芯半导体(深圳)有限公司 | Phase interpolation system |
| CN111900960B (en) * | 2020-07-17 | 2024-06-11 | 牛芯半导体(深圳)有限公司 | Phase interpolation system |
| CN112165315A (en) * | 2020-09-25 | 2021-01-01 | 北京智芯微电子科技有限公司 | Linear phase interpolator, linear phase interpolation chip and data clock recovery circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111010175B (en) | 2021-06-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6597212B1 (en) | Divide-by-N differential phase interpolator | |
| CN111010175B (en) | High-linearity phase interpolator | |
| CN100454755C (en) | Annular voltage controlled oscillator | |
| US8786346B2 (en) | Phase interpolator and method of phase interpolation with reduced phase error | |
| CN106656116B (en) | High linearity phase interpolator | |
| CN102292915B (en) | Current switch cell and digital/analog converter | |
| US20170187361A1 (en) | Clock and data recovery circuit and phase interpolator therefor | |
| CN102158211B (en) | Current switching circuit for high-speed current rudder digital-to-analog converter | |
| US20040188736A1 (en) | Methods of manufacture for a low control voltage switch | |
| CN109672444B (en) | Ultra-high-speed digital-to-analog converter with multi-channel clock interweaving | |
| CN111756348B (en) | N-path band-pass filter with configurable transconductance capacitor | |
| CN115865040A (en) | Variable gain active phase shifter capable of working bidirectionally | |
| WO2022213587A1 (en) | High-linearity phase interpolation circuit | |
| CN110650105A (en) | Adaptive continuous time linear equalization broadband active linear equalizer circuit | |
| CN112291120B (en) | Delay line structure and correction method of delay jitter thereof | |
| CN111900960A (en) | Phase interpolation system | |
| CN105991112B (en) | A kind of data clock recovery circuit and its phase interpolator | |
| CN106856405A (en) | A kind of switching current device and the digital analog converter based on the device | |
| CN106603039B (en) | Delay unit and annular voltage-controlled oscillator comprising same | |
| CN115694527A (en) | Four-level pulse amplitude modulation high-speed serial port transmitter structure based on DAC | |
| CN111381654B (en) | Load detection circuit, SOC system, and method for configuring load detection circuit | |
| CN110119179B (en) | Floating high-voltage selection circuit applied to multiple high-voltage sources | |
| CN111884627A (en) | Dynamic miller compensation circuit and method for driving Buffer without external capacitor | |
| CN110233611B (en) | Cascade phase interpolation method and circuit and clock data recovery circuit | |
| CN117040496B (en) | High-speed multi-bit phase interpolator and phase shifting method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |