CN108923773A - A kind of low-power consumption adjustable type high linearity phase interpolator - Google Patents
A kind of low-power consumption adjustable type high linearity phase interpolator Download PDFInfo
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- CN108923773A CN108923773A CN201810676845.0A CN201810676845A CN108923773A CN 108923773 A CN108923773 A CN 108923773A CN 201810676845 A CN201810676845 A CN 201810676845A CN 108923773 A CN108923773 A CN 108923773A
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- phase interpolator
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- 239000003990 capacitor Substances 0.000 claims description 3
- 238000005265 energy consumption Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 description 8
- 238000011084 recovery Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
Abstract
The present invention relates to IC design technical fields, a kind of low-power consumption adjustable type high linearity phase interpolator is provided, including phase interpolator, phase interpolator is formed in parallel by several interpolating units, interpolating unit is the selector of an alternative, two clock signal input mouths CK1 or CK2 of selector are equipped with enable end en and are motivated, the port t1-t4 of interpolating unit is connected separately with the resistance of similar resistance, and the resistance between different interpolating units is different, resistance is adjustable, and resistor coupled in parallel together and is externally connected to power end；The present invention is intended to provide a kind of clock phase interpolation for supporting 5GHz or more, and good, the linear phase interpolation circuit low in energy consumption and ultrahigh resolution with the linearity.
Description
Technical field
The present invention relates to circuit integration design fields, and in particular to a kind of low-power consumption adjustable type high linearity phase is slotting
It is worth device.
Background technique
Phase interpolator is as the key modules in clock data recovery circuit (CDR), the non-linear meeting of phase interpolator
The dynamic characteristic for directly affecting clock data recovery circuit also will affect when input data and local clock are there are when difference on the frequency
Its jitter toleration.Phase interpolator in high-speed signal transmission circuit for generating the clock of Accurate align.Work as transmission link
In without specific clock signal when, usually just clock data recovery circuit is needed to recover clock signal from data flow.
A kind of traditional implementation of phase interpolator is to mix phase with output loading.This phase interpolator
Design is that the difference based on a MOS current mode logic (MOS current mode logic, MCML) caches to realize.Through
The MCML logic of allusion quotation is mainly made of pulldown network switch, pull-up resistor and constant current a reference source three parts.Signal is with fully differential shape
Formula input, differential pulldown network are equivalent to the effect of switch, open one side access, another side path blockade, to drive partially
It sets electric current and flows only through one side access, then by pull-up resistor, realize the output of level.As shown in Figure 1, based on MCML logic
Caching generates differential output signal a VOUT+ and VOUT-, its two differential input signals are VIN+ and VIN-.Difference is negative
The input of load is voltage signal VL-BIAS, and differential source coupling is converted into output electric current to by input voltage.Biasing in differential pair
Electric current is provided by NMOS pull down resistor, is controlled by bias voltage VBIAS.But the phase interpolator resolution ratio of the prior art
It is lower, it is difficult to meet the needs of designing using practical application.
Summary of the invention
The technical issues of solution
In view of the deficiencies of the prior art, the present invention provides a kind of low-power consumption adjustable type high linearity phase interpolator, purports
A kind of clock phase interpolation for supporting 5GHz or more is being provided, and is having the linearity good, low in energy consumption and ultrahigh resolution linear
Phase-interpolation circuit.
Technical solution
In order to achieve the above object, the present invention is achieved by the following technical programs：
A kind of low-power consumption adjustable type high linearity phase interpolator, including phase interpolator, if the phase interpolator by
A dry interpolating unit is formed in parallel, and the interpolating unit is the selector of an alternative, two clocks letter of the selector
Number input port CK1 or CK2 are equipped with enable end en and are motivated, and the port t1-t4 of the interpolating unit is connected separately with phase
With the resistance of resistance value, and the resistance between different interpolating units is different, and the resistance is adjustable, the resistor coupled in parallel
Together and it is externally connected to power end.
Further, the clock input of the phase-interpolation unit is CK1 and CK2,8 45 ° of phase phase difference when
Clock signal CKi<8:1>Select a selector MUX4 through two four, selection obtain 45 ° of 2 phase phase differences clock signal CK1 and
CK2, the clock as phase-interpolation input.
Further, the external decoder of the selector, the selector control signal sel of the decoder output<4:1
>And sel<8:5>There was only 1 respectively for height, specific control logic is controlled by state machine.
Further, the input port CK1 and CK2 of the selector have the MOM capacitor of 1 200fF for being connected to ground
Load, the capacitive load are used for the rise and fall edge of smoothed clock signal, handle its phase convenient for phase interpolator.
Further, the enable signal en is 32 thermometer-codes, i.e., when each enable signal changes, 32 temperature
Meter code has and only 1 bit jumps.
Further, the quantity of the interpolating unit is 32, and is matched with 32 enable end en.
Beneficial effect
The present invention provides a kind of low-power consumption adjustable type high linearity phase interpolators, compared with existing well-known technique, this
Invention has the advantages that：
1, enable end en is cooperated to use 32 thermometer-codes by preferred 32 difference units in parallel, as long as therefore guaranteeing every
The corresponding phase changing capacity of a bit is consistent, also ensures that the preferable linearity；Multiple circuit simulation shows to adjust resistance
Resistance value is to guarantee the consistent effective way of phase changing capacity.The mechanism of this 32 thermometer-codes ensure that the linearity of phase；
And the gradually change of 32 thermometer-codes by decoder output, also it is achieved that 32 class resolution ratios of phase are adjusted, Ke Yiying
Low-power consumption linear interpolation is realized in the clock data recovery circuit based on phaselocked loop.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is traditional interpolator schematic diagram；
Fig. 2 is phase interpolator schematic diagram of the invention；(being wherein interpolating unit physical circuit figure in dotted line frame)
Fig. 3 is clock input circuit schematic diagram of the invention；
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without creative efforts, shall fall within the protection scope of the present invention.
Embodiment：
A kind of low-power consumption adjustable type high linearity phase interpolator of the present embodiment, including phase interpolator, phase-interpolation
Device is formed in parallel by several interpolating units, and the quantity of interpolating unit is 32, and is matched with 32 enable end en；Interpolating unit is
The selector of one alternative, two clock signal input mouths CK1 or CK2 of selector are equipped with enable end en and are swashed
It encourages, the port t1-t4 of interpolating unit is connected separately with the resistance of similar resistance, and the resistance between different interpolating units is not
Together, resistance is adjustable, and resistor coupled in parallel together and is externally connected to power end VDD.
The clock input of phase-interpolation unit is CK1 and CK2,8 45 ° of phase phase difference of clock signal CKi<8:1>Through
Two four are selected a selector MUX4, and selection obtains the clock signal CK1 and CK2 of 45 ° of 2 phase phase differences, as phase-interpolation
Clock input.
The external decoder of selector, the selector control signal sel of decoder output<4:1>And sel<8:5>Only have respectively
1 is height, and specific control logic is controlled by state machine.
The input port CK1 and CK2 of selector have the MOM capacitor load of 1 200fF for being connected to ground, and capacitive load is used
In the rise and fall edge of smoothed clock signal, its phase is handled convenient for phase interpolator.
Enable signal en is 32 thermometer-codes, i.e., when each enable signal changes, 32 thermometer-codes have and only 1
Bit jumps.
Enable end en is cooperated to use 32 thermometer-codes by preferred 32 difference units in parallel, as long as therefore guaranteeing each
The corresponding phase changing capacity of bit is consistent, also ensures that the preferable linearity；Multiple circuit simulation shows to adjust resistance resistance
Value is to guarantee the consistent effective way of phase changing capacity.The mechanism of this 32 thermometer-codes ensure that the linearity of phase；And
By the gradually change of 32 thermometer-codes of decoder output, also it is achieved that 32 class resolution ratios of phase are adjusted.
It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to the foregoing embodiments
Invention is explained in detail, those skilled in the art should understand that：It still can be to aforementioned each implementation
Technical solution documented by example is modified or equivalent replacement of some of the technical features；And these modification or
Replacement, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (6)
1. a kind of low-power consumption adjustable type high linearity phase interpolator, including phase interpolator, which is characterized in that the phase is inserted
Value device is formed in parallel by several interpolating units, the interpolating unit be an alternative selector, the two of the selector
A clock signal input mouth CK1 or CK2 are equipped with enable end en and are motivated, the port t1-t4 difference of the interpolating unit
It is connected with the resistance of similar resistance, and the resistance between different interpolating units is different, the resistance is adjustable, described
Resistor coupled in parallel together and is externally connected to power end.
2. a kind of low-power consumption adjustable type high linearity phase interpolator according to claim 1, which is characterized in that the phase
The clock input of position interpolating unit is CK1 and CK2,8 45 ° of phase phase difference of clock signal CKi<8:1>One is selected through two four
Selector MUX4, selection obtain the clock signal CK1 and CK2 of 45 ° of 2 phase phase differences, and the clock as phase-interpolation inputs.
3. a kind of low-power consumption adjustable type high linearity phase interpolator according to claim 1, which is characterized in that the choosing
Select the external decoder of device, the selector control signal sel of the decoder output<4:1>And sel<8:5>There was only 1 respectively is
Height, specific control logic are controlled by state machine.
4. a kind of low-power consumption adjustable type high linearity phase interpolator according to claim 1, which is characterized in that the choosing
The input port CK1 and CK2 for selecting device have the MOM capacitor load of 1 200fF for being connected to ground, and the capacitive load is for smooth
The rise and fall edge of clock signal handles its phase convenient for phase interpolator.
5. a kind of low-power consumption adjustable type high linearity phase interpolator according to claim 1, which is characterized in that described to make
Energy signal en is 32 thermometer-codes, i.e., when each enable signal changes, 32 thermometer-codes have and only 1 bit
Jump.
6. a kind of low-power consumption adjustable type high linearity phase interpolator according to claim 1, which is characterized in that described to insert
The quantity of value cell is 32, and is matched with 32 enable end en.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810676845.0A CN108923773A (en) | 2018-06-27 | 2018-06-27 | A kind of low-power consumption adjustable type high linearity phase interpolator |
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| CN201810676845.0A CN108923773A (en) | 2018-06-27 | 2018-06-27 | A kind of low-power consumption adjustable type high linearity phase interpolator |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111010175A (en) * | 2019-12-11 | 2020-04-14 | 浙江大学 | High-linearity phase interpolator |
| US10848299B2 (en) | 2018-12-29 | 2020-11-24 | Amlogic (Shanghai) Co., Ltd. | Phase interpolator |
| CN116846369A (en) * | 2023-06-09 | 2023-10-03 | 高澈科技(上海)有限公司 | Phase interpolator and electronic device |
-
2018
- 2018-06-27 CN CN201810676845.0A patent/CN108923773A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10848299B2 (en) | 2018-12-29 | 2020-11-24 | Amlogic (Shanghai) Co., Ltd. | Phase interpolator |
| CN111010175A (en) * | 2019-12-11 | 2020-04-14 | 浙江大学 | High-linearity phase interpolator |
| CN111010175B (en) * | 2019-12-11 | 2021-06-29 | 浙江大学 | High-linearity phase interpolator |
| CN116846369A (en) * | 2023-06-09 | 2023-10-03 | 高澈科技(上海)有限公司 | Phase interpolator and electronic device |
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Application publication date: 20181130 |