CN116846369A - Phase interpolator and electronic device - Google Patents
Phase interpolator and electronic device Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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Abstract
The application relates to the field of integrated circuit design, and discloses a phase interpolator and electronic equipment. The phase interpolator comprises a digital module and an interpolation module comprising a plurality of basic units, wherein each basic unit comprises a first interpolation circuit and a second interpolation circuit, one end of the first interpolation circuit is connected with a first power supply end, the other end of the first interpolation circuit is grounded, and a first resistor is arranged at one end of the first interpolation circuit connected with the first power supply end; the first interpolation circuit is used for charging or discharging according to a first input clock when being conducted; one end of the second interpolation circuit is connected with a second power end, the other end of the second interpolation circuit is grounded, and a second resistor is arranged at one end of the second interpolation circuit, which is connected with the second power end; the second interpolation circuit is used for charging or discharging according to a second input clock when being conducted; the weight factors are used for controlling the first interpolation circuit or the second interpolation circuit to be conducted, so that the interpolation module generates interpolation clocks with different phases based on the output of each basic unit, and the linearity of the phase interpolator is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of integrated circuit design, in particular to a phase interpolator and electronic equipment.
Background
The phase interpolator (Phase Interpolator, PI), as the name implies, works by interpolating the phase. The phase interpolator requires a plurality of input clocks of different phases, typically four-phase or eight-phase, and then selects two adjacent input phases, performs weighted interpolation on them, and can output clocks of any phase by adjusting the weights of the two phases.
However, in some application scenarios, the linearity requirement of the phase interpolator is high, and the current phase interpolator cannot meet the requirement.
Disclosure of Invention
The embodiment of the application aims to provide a phase interpolator and electronic equipment, which can improve the linearity of the phase interpolator and meet the scene of the linearity requirement of the high phase interpolator.
In order to solve the technical problems, an embodiment of the present application provides a phase interpolator, including a digital module and an interpolation module including a plurality of basic units, where the digital module is connected with the interpolation module; the digital module is used for generating a weight factor according to a preset binary signal and inputting the weight factor to the interpolation module; each basic unit comprises a first interpolation circuit and a second interpolation circuit, one end of the first interpolation circuit is connected with a first power end, the other end of the first interpolation circuit is grounded, and a first resistor is arranged at one end, connected with the first power end, of the first interpolation circuit; the first interpolation circuit is used for charging or discharging according to a preset first input clock when being conducted; one end of the second interpolation circuit is connected with a second power end, the other end of the second interpolation circuit is grounded, and a second resistor is arranged at one end of the second interpolation circuit, which is connected with the second power end; the second interpolation circuit is used for charging or discharging according to a preset second input clock when being conducted; the weight factors are used for controlling the first interpolation circuit or the second interpolation circuit to be conducted so that the interpolation module can generate interpolation clocks with different phases based on the output of the basic units.
The embodiment of the application also provides electronic equipment comprising the phase interpolator.
The phase interpolator comprises a digital module and an interpolation module comprising a plurality of basic units, wherein the digital module is used for generating a weight factor according to a preset binary signal and inputting the weight factor to the interpolation module, each basic unit comprises a first interpolation circuit and a second interpolation circuit, one end of the first interpolation circuit is connected with a first power end, the other end of the first interpolation circuit is grounded, a first resistor is arranged at one end of the first interpolation circuit connected with the first power end, and the first interpolation circuit is used for charging or discharging according to a preset first input clock when the first interpolation circuit is conducted; one end of the second interpolation circuit is connected with a second power end, the other end of the second interpolation circuit is grounded, a second resistor is arranged at one end of the second interpolation circuit, which is connected with the second power end, and the second interpolation circuit is used for charging or discharging according to a preset second input clock when the second interpolation circuit is conducted; the weight factors are used for controlling the first interpolation circuit or the second interpolation circuit to be conducted so that the interpolation module generates interpolation clocks with different phases based on the output of each basic unit. Through setting up first resistance in the one end that first interpolation circuit and first power end are connected, the one end that second interpolation circuit and second power end are connected sets up the second resistance, makes first interpolation circuit and second interpolation circuit in the charging process, and the rate of charging reduces, and first interpolation circuit and second interpolation circuit charging curve's slope is more stable to promote the linearity of phase interpolator, satisfy the scene of high phase interpolator linearity demand.
In addition, the first interpolation circuit comprises a first charging loop, a first discharging loop and an OUT node, one end of the first charging loop is connected with the first power end, the other end of the first charging loop is connected with the OUT node, one end of the first discharging loop is connected with the OUT node, and the other end of the first discharging loop is grounded; when the first interpolation circuit is conducted, the first charging loop charges the OUT node according to the first input clock, or the OUT node is discharged to the ground through the first discharging loop; the second interpolation circuit comprises a second charging loop, a second discharging loop and an OUT node, one end of the second charging loop is connected with the second power end, the other end of the second charging loop is connected with the OUT node, one end of the second discharging loop is connected with the OUT node, and the other end of the second discharging loop is grounded; and when the second interpolation circuit is conducted, the second charging loop charges the OUT node according to the second input clock, or the OUT node is discharged to the ground through the second discharging loop.
In addition, one end of the first charging loop connected with the OUT node is provided with a third resistor, and one end of the second charging loop connected with the OUT node is provided with a fourth resistor, so that the linearity of the phase interpolator is further improved.
In addition, the phase interpolator also comprises an adjusting module, and the adjusting module is connected with the interpolation module; the interpolation module is also used for inputting the generated interpolation clock to the adjustment module; the adjusting module is used for adjusting the current clock frequency of the interpolation clock according to a preset control signal so as to generate an interpolation clock with a target clock frequency, and therefore the output clock frequency of the phase interpolator can be adjusted arbitrarily.
In addition, the adjusting module comprises at least one capacitor, generates a delay signal by charging at least one capacitor, and adjusts the current clock frequency of the interpolation clock according to the delay signal so as to improve the adjusting range of the output clock frequency of the phase interpolator.
In addition, the weight factors include a first weight factor and a second weight factor, the first weight factor and the second weight factor being complementary.
In addition, the digital module is further configured to input the first weight factor and the second weight factor to the interpolation module synchronously, so as to meet a timing requirement of the phase interpolator.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
FIG. 1 is a schematic diagram of a phase interpolator according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a basic unit according to one embodiment of the present application;
FIG. 3 is a schematic diagram of a basic unit according to an embodiment of the present application;
fig. 4 is a schematic diagram of a phase interpolator according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the claimed technical solution of the present application can be realized without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the present application, and the embodiments can be mutually combined and referred to without contradiction.
One embodiment of the application relates to a phase interpolator, which comprises a digital module and an interpolation module comprising a plurality of basic units, wherein the digital module is used for generating a weight factor according to a preset binary signal and inputting the weight factor to the interpolation module, each basic unit comprises a first interpolation circuit and a second interpolation circuit, one end of the first interpolation circuit is connected with a first power end, the other end of the first interpolation circuit is grounded, a first resistor is arranged at one end of the first interpolation circuit connected with the first power end, and the first interpolation circuit is used for charging or discharging according to a preset first input clock when being conducted; one end of the second interpolation circuit is connected with a second power end, the other end of the second interpolation circuit is grounded, a second resistor is arranged at one end of the second interpolation circuit, which is connected with the second power end, and the second interpolation circuit is used for charging or discharging according to a preset second input clock when the second interpolation circuit is conducted; the weight factors are used for controlling the first interpolation circuit or the second interpolation circuit to be conducted so that the interpolation module generates interpolation clocks with different phases based on the output of each basic unit. Through setting up first resistance in the one end that first interpolation circuit and first power end are connected, the one end that second interpolation circuit and second power end are connected sets up the second resistance, makes first interpolation circuit and second interpolation circuit in the charging process, and the rate of charging reduces, and first interpolation circuit and second interpolation circuit charging curve's slope is more stable to promote the linearity of phase interpolator, satisfy the scene of high phase interpolator linearity demand.
The implementation details of the phase interpolator of the present embodiment are specifically described below, and the following is merely provided for understanding the implementation details, and is not necessary to implement the present embodiment.
The architecture of the phase interpolator of the present embodiment may include, as shown in fig. 1: the digital module 1 is connected with the interpolation module 2. Wherein the interpolation module comprises a plurality of basic units 21 (only 3 basic units are shown in the figure).
Specifically, the digital module 1 is configured to receive a preset binary signal input from the outside, convert the binary signal into a thermometer code, and generate a weight factor according to the thermometer code, so that the preset binary signal determines the size of the generated weight factor, and then the digital module 1 inputs the generated weight factor into the interpolation module 2. The interpolation module 2 is configured to receive a preset first input clock and a preset second input clock, where the first input clock and the second input clock have the same frequency but a phase difference, for example, the phase of the first input clock is 90 °, the phase of the second input clock is 45 °, and the interpolation module 2 is configured to perform phase interpolation on the first input clock and the second input clock according to the weight factor sent by the digital module 1, so as to output interpolation clocks with different phases between the phases of the first input clock and the second input clock. The weight factors include a first weight factor and a second weight factor, the first weight factor is a weight factor of the first input clock, the second weight factor is a weight factor of the second input clock, and the digital module 1 can ensure that the generated first weight factor and the generated second weight factor are complementary, for example, the first weight factor s1=0, and the second weight factor s2=1. In some embodiments, if a part of the application scenario has a requirement on the timing of the phase interpolator, the digital module 1 is further configured to input the first weight factor and the second weight factor into the interpolation module 2 synchronously.
The plurality of basic units 2 of the interpolation module 2 work separately, for example, the interpolation module 2 includes 64 basic units, which means that the resolution of the interpolation module 2 is 1/64, and the interpolation module 2 can divide the phase difference between the first input clock and the second input clock into 64 shares, then perform interpolation separately, and finally the interpolation module 2 superimposes the outputs of the basic units 21 to obtain a final interpolation clock. A schematic structural view of each base unit 21 can be seen in fig. 2, including: a first interpolation circuit 211 and a second interpolation circuit 212.
One end of the first interpolation circuit 211 is connected to the first power supply terminal VDD1, the other end is grounded, and a first resistor R1 is disposed at the end of the first interpolation circuit 211 connected to the first power supply terminal VDD1, and the first interpolation circuit 211 is configured to charge or discharge according to a preset first input clock In1 when turned on. One end of the second interpolation circuit 212 is connected to the second power supply terminal VDD2, the other end is grounded, and a second resistor R2 is disposed at the end of the second interpolation circuit 212 connected to the second power supply terminal VDD2, and the second interpolation circuit 212 is configured to charge or discharge according to a preset second input clock In2 when turned on. Wherein the weight factor is used to control the first interpolation circuit 211 or the second interpolation circuit 212 to be turned on, that is, the conduction of the first interpolation circuit 211 or the second interpolation circuit 212 of all the basic units 21 in the interpolation module 2 can be controlled by the weight factor to determine the conduction quantity of the first interpolation circuit 211 and the second interpolation circuit 212 which are finally turned on. Therefore, the interpolation module 2 can generate interpolation clocks of different phases based on the outputs of the respective basic units 21 by controlling the difference in the number of the turned-on first interpolation circuits 211 or second interpolation circuits 212 by the weight factors. In some embodiments, the first power supply terminal VDD1 and the first power supply terminal VDD1 are the same power supply terminal, and the resistances of the first resistor R1 and the second resistor R2 are equal.
When the first power supply terminal VDD1 charges the first interpolation circuit 211 that is turned on, since the first resistor R1 is disposed at the end of the first interpolation circuit 211 that is connected to the first power supply terminal VDD1, the charging rate of the first power supply terminal VDD1 to the first interpolation circuit 211 is slow, and after the first interpolation circuit 211 is charged, the discharging rate is fast when the first interpolation circuit 211 is discharged. The second interpolation circuit 212 is also configured such that when the second power supply terminal VDD2 charges the turned-on second interpolation circuit 212, the second resistor R2 is disposed at the end of the second interpolation circuit 2112 connected to the second power supply terminal VDD2, so that the charging rate of the second power supply terminal VDD2 to the second interpolation circuit 212 is slow, and when the second interpolation circuit 212 is discharged after the second interpolation circuit 212 is charged, the discharging rate is fast. Therefore, the slopes of the charging curves of the first interpolation circuit 211 and the second interpolation circuit 212 are more stable, thereby improving the linearity of the phase interpolator.
In some embodiments, as shown in fig. 2, the first interpolation circuit 211 includes a first charging loop 311, a first discharging loop 312, and an OUT node 313, where one end of the first charging loop 311 is connected to the first power source terminal VDD1, the other end is connected to the OUT node 313, one end of the first discharging loop 312 is connected to the OUT node 313, and the other end is grounded. When the first interpolation circuit 211 is turned on, the first charging circuit 311 charges the OUT node 313 according to the first input clock In1, and after the charging is completed, the OUT node 313 is discharged to the ground through the first discharging circuit 312. The second interpolation circuit 212 includes a second charging loop 411, a second discharging loop 412, and an OUT node 313, where one end of the second charging loop 411 is connected to the second power supply terminal VDD2, the other end is connected to the OUT node 313, and one end of the second discharging loop 412 is connected to the OUT node 313, and the other end is grounded. When the second interpolation circuit 212 is turned on, the second charging circuit 411 charges the OUT node 313 according to the second input clock In2, and after the charging is completed, the OUT node 313 is discharged to the ground through the second discharging circuit 412.
In a specific implementation, the digital module 1 is configured to generate four weight factors according to a preset binary signal, a first weight factor S1 and a third weight factor Sb1 of a first input clock, and a second weight factor S2 and a fourth weight factor Sb2 of a second input clock. The first weight factor S1 and the second weight factor S2 are complementary, and the first weight factor S1 and the third weight factor Sb1 are complementary, the first weight factor S1 is used for controlling the conduction of the first charging circuit 311, the third weight factor Sb1 is used for controlling the conduction of the first discharging circuit 312, the second weight factor S2 is used for controlling the conduction of the second charging circuit 411, and the fourth weight factor Sb2 is used for controlling the conduction of the second discharging circuit 412.
For ease of understanding, the following description is given below for the operation of each base unit 21 in conjunction with fig. 2:
assuming that the first input clock In1 leads the second input clock In2, when the first weight factor s1=1, the third weight factor s1=0, the second weight factor s2=0, and the fourth weight factor s2=1, at this time, the first charging loop 311 is conductive, the first discharging loop 312 is non-conductive, the second charging loop 411 is non-conductive, and the second discharging loop 412 is conductive. When the rising edge of the first input clock In1 arrives, since the first charging circuit 311 is turned on, the first power supply terminal VDD1 may charge the OUT node 313 through the first charging circuit 311, and the OUT node 313 may be discharged to the ground through the first discharging circuit 312 when the falling edge of the first input clock In1 arrives. On the contrary, assuming that the second input clock In2 leads the first input clock In1, when the first weight factor s1=0, the third weight factor s1=1, the second weight factor s2=1, and the fourth weight factor s2=0, at this time, the first charging loop 311 is not turned on, the first discharging loop 312 is turned on, the second charging loop 411 is turned on, and the second discharging loop 412 is not turned on. When the rising edge of the second input clock In2 arrives, since the second charging circuit 411 is turned on, the second power supply terminal VDD2 can charge the OUT node 313 through the second charging circuit 411, and the OUT node 313 is discharged to the ground through the second discharging circuit 412 when the falling edge of the second input clock In2 arrives.
In one example, the first charging loop 311 and the second charging loop 411 may be regarded as PMOS transistors, and the first discharging loop 312 and the second discharging loop 412 may be regarded as NMOS transistors, so that when a rising edge of the clock arrives, all PMOS transistors are turned on, all NMOS transistors are turned off, and when a falling edge of the clock arrives, all NMOS transistors are turned on, and all PMOS transistors are turned off.
In some embodiments, as shown in fig. 3, on the basis of the above embodiments, a third resistor R3 is disposed at the end of the first charging loop 311 connected to the OUT node 313, and a fourth resistor R4 is disposed at the end of the second charging loop 411 connected to the OUT node 313, so that the charging rate of the charging loop can be further reduced, and the linearity of the phase interpolator is further improved.
In one example, the third resistor R3 and the fourth resistor R4 have equal resistance values.
In some embodiments, the phase interpolator further includes an adjusting module 3 as shown in fig. 4, where the adjusting module 3 is connected to the interpolating module 2, and the interpolating module 2 is further configured to input the generated interpolation clock to the adjusting module 3, and the adjusting module 3 is configured to adjust the current clock frequency of the interpolation clock according to a preset control signal, so as to generate the interpolation clock with the target clock frequency.
In one example, the adjustment module 3 comprises at least one capacitor, and the adjustment module 3 generates the delay signal by charging the at least one capacitor and adjusts the current clock frequency of the interpolation clock according to the delay signal.
The adjusting module of the embodiment not only can adjust the frequency of the interpolation clock generated by the interpolation module 2, but also can increase or decrease the number of capacitors to increase the adjustable range of the frequency of the interpolation clock.
It should be noted that, the foregoing examples in the present embodiment are all examples for understanding and are not limited to the technical solution of the present application.
Another embodiment of the present application relates to an electronic device comprising a phase interpolator as described in any of the above embodiments.
It is to be noted that this embodiment is an apparatus embodiment corresponding to the above-described phase interpolator embodiment, and can be implemented in cooperation with the above-described phase interpolator embodiment. The related technical details and technical effects mentioned in the above embodiments are still valid in this embodiment, and in order to reduce repetition, they are not described here again. Accordingly, the related technical details mentioned in the present embodiment can also be applied to the above-described embodiments.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the application and that various changes in form and details may be made therein without departing from the spirit and scope of the application.
Claims (8)
1. A phase interpolator, comprising: the system comprises a digital module and an interpolation module comprising a plurality of basic units, wherein the digital module is connected with the interpolation module;
the digital module is used for generating a weight factor according to a preset binary signal and inputting the weight factor to the interpolation module;
each basic unit comprises a first interpolation circuit and a second interpolation circuit, one end of the first interpolation circuit is connected with a first power end, the other end of the first interpolation circuit is grounded, and a first resistor is arranged at one end, connected with the first power end, of the first interpolation circuit; the first interpolation circuit is used for charging or discharging according to a preset first input clock when being conducted;
one end of the second interpolation circuit is connected with a second power end, the other end of the second interpolation circuit is grounded, and a second resistor is arranged at one end of the second interpolation circuit, which is connected with the second power end; the second interpolation circuit is used for charging or discharging according to a preset second input clock when being conducted; the weight factors are used for controlling the first interpolation circuit or the second interpolation circuit to be conducted so that the interpolation module can generate interpolation clocks with different phases based on the output of the basic units.
2. The phase interpolator of claim 1, wherein the first interpolation circuit comprises a first charging loop, a first discharging loop, and an OUT node, one end of the first charging loop is connected to the first power supply terminal, the other end is connected to the OUT node, one end of the first discharging loop is connected to the OUT node, and the other end is grounded; when the first interpolation circuit is conducted, the first charging loop charges the OUT node according to the first input clock, or the OUT node is discharged to the ground through the first discharging loop;
the second interpolation circuit comprises a second charging loop, a second discharging loop and an OUT node, one end of the second charging loop is connected with the second power end, the other end of the second charging loop is connected with the OUT node, one end of the second discharging loop is connected with the OUT node, and the other end of the second discharging loop is grounded; and when the second interpolation circuit is conducted, the second charging loop charges the OUT node according to the second input clock, or the OUT node is discharged to the ground through the second discharging loop.
3. The phase interpolator of claim 2, wherein a third resistor is provided at an end of the first charge loop connected to the OUT node and a fourth resistor is provided at an end of the second charge loop connected to the OUT node.
4. The phase interpolator of claim 1, further comprising an adjustment module coupled to the interpolation module;
the interpolation module is also used for inputting the generated interpolation clock to the adjustment module;
the adjusting module is used for adjusting the current clock frequency of the interpolation clock according to a preset control signal so as to generate an interpolation clock with a target clock frequency.
5. The phase interpolator of claim 4, wherein the adjustment module comprises at least one capacitor, the adjustment module generating a delay signal by charging at least one of the capacitors, and adjusting a current clock frequency of the interpolation clock based on the delay signal.
6. The phase interpolator of any of claims 1 to 5, wherein the weight factors comprise a first weight factor and a second weight factor, the first weight factor and the second weight factor being complementary.
7. The phase interpolator of claim 6, wherein said digital module is further configured to input said first weight factor and said second weight factor into said interpolation module synchronously.
8. An electronic device comprising a phase interpolator as claimed in any of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310687506.3A CN116846369A (en) | 2023-06-09 | 2023-06-09 | Phase interpolator and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310687506.3A CN116846369A (en) | 2023-06-09 | 2023-06-09 | Phase interpolator and electronic device |
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| US20090163166A1 (en) * | 2007-12-21 | 2009-06-25 | Realtek Semiconductor Corp. | Phase lock loop with phase interpolation by reference clock and method for the same |
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| CN109217850A (en) * | 2018-08-13 | 2019-01-15 | 上海奥令科电子科技有限公司 | A kind of digital control single-stage multi-clock phase interpolator of stable duty ratio |
| JP2019022136A (en) * | 2017-07-20 | 2019-02-07 | ローム株式会社 | Phase interpolator and timing generator, semiconductor integrated circuit |
| CN109981086A (en) * | 2018-12-29 | 2019-07-05 | 晶晨半导体(上海)股份有限公司 | A kind of phase interpolator |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090163166A1 (en) * | 2007-12-21 | 2009-06-25 | Realtek Semiconductor Corp. | Phase lock loop with phase interpolation by reference clock and method for the same |
| JP2019022136A (en) * | 2017-07-20 | 2019-02-07 | ローム株式会社 | Phase interpolator and timing generator, semiconductor integrated circuit |
| CN108923773A (en) * | 2018-06-27 | 2018-11-30 | 重庆湃芯入微科技有限公司 | A kind of low-power consumption adjustable type high linearity phase interpolator |
| CN109217850A (en) * | 2018-08-13 | 2019-01-15 | 上海奥令科电子科技有限公司 | A kind of digital control single-stage multi-clock phase interpolator of stable duty ratio |
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